JPH0290348A - Cache memory system with variable data invalidation size - Google Patents

Abstract

PURPOSE:To improve the performance of a cache memory system by preparing a valid bit clear instruction circuit and a pulse generating circuit which produces a pulse to clear the valid bit. CONSTITUTION:A write pulse given from a valid bit memory 1 is equal to a pulse signal 701 given from a pulse generating circuit 7. The circuit 7 works with input of a bus clock signal 171 and an instruction signal 601 given from a valid bit clear instruction circuit 6. The circuit 6 compares an external address with a tag address of a cache memory and instructs a valid bit clear operation of the corresponding data when the coincidence is secured between both addresses. An address latch 5 inputs entirely an address signal group 151 via an address signal group terminal 15. A 4-bit valid clear selection signal 801 is set at 0 through an inverter 8 when a 4-bit valid bit clear selection terminal 16 is equal to 1. Thus a valid bit can be cleared for each type in response to the rewrite byte of a main memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory system with variable data invalidation size.

[Conventional technology]

Conventional cache memory systems manage the validity of stored data by setting a valid bit for each size of data, and when the valid bit is "1", the data is valid, and when it is "0°". In some cases, the method is to invalidate it. When setting the valid bit to 1″, set the CPU
This is when data is stored from the main memory into the cache memory in response to a request from the main memory, or when cleared to 0°'. This is when it is rewritten by a processor or controller.

When clearing to "0", there are two methods: clearing all valid bits with a command, and clearing each unit of data stored from the main memory to the cache memory, called block size.

[Problem to be solved by the invention]

In the conventional cache memory described above, for example, if the block size is set to 16 bytes in order to increase the hit rate, 16 bytes will be cleared all at once. However, if the main memory bus size is 4 bytes, the main memory rewrite that caused the clearing of "0" is probably 4 bytes per rewrite from the processor, and the rewrite from the DMA controller. However, it is not limited to 16-byte transfer by burst transfer, and single-byte transfer is also possible.

Therefore, it is very inefficient to clear all 16 bytes at once by rewriting the main memory once, as in the past, when clearing 1 byte out of 4 bytes is sufficient. This is because data stored in the cache memory has a high probability of being read and accessed by the CPU many times, so once it is cleared, the data must be retrieved from the main memory to the cache memory again. This has the disadvantage of reducing system performance.

An object of the present invention is to provide a cache memory that has a function of accepting instructions for the number of valid bits to be cleared according to the rewritten data size of the main memory, and that allows selection of clearing of a single valid bit or a plurality of valid bits. The goal is to provide a system.

[Means to solve the problem]

The data invalidation size variable cache memory system of the present invention includes a valid pit memory containing valid bits prepared for each byte of data memory of an arbitrary size, and a latch that temporarily stores an address for data invalidation from the outside. or a counter, a decoder that decodes a part of the address signal from the latch or counter, a valid bit clear instruction circuit that starts valid bit clearing, and a circuit that generates a pulse for valid bit clearing; and a circuit for selecting whether to clear a valid bit or to clear a plurality of valid bits.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, showing only the parts related to the present invention. Valid bit memory 1 and data memory 2 are connected to address latch 5.
A word is selected by a set address decode signal group 301, . . . 30n, . Each word in valid pit memory 1 consists of 4 valid bits, data memory 2 consists of 4 bytes of data, and valid bits 0, V
l, V2. V3 is data Do and Di, respectively.

D2. Corresponds to D3. Valid bit clearing of valid pit memory 1 is performed by valid bit signal group I401.4, which is obtained by decoding signals 502.503 from valid addresses 1 and 0, which are part of latch 5, by decoder 4.
02,403,404.

For example, when valid addresses 0 and 1 are "00", the signal groups I401, 402, 403, and 404 become "0", "1" II I II, and "1", respectively.

NAND gates 11, 12, 13, and 14 are controlled by valid bit signal groups 11111, 121, 131, and 141 by a 4-bit valid bit clear selection signal 801.

For example, when the signal 801 is O'', the signal group ■111.12
1,131,141 is o, o, o.

When the signal 801 is "1", the signal group I401.
Determined by 402, 403, 404, signal group engineer and ■
are 401, 402, 403°404 and 111, respectively.
121, 131, and 141 correspond to the same value.

The write pulse for the valid bit memory 1 is a pulse signal 701 from the pulse generation circuit 7.

The pulse generation circuit 7 is operated by inputting the pass clock signal 171 and the instruction signal 601 from the valid bit clear instruction circuit 6. The instruction circuit 6 is a circuit that compares the address from the outside with the tag address of the cache memory, and when they match, instructs to clear the valid bit of the corresponding data. Address latch 5 is address signal group terminal 15
The entire address signal group 151 is input from. The 4-bit/valid bit clear selection signal 801 passes through the inverter 8 and becomes "0'" when the 4-bit/valid bit clear selection terminal 16 is "1". Pass clock signal 171
inputs the pass clock from the pass clock terminal 17.

FIG. 2 is a timing chart in which the valid bit is cleared by the signals 502 and 503 from the address latch 5 when the selection signal 801 is "o". In the example where the signals 502 and 503 are 00, the decoder 4 converts the signal groups 11111, 121°131.141 into 0.1, 1, .
Becomes 1. When the clear instruction signal 601 reaches ``11'', the valid bit v is cleared at the timing of the trailing edge of the pulse signal 701.
O2Vl, V2. If the previous state of V3 is all "1", it becomes 0, 1, 1.1.

FIG. 3 is a timing chart when the selection signal 801 matches '11' and the signals 502 and 50 from the address latch 5.
3, the signal group (2) is all "0", the clear instruction signal 601 is "1"', and the valid bits are all "0" at the timing of the trailing edge of the pulse signal 701.
become. Therefore, for example, if you want to clear the data in 1 byte of cache memory, you can set the 4 byte valid pit clear selection terminal 16 to "0°', and if you want to clear the data in 4 bytes of cache memory, The clear selection terminal 16 may be set to "1".

FIG. 4 is a circuit diagram showing a second embodiment of the present invention, showing only the parts related to the present invention.

The difference from the first embodiment is that when clearing 4 bits,
It has an address counter and a circuit that generates four pulses. In other words, in the first embodiment, four valid bits are cleared at the same time, but in this embodiment, the addresses are counted up (wraparound) in synchronization with the pass clock, and the valid bits are cleared in order by four pulses. Clearing is in progress. This embodiment has the advantage that power supply noise caused by simultaneous clear operations is alleviated.

〔Effect of the invention〕

As explained above, the present invention compares an address for invalidating data given from the outside with an address tag, and if they match, clears the valid bit associated with the corresponding data. In a cache system that has a function to invalidate data, the data memory has a valid pit memory containing valid bits prepared for each byte of an arbitrary size, and a latch or counter that temporarily stores an address for invalidating data from the outside. , a decoder that decodes a part of the address signal from the latch or counter, a valid bit clear instruction circuit that starts valid bit clearing, a circuit that generates a pulse for valid bit clearing, and a single valid bit. By configuring it with a circuit that selects whether to clear or clear multiple valid bits, valid pits can be cleared for each byte according to the rewritten byte of the main memory, improving the performance of the cache memory system. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the first embodiment of the present invention, and FIG. 2 is a timing chart when clearing in 1-byte units.
FIG. 3 is a timing chart when 4 bytes are simultaneously cleared, and FIG. 4 is a block diagram of the second embodiment of the present invention.
FIG. 5 is a timing chart for clearing 4 bytes with 4 pulses. DESCRIPTION OF SYMBOLS 1... Valid pit memory, 2... Data memory, 3, 4... Decoder, 5... Latch, 6... Instruction circuit, 7... Pulse generation circuit, 8... Inverter, 11, 12, 13. 14...AND gate, 15,
16.17...Terminal, 21...Pulse generation circuit, 2
2...Selector, 23...Counter, 31. ．． 32
, 33° 34...AND gate, 311, 321, 3
31°341...Partial write pulse signal, 30
1°...30n,...30m...Set address decode signal group, 401, 402, 403, 404...
- Valid pit signal group, 501... Set address signal group, 502, 503... Valid address signal group, 111.121, 131, 141... Valid bit signal group ■, 601... Valid pit clear Instruction signal, 701...1 pulse signal, 211...4 pulse signal, 161...pass clock signal, 171.
・・4-byte valid bit clear selection signal, 151・
...address signal group.

Claims (1)

[Claims] In a cache system that has the function of checking an address tag for invalidating data given from the outside, and invalidating the corresponding data by clearing the valid bit attached to the data if there is a match,
A valid bit memory containing valid bits prepared for each byte in a data memory of an arbitrary size, a latch or counter that temporarily stores an address for invalidating data from the outside, and one address signal from the latch or counter. a decoder that decodes a valid bit, a valid bit clear instruction circuit that starts valid bit clearing, a circuit that generates a pulse for clearing the valid bit, and a circuit that clears a single valid bit or clears multiple valid bits. A data invalidation size variable cache memory system, comprising: a circuit for selecting data invalidation size.