JPH0310237B2 - - Google Patents
Info
- Publication number
- JPH0310237B2 JPH0310237B2 JP60195097A JP19509785A JPH0310237B2 JP H0310237 B2 JPH0310237 B2 JP H0310237B2 JP 60195097 A JP60195097 A JP 60195097A JP 19509785 A JP19509785 A JP 19509785A JP H0310237 B2 JPH0310237 B2 JP H0310237B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- circuits
- frequency
- semiconductor integrated
- amplification
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体集積回路に関し、特に回路
間のセパレーシヨンを悪化させることなく2つ以
上の高周波回路を、1つの半導体ペレツト上に搭
載できるようにしたものに関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuits, and in particular, to a method that allows two or more high-frequency circuits to be mounted on one semiconductor pellet without deteriorating the separation between the circuits. This is related to things that have been done in this way.
従来、半導体集積回路において、2つ以上の回
路を1つのペレツトに搭載する場合、高い周波数
信号を取り扱う場合であつても、それに応じた配
慮が全くなされておらず、内部回路に印加する信
号周波数の高い、低いに関係なく、同様の回路配
置としており、このため回路間のセパレーシヨン
が悪かつた。又セパレーシヨンが悪いために回路
要求を満足しないことから、利得の大きな回路を
複数作り込むことができず、小利得の回路しか1
ペレツトに搭載できないものであつた。
Conventionally, in semiconductor integrated circuits, when two or more circuits are mounted on one pellet, even when handling high frequency signals, no consideration has been given to the signal frequency applied to the internal circuit. The circuit arrangement was the same regardless of whether the voltage was high or low, resulting in poor separation between the circuits. Also, because the circuit requirements are not satisfied due to poor separation, it is not possible to create multiple circuits with large gains, and only one circuit with small gains is required.
It could not be loaded into pellets.
従来の半導体集積回路は、以上のように構成さ
れており、高い信号周波数を通す回路を搭載する
にもかかわらず、それに応じた配慮を全くしてい
ないことから、回路間のセパレーシヨンが悪く、
従つて利得が大きく高い周波数を扱う2回路以上
の回路の1チツプIC化は実現できないものであ
つた。
Conventional semiconductor integrated circuits are configured as described above, and although they are equipped with circuits that pass high signal frequencies, no consideration has been given to this, resulting in poor separation between circuits.
Therefore, it has been impossible to integrate two or more circuits with large gains and handle high frequencies into a single chip IC.
この発明は上記のような問題点を解消するため
になされたもので、回路間のセパレーシヨンを保
ちながら複数の高周波回路を1チツプ上に搭載で
きる半導体集積回路を得ることを目的とする。 The present invention has been made to solve the above-mentioned problems, and its object is to provide a semiconductor integrated circuit that can mount a plurality of high-frequency circuits on one chip while maintaining separation between the circuits.
この発明に係る半導体集積回路は、高周波回路
間に、干渉に強い回路を設けるかあるいはインピ
ーダンスの低い電源・アースライン等の配線領域
を走らせるようにしたものである。
In the semiconductor integrated circuit according to the present invention, a circuit resistant to interference is provided between high-frequency circuits, or wiring areas such as low-impedance power supply lines and ground lines are run between the high-frequency circuits.
この発明においては、各高周波回路間に高周波
回路による干渉を受けにくい回路または各高周波
回路の周辺に低インピーダンスの配線領域が設け
られているから、干渉を受けにくい回路を設けた
場合、高周波回路間の距離が長くなることにより
該回路間を飛び交う信号が減衰し、また低インピ
ーダンスの配線領域を設けた場合、高周波回路間
を飛び交う信号が該配線領域に落ちるから、高周
波回路の受ける影響が少なくなる。
In this invention, a low-impedance wiring area is provided between each high-frequency circuit and a circuit that is not susceptible to interference by the high-frequency circuit or around each high-frequency circuit. As the distance increases, the signals flying between the circuits are attenuated, and if a low-impedance wiring area is provided, the signals flying between the high-frequency circuits fall into the wiring area, which reduces the effect on the high-frequency circuits. .
以下、この発明の一実施例を図について説明す
る。第1図は本発明の一実施例による半導体集積
回路を示し、図において、1は電気回路を搭載す
るかあるいは埋め込むための基板で、現在基板の
材料としてシリコン(Si)、ガリウム砒素
(GaAs)等の半導体が用いられることが多いこ
とから、半導体ペレツトと呼ぶ。また2〜9はボ
ンデイングパツドと呼ばれる、内部回路A〜Gの
信号を入出力するための端子であつて、3,4,
5は電気回路C,A,Bの正電圧電源又は負電圧
電源用の端子、6,7は電気回路Dの信号入力端
子、8,9は電気回路Eの信号入力端子である。
なお2は3〜9以外の内部回路A〜Gに接続され
ているボンデイングパツドである。
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, 1 is a substrate on which an electric circuit is mounted or embedded. Currently, silicon (Si), gallium arsenide (GaAs) is used as the substrate material. Since semiconductors such as these are often used, they are called semiconductor pellets. Further, 2 to 9 are terminals called bonding pads for inputting and outputting signals from internal circuits A to G.
5 is a terminal for a positive voltage power supply or a negative voltage power supply of the electric circuits C, A, and B; 6 and 7 are signal input terminals of the electric circuit D; and 8 and 9 are signal input terminals of the electric circuit E.
Note that 2 is a bonding pad connected to internal circuits A to G other than 3 to 9.
またAは高周波増幅回路で、増幅回路E,Gを
含む回路、Bは高周波増幅回路で増幅回路D,F
を含む回路である。 Also, A is a high frequency amplification circuit, which includes amplification circuits E and G, and B is a high frequency amplification circuit, which includes amplification circuits D and F.
This is a circuit that includes
また第2図は本発明の他の実施例による半導体
集積回路を示し、図において、第1図と同一符号
は同一のものを示す。10,11は増幅回路Dの
正電圧電源又は負電圧電源端子である。即ち、第
1図のものでは回路D,Fの電源は端子5を介し
て供給されているが、第2図のものでは回路Dの
電源は端子10,11を介して、回路Fの電源は
端子5を介して供給されている。なお、H,Iは
回路D,Eと端子10,11とをつなぐ低インピ
ーダンスの配線領域である。 Further, FIG. 2 shows a semiconductor integrated circuit according to another embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 1 indicate the same parts. 10 and 11 are positive voltage power supply terminals or negative voltage power supply terminals of the amplifier circuit D. That is, in the one shown in FIG. 1, the power to circuits D and F is supplied through terminal 5, but in the one shown in FIG. It is supplied via terminal 5. Note that H and I are low impedance wiring areas that connect the circuits D and E and the terminals 10 and 11.
次に作用効果について説明する。 Next, the effects will be explained.
ダイバシチ回路とは、第1図に示すように送信
用増幅回路または受信用増幅回路を2系列以上設
けたものであり、A,Bの2系列が同じ電気的特
性を示す必要があることから、A,B両回路を同
じ回路で構成するのが一般的である。 A diversity circuit is one in which two or more series of transmitting amplifier circuits or receiving amplifier circuits are provided as shown in Fig. 1, and the two series A and B must exhibit the same electrical characteristics. Generally, both circuits A and B are constructed from the same circuit.
例えば回路A,Bが受信用増幅回路である場合
について説明する。図示しないアンテナa,bの
2つがあつてアンテナaで受信した信号は回路
E,Gで増幅され、アンテナbで受信した信号は
回路D,Fで増幅されるものとする。ここで受信
用増幅回路A,Bは制御回路によりその出力の大
きい方が取り出される回路であるため、回路A,
Bはほぼ同じ電気的特性を示す必要があり、従つ
て回路A,Bは対称に配置する必要がある。しか
るにこの回路A,Bは取り扱う周波数が高く、か
つ回路利得が大きいことから、両回路A,Bをそ
のまま同一の半導体ペレツトに搭載するとAライ
ンの信号がBラインへ、Bラインの信号がAライ
ンへ飛び交う可能性がある。このため、本実施例
では回路A,B間にA,Bラインの信号による影
響の少ない回路、例えばA,Bどちらのラインを
選択するかを制御する上述の制御回路C等を設け
て、A,B間の距離を取り、回路A,B間の互い
の干渉を防ぐようにしており、これにより同一機
能を有する高利得の高周波増幅回路を2つ、回路
間のセパレーシヨンを保ちながら同一チツプ上に
搭載できるようになつた。 For example, a case will be explained in which circuits A and B are receiving amplifier circuits. It is assumed that two antennas a and b (not shown) are connected, and a signal received by antenna a is amplified by circuits E and G, and a signal received by antenna b is amplified by circuits D and F. Here, since the receiving amplifier circuits A and B are circuits from which the larger output is taken out by the control circuit, the circuit A,
B needs to exhibit approximately the same electrical characteristics, so circuits A and B need to be arranged symmetrically. However, since these circuits A and B handle a high frequency and have a large circuit gain, if both circuits A and B are mounted on the same semiconductor pellet as they are, the signal on the A line will be transferred to the B line, and the signal on the B line will be transferred to the A line. There is a possibility that it will fly to. For this reason, in this embodiment, a circuit that is less affected by the signals on the A and B lines, such as the above-mentioned control circuit C that controls which line is selected, is provided between the circuits A and B. , B to prevent mutual interference between circuits A and B. This allows two high-gain high-frequency amplification circuits with the same function to be installed on the same chip while maintaining separation between the circuits. It can now be mounted on top.
なお、上記実施例ではダイバシチ回路の増幅回
路の間に制御回路を設けたものを示したが、各増
幅回路の周辺に電源ライン、アースライン等、固
定電位の低インピーダンス配線領域を設けるよう
にしてもよく、回路A,B間を飛び交う信号が該
配線領域に落ちることにより、上記実施例と同様
に効果を奏する。 Although the above embodiment shows a diversity circuit in which a control circuit is provided between the amplifier circuits, it is also possible to provide a low impedance wiring area with a fixed potential, such as a power supply line and an earth line, around each amplifier circuit. Since the signals flying between circuits A and B fall into the wiring area, the same effect as in the above embodiment can be achieved.
また上記実施例では、高周波増幅回路A及びB
がそれぞれ増幅回路E,G及び増幅回路D,Fか
らなるものを示したが、該高周波増幅回路はミク
サ回路、周波数弁別回路等を含んでいてもよく、
上記実施例と同様の効果を奏する。 Further, in the above embodiment, high frequency amplifier circuits A and B
are shown as consisting of amplifier circuits E, G and amplifier circuits D, F, respectively, but the high frequency amplifier circuit may also include a mixer circuit, a frequency discrimination circuit, etc.
The same effects as in the above embodiment are achieved.
また、第2図に示すように回路D,Fをインピ
ーダンスの低い電源回路等、固定電位のライン
(配線領域)10,11で包囲し、回路Dの信号
が回路Cに飛ばないように、又回路Dの信号が回
路Fへ飛ばないようにして回路D,F間、回路
E,G間の干渉を防いでも良い。 In addition, as shown in Fig. 2, circuits D and F are surrounded by fixed potential lines (wiring areas) 10 and 11, such as low impedance power supply circuits, to prevent the signal from circuit D from jumping to circuit C. Interference between circuits D and F and between circuits E and G may be prevented by preventing the signal from circuit D from passing to circuit F.
また上記実施例では受信機用のダイバシチ回路
について示したが、送信機用のダイバシチ回路
等、同一の機能を有する複数の高周波回路を同一
チツプ上に搭載する場合であつてもよく、上記実
施例と同様の効果を奏する。 Further, although the above embodiment shows a diversity circuit for a receiver, it is also possible to mount a plurality of high frequency circuits having the same function on the same chip, such as a diversity circuit for a transmitter. It has the same effect as.
さらにまた、機能の異なる高周波回路を複数、
同一チツプに搭載することも勿論可能である。 Furthermore, multiple high-frequency circuits with different functions,
Of course, it is also possible to install them on the same chip.
以上のように、この発明に係る半導体集積回路
によれば、同一の機能を有する複数の高周波回路
間に干渉に強い回路を設けるかあるいは各高周波
回路の周辺に低インピーダンスの配線領域を設け
るようにしたので、従来2個以上の集積回路で構
成していたものを、1個の集積回路にすることが
でき、同時に高周波回路が同一基板上に搭載され
ていることから、各回路の電気的特性が良く一致
するものを得ることができる効果がある。
As described above, according to the semiconductor integrated circuit of the present invention, a circuit resistant to interference is provided between a plurality of high frequency circuits having the same function, or a low impedance wiring area is provided around each high frequency circuit. Therefore, what used to be composed of two or more integrated circuits can now be made into a single integrated circuit, and at the same time, since high-frequency circuits are mounted on the same substrate, the electrical characteristics of each circuit can be reduced. This has the effect of allowing a good match to be obtained.
第1図は本発明の一実施例による半導体集積回
路を示す図、第2図は回路間に低インピーダンス
の配線を走らせることにより干渉を少なくした本
発明の他の実施例を示す図である。
図において、1は半導体ペレツト、A,Bは高
周波増幅回路、D,E,F,Gは増幅回路(増幅
回路を構成する回路)、Cは制御回路(干渉に強
い回路)、H,Iは配線領域である。
FIG. 1 is a diagram showing a semiconductor integrated circuit according to one embodiment of the present invention, and FIG. 2 is a diagram showing another embodiment of the present invention in which interference is reduced by running low-impedance wiring between circuits. . In the figure, 1 is a semiconductor pellet, A and B are high-frequency amplifier circuits, D, E, F, and G are amplifier circuits (circuits that make up the amplifier circuit), C is a control circuit (a circuit that is resistant to interference), and H and I are This is the wiring area.
Claims (1)
プ上に搭載され、 干渉に強い回路が各高周波回路間に設けられる
かあるいはアース、電源ライン等の低インピーダ
ンスの配線領域が各高周波回路の周辺に設けられ
ていることを特徴とする半導体集積回路。 2 上記高周波回路は、ミクサ回路、高周波増幅
回路、周波数弁別回路等からなるダイバシチ回路
の増幅回路であり、上記干渉に強い回路は該増幅
回路のうちの出力の大きい方を選択するダイバシ
チ回路の制御回路であることを特徴とする特許請
求の範囲第1項記載の半導体集積回路。 3 低インピーダンスの配線領域が、上記増幅回
路を構成する回路の周辺に設けられていることを
特徴とする特許請求の範囲第2項記載の半導体集
積回路。[Claims] 1. A plurality of high-frequency circuits having the same function are mounted on the same chip, and a circuit resistant to interference is provided between each high-frequency circuit, or a low-impedance wiring area such as a ground or power line is connected to each high-frequency circuit. A semiconductor integrated circuit characterized by being provided around the circuit. 2. The above-mentioned high-frequency circuit is an amplification circuit of a diversity circuit consisting of a mixer circuit, a high-frequency amplification circuit, a frequency discrimination circuit, etc., and the above-mentioned interference-resistant circuit controls the diversity circuit to select the one with a larger output from among the amplification circuits. The semiconductor integrated circuit according to claim 1, which is a circuit. 3. The semiconductor integrated circuit according to claim 2, wherein a low impedance wiring region is provided around a circuit constituting the amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60195097A JPS6254950A (en) | 1985-09-04 | 1985-09-04 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60195097A JPS6254950A (en) | 1985-09-04 | 1985-09-04 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6254950A JPS6254950A (en) | 1987-03-10 |
| JPH0310237B2 true JPH0310237B2 (en) | 1991-02-13 |
Family
ID=16335473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60195097A Granted JPS6254950A (en) | 1985-09-04 | 1985-09-04 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6254950A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4018312B2 (en) | 2000-02-21 | 2007-12-05 | 株式会社ルネサステクノロジ | Wireless communication device |
| US8716834B2 (en) | 2004-12-24 | 2014-05-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including antenna |
| JP4711442B2 (en) * | 2007-08-23 | 2011-06-29 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
| JP4828644B2 (en) * | 2010-06-10 | 2011-11-30 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
-
1985
- 1985-09-04 JP JP60195097A patent/JPS6254950A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6254950A (en) | 1987-03-10 |
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