JPH0310247B2 - - Google Patents
Info
- Publication number
- JPH0310247B2 JPH0310247B2 JP58177990A JP17799083A JPH0310247B2 JP H0310247 B2 JPH0310247 B2 JP H0310247B2 JP 58177990 A JP58177990 A JP 58177990A JP 17799083 A JP17799083 A JP 17799083A JP H0310247 B2 JPH0310247 B2 JP H0310247B2
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- voltage
- transistor
- drains
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
Landscapes
- Manipulation Of Pulses (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は電圧比較器、さらに詳しく言えば、二
つのアナログ電圧レベルの大小を比較して、その
結果に対応した論理レベルを出力する電圧比較器
に関し、特に、高速度、高制度の各種Ａ／Ｄ変換
器をMOS半導体集積回路内に実現するに適した
電圧比較器を提供するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a voltage comparator, and more specifically, a voltage comparator that compares the magnitude of two analog voltage levels and outputs a logic level corresponding to the result. In particular, the present invention provides a voltage comparator suitable for realizing various high-speed, high-accuracy A/D converters in a MOS semiconductor integrated circuit.
従来のMOS半導体を用いた電圧比較器は、例
えば、IEEE Journal of Solid−state Circuist、
SC−14、No.６、DEC.1979、PP965等に説明され
ているように、位相補償回路を有しない、多段縦
続構成のいわゆる演算増幅器形が用いられてい
た。この場合の多段縦続構成は、大電圧利得の実
現、すなわち、MOS半導体の相互コンドクタン
スが比較的小さいという性質を補つて、所望の最
小比較電圧レベルを確保させるための必然的方法
であり、したがつて、回路が複雑かつ大規模とな
り、さらに、又、高速動作を行なわしめようとす
る場合には、各段のバイアス電流を大きくする必
要もあつて、集積回路化したときの占有面積及び
消費電力が大きくなる欠点があつた。
Voltage comparators using conventional MOS semiconductors are described in, for example, IEEE Journal of Solid-state Circuist,
As explained in SC-14, No. 6, DEC.1979, PP965, etc., a so-called operational amplifier type with a multi-stage cascade configuration without a phase compensation circuit was used. The multi-stage cascade configuration in this case is a natural way to achieve a large voltage gain, that is, to compensate for the relatively small mutual conductance of MOS semiconductors and to ensure the desired minimum comparison voltage level. As a result, the circuit becomes complex and large-scale, and when high-speed operation is desired, it is necessary to increase the bias current in each stage, which increases the area occupied and power consumption when integrated. The disadvantage was that it became larger.
本発明の目的は、上記した従来回路形式の欠点
をなくし、小面積、小消費電力で、かつ高速、高
制度のMOS半導体電圧比較器を提供することに
ある。
An object of the present invention is to eliminate the drawbacks of the conventional circuit type described above, and to provide a MOS semiconductor voltage comparator that has a small area, low power consumption, high speed, and high accuracy.
本発明は上記目的を達成するため、二入力のア
ナログ信号を差動増幅段で増幅し、その差動増幅
段の出力をさらに第２の増幅段で増幅する電圧比
較器において、上記差動増幅段を定電流回路と、
ソース電極が共通に上記定電流回路に接続され、
ゲート電極のそれぞれに上記二入力アナログが加
えられる第１及び第２のトランジスタと、トラン
ジスタからなる第１及び第２負荷回路と制御論理
信号によつて上記第１及び第２の負荷回路がそれ
そぞれ第１及び第２又は第２及び第１のトランジ
スタのドレイン電極に切換接続する切換回路とで
構成したものである。
In order to achieve the above object, the present invention provides a voltage comparator that amplifies a two-input analog signal in a differential amplification stage and further amplifies the output of the differential amplification stage in a second amplification stage. The stage is a constant current circuit,
The source electrodes are commonly connected to the constant current circuit,
The first and second load circuits each include first and second transistors to which the two analog inputs are applied to each of the gate electrodes, first and second load circuits each consisting of a transistor, and a control logic signal. The switching circuits are respectively connected to the drain electrodes of the first and second transistors or the drain electrodes of the second and first transistors.
上記構成によれば、以下に詳細に説明する如
く、本発明による電圧比較器では、差動増幅段が
比較的小さな電圧利得をもつプリンアンプ動作モ
ードと交差接続状態となる比較動作モードとの２
つの動作モードが行なえるような構成となり、そ
のモード切替を制御論理信号によつて行なうた
め、高速動作と交差接続における欠点を除き、高
精度の電圧比較が得られる。 According to the above configuration, as will be explained in detail below, the voltage comparator according to the present invention has two modes: a pre-amplifier operation mode in which the differential amplifier stage has a relatively small voltage gain, and a comparison operation mode in which the differential amplifier stage is in a cross-connected state.
Since the configuration is such that two operation modes can be performed, and the mode switching is performed by a control logic signal, high-accuracy voltage comparison can be obtained while eliminating drawbacks in high-speed operation and cross-connection.
以下、本発明を図面に用いて詳細に説明する。
第１図は本発明による電圧比較器の一実施例の回
路図で、第２図は上記回路の動作説明のための波
形図である。第１図において、端子１と２の間に
電圧VDD，VSS（ただし、VDD−VSS＞０）が印加さ
れ、ＰチヤネルMOSトランジスタ（以下、端に
PMOSと呼ぶ）Ｍ１及びＭ１０のゲート電極に
は端子３からVDD−VB＝Ｃ（ただしＣは正の一定
値）なるバイアス電圧VBが印加されている。し
たがつて、Ｍ１，Ｍ１０の各ゲート〜ソース間電
圧VGSは定電圧であり、これによりＭ１，Ｍ１０
はともに定電流素子動作を行なう。POMS、Ｍ
２とＭ３は互いにソース電極が共通接続されたト
ランジスタ寸法が等しい入力トランジスタであ
り、それぞれのゲート電極４及び５に２つのアナ
ログ比較電圧、VIN（−）及びVIN（＋）が印加さ
れる。ＮチヤネルMOSトランジスタ（以下、単
にNMOSと呼ぶ）Ｍ４及びＭ５は上記Ｍ２及び
Ｍ３の負荷回路であり、これらのゲート電極とド
レイン電極との間にNMOS、Ｍ６〜Ｍ９が接続
されている。すなわち、PMOS、Ｍ２とNMOS、
Ｍ４のドレイン共通接続点８と、Ｍ４のゲート電
極との間にＭ６を、同じく８とＭ５のゲート電極
との間にＭ８を、又、Ｍ３とＭ５のドレイン共通
接続点９とＭ４ゲート電極との間にＭ７を、そし
て、同じく９とＭ５のゲート電極との間にＭ９
を、それぞれ接続している。又、PMOS、Ｍ１
２とNMOS、Ｍ１３とで構成されるCMOSイン
バータの入力ゲート電極と上記Ｍ６及びＭ９のゲ
ート電極は、モード切替信号の入力端子６に接続
されている。一方、上記NMOS、Ｍ７及びＭ８
のゲート電極は上記インバータの出力ノード７に
接続されている。すなわち、MOS、Ｍ６〜Ｍ９，
Ｍ１２及びＭ１３は負荷回路であるMOS、Ｍ２
及びＭ３の接続を切換えるものである。さらに、
NMOS、Ｍ１１は前記PMOS、Ｍ１０を定電流
負荷とする反転増幅器を構成し、上述した初段の
差動増幅出力ノード９の電圧を反転増幅して端子
１０より比較結果を出力する。
Hereinafter, the present invention will be explained in detail using the drawings.
FIG. 1 is a circuit diagram of an embodiment of a voltage comparator according to the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the circuit. In Figure 1, voltages V DD and V SS (however, V DD −V SS >0) are applied between terminals 1 and 2, and a P-channel MOS transistor (hereinafter referred to as
A bias voltage V B of V DD -V B =C (where C is a constant positive value) is applied from a terminal 3 to the gate electrodes of M1 and M10 (referred to as PMOS). Therefore, each gate-source voltage V GS of M1, M10 is a constant voltage, which causes M1, M10
Both perform constant current element operation. POMS, M
2 and M3 are input transistors having the same transistor size and whose source electrodes are commonly connected to each other, and two analog comparison voltages, V IN (-) and V IN (+), are applied to their respective gate electrodes 4 and 5. . N-channel MOS transistors (hereinafter simply referred to as NMOS) M4 and M5 are load circuits for M2 and M3, and NMOS transistors M6 to M9 are connected between their gate electrodes and drain electrodes. That is, PMOS, M2 and NMOS,
M6 is connected between the drain common connection point 8 of M4 and the gate electrode of M4, M8 is also connected between 8 and the gate electrode of M5, and the drain common connection point 9 of M3 and M5 is connected to the M4 gate electrode. and M9 between the gate electrodes of 9 and M5.
are connected to each other. Also, PMOS, M1
The input gate electrodes of the CMOS inverter constituted by M2, NMOS, and M13 and the gate electrodes of M6 and M9 are connected to the input terminal 6 of the mode switching signal. On the other hand, the above NMOS, M7 and M8
The gate electrode of is connected to the output node 7 of the inverter. That is, MOS, M6 to M9,
M12 and M13 are MOS load circuits, M2
and M3 connections. moreover,
The NMOS M11 constitutes an inverting amplifier using the PMOS M10 as a constant current load, and inverts and amplifies the voltage at the differential amplification output node 9 of the first stage, and outputs the comparison result from a terminal 10.
次に、以上の構成各部の動作を述べる。 Next, the operation of each of the above components will be described.
第２図は上記実施例の動作説明のための波形図
で、横軸は時間、縦軸は各部電圧である。又、同
数の数は第１の同一番号の所の電圧を示す。い
ま、端子５の印加電圧VIN（＋）を一定値とし、
端子４の印加電圧VIN（−）を比較される電圧と
して説明する。 FIG. 2 is a waveform diagram for explaining the operation of the above embodiment, where the horizontal axis is time and the vertical axis is voltage at each part. Also, the same numbers indicate the voltage at the first same number. Now, let the voltage V IN (+) applied to terminal 5 be a constant value,
The voltage V IN (-) applied to the terminal 4 will be explained as a voltage to be compared.
時刻ｔが０≦ｔ＜t1の時間域においては、端子
６の動作モード切替信号が高論理レベルであり、
したがつて、ノード７は低論理レベルであるか
ら、NMOS、Ｍ６及びＭ９がオン、Ｍ７及びＭ
８がオフの状態である。したがつて、このときの
初段増幅回路（MOSトランジスタ、Ｍ１〜Ｍ５
で構成）は比較的電圧利得の小さい線形差動増幅
器として動作し、VIN（＋）＝VIN（−）＝VIBならば
ノード８及びノード９の電圧（V8及びいV9）は
共にV8＝V9＝VOBであり、VIN（−）＝VIN（＋）＋
△VIBならばV8＝VOB−△VOB、（ただしノード８
の電圧波形は第２図には示していない）V9＝VOB
＋△VOBとなる。ここで電圧増幅利得GA＝△
VOB／△VIBをいくらに選ぶかは設計上の問題で
あるが、通常、この状態での負荷構成並びに低消
費電力化を考えるとGAは比較的小さな値であり、
△VIBが小さい場合にはこのままでは出力１０の
電圧を反転することはできない。 In the time range where time t is 0≦t< t1 , the operation mode switching signal at terminal 6 is at a high logic level,
Therefore, since node 7 is at a low logic level, NMOS, M6 and M9 are on, M7 and M
8 is in the off state. Therefore, at this time, the first stage amplifier circuit (MOS transistors, M1 to M5
) operates as a linear differential amplifier with relatively small voltage gain, and if V IN (+) = V IN (-) = V IB , the voltages at nodes 8 and 9 (V 8 and V 9 ) are Both V 8 = V 9 = V OB , and V IN (-) = V IN (+) +
If △V IB , then V 8 =V OB −△V OB , (however, node 8
(The voltage waveform of is not shown in Figure 2) V 9 = V OB
+△V OB . Here, voltage amplification gain G A =△
How much to choose V OB /△V IB is a design issue, but normally, considering the load configuration and low power consumption in this state, G A is a relatively small value,
If ΔV IB is small, the voltage at output 10 cannot be inverted as is.
しかし、ｔ＝t1で端子６の印加電圧を低論理レ
ベルに変化させると、NMOS、Ｍ６及びＭ９は
オフ、Ｍ７及びＭ８はオンとなり、すなわち、ノ
ード８の電圧がNMOS、Ｍ５のゲート電極に、
また、ノード９の電圧がNMOS、Ｍ４のゲート
電極に印加されることになり、負荷MOS、Ｍ４
とＭ５が互いに交差接続状態になる。したがつ
て、この場合、Ｍ４はそのゲート電極に前述のプ
リアンプモード時における電位より大きい値が与
えられ、よりオン抵抗値が小さくなるように動作
するから、そのドレイン電極（すなわち、ノード
８）の電位が前述のプリアンモード時より小さく
なる。一方、NMOS、Ｍ５は、そのノード電極
に、やはり、前述プリアンモード時よりも小さい
値の電位が与えられ、その値はすぐ上で述べたよ
うにさらに小さな値に変化しているから、よりオ
ン抵抗値が大きくなるように動作して、そのドレ
イン電極（すなわち、ノード９）の電位を大きく
するように変化する。すなわち、この状態でのノ
ード８及びノード９は、もしそのノード間にわず
かな差（２△VBO）があれば、いま述べた正帰還
動作によつて、急速にその差を拡大するように変
化する。 However, when the applied voltage at terminal 6 is changed to a low logic level at t=t 1 , NMOS, M6 and M9 are turned off and M7 and M8 are turned on, i.e. the voltage at node 8 is applied to the gate electrode of NMOS, M5. ,
Also, the voltage at node 9 will be applied to the gate electrode of NMOS, M4, and the load MOS, M4.
and M5 are cross-connected to each other. Therefore, in this case, M4 has its gate electrode given a potential larger than the potential in the preamplifier mode described above, and operates so that its on-resistance value becomes smaller. The potential is lower than that in the preamplifier mode described above. On the other hand, in NMOS, M5, a smaller potential is applied to its node electrode than in the preamplifier mode, and that value has changed to an even smaller value as mentioned just above, so it is more turned on. It operates to increase the resistance value, and changes to increase the potential of its drain electrode (ie, node 9). In other words, if there is a slight difference (2△V BO ) between nodes 8 and 9 in this state, the difference will rapidly expand due to the positive feedback operation just described. Change.
したがつて、第２図に示すように、ノード９の
電圧がＭ１０及びＭ１１から成る次段の反転増幅
部でさらに増幅され、結果として、出力端子１０
に、VIN（−）とVIN（＋）との大小判定結果を電
源電圧値間にわたつて変化する論理レベルとして
出力することができる。しかも、この正帰還動作
は急速で、かつ、電圧利得が大きいから、例え、
この時間域中に入力比較電圧VIN（−）が反対方
向に変化しても、その反対方向電圧がよほど大で
ない限り、再び出力を反転することはできない。
すなわち換言すると、一度この比較モードが与え
られるとその期間中に入力が変化しても出力１０
の結果は保持される。 Therefore, as shown in FIG. 2, the voltage at node 9 is further amplified by the next-stage inverting amplifier composed of M10 and M11, and as a result, the voltage at output terminal 10 is
In addition, the result of determining the magnitude of V IN (-) and V IN (+) can be output as a logic level that changes across power supply voltage values. Moreover, this positive feedback operation is rapid and has a large voltage gain, so even if
Even if the input comparison voltage V IN (-) changes in the opposite direction during this time period, the output cannot be inverted again unless the voltage in the opposite direction is very large.
In other words, once this comparison mode is given, even if the input changes during that period, the output will be 10
results are retained.
次にｔ＝t2で再び端子６の電位が高論理レベル
となり、プリオペアンプ動作にモードが切替えら
れると、ノード９（及びノード８）の電圧は小電
圧利得の増幅動作を行ない、したがつて、出力ノ
ード１０の電位は再び高論理レベルとなる。 Next, at t= t2, the potential at terminal 6 becomes a high logic level again and the mode is switched to pre-op amplifier operation, the voltage at node 9 (and node 8) performs an amplification operation with a small voltage gain, and therefore , the potential of the output node 10 becomes a high logic level again.
次にｔ＝t3で再び比較モードとなるが、このと
き、図例では、そのモード切替直前の入力比較電
圧VIN（−）がVIN（−）−VIN（＋）＝−VBI（＜０）
の場合を示している。この場合、詳細説明は省略
するが、上述同様の動作により、出力ノード１０
には高論理レベルが得られることになる。 Next, at t= t3 , the comparison mode is entered again, but at this time, in the illustrated example, the input comparison voltage V IN (-) immediately before the mode switching becomes V IN (-) - V IN (+) = -V BI (<0)
The case is shown below. In this case, although detailed explanation is omitted, the output node 10
This results in a high logic level.
以上、本発明の動作を説明したが、本発明回路
構成はこれを動作使用中の電源電圧変動に対して
極めて安定であるという特徴を有する。すなわ
ち、初段差動増幅回路及び次段反転回路共に、上
部の電源VDDに接続されたPMOS、Ｍ１及びＭ１
０が定電流源構成であるため、もし動作使用中に
電源電圧VDDが変動しても、ノード８及び９の電
圧は変動せず、したがつて出力ノード１０の電圧
も安定である。又、VSS電源側が変動した場合、
ノード８及び９はその電源電圧変動量だけ同時に
変動するが、NMOS、Ｍ１１のゲート〜ソース
電極間電圧は一定であるから、やはり出力ノード
１０の電圧はVSSに対して安定である。 The operation of the present invention has been described above, and the circuit configuration of the present invention is characterized in that it is extremely stable against fluctuations in the power supply voltage during operation. That is, both the first-stage differential amplifier circuit and the next-stage inverting circuit have PMOS, M1, and M1 connected to the upper power supply V DD .
0 has a constant current source configuration, even if the power supply voltage V DD fluctuates during operation, the voltages at nodes 8 and 9 do not fluctuate, and therefore the voltage at output node 10 is also stable. Also, if the V SS power supply side fluctuates,
Although nodes 8 and 9 simultaneously fluctuate by the amount of power supply voltage fluctuation, since the voltage between the gate and source electrodes of NMOS M11 is constant, the voltage at output node 10 is also stable with respect to V SS .
以上説明した如く、本発明によれば、極めて簡
易な構成により、小面積、低消費電力で、かつ高
速、高安定、高利得の電圧比較器が実現でき、高
速、高精度のＡ／Ｄ変換器等を経済的に集積回路
化することができる。 As explained above, according to the present invention, a voltage comparator with a small area, low power consumption, high speed, high stability, and high gain can be realized with an extremely simple configuration, and high speed and high precision A/D conversion can be realized. It is possible to economically integrate devices, etc. into integrated circuits.
第１図は本発明による電圧比較器の一実施例の
回路図、第２図は第１図の各部動作を説明する電
圧波形である。
１，２，３……電源入力端子、４，５……アナ
ログ比較電圧入力端子、１０……出力端子、Ｍ１
〜Ｍ１３……MOSトランジスタ。
FIG. 1 is a circuit diagram of an embodiment of a voltage comparator according to the present invention, and FIG. 2 is a voltage waveform explaining the operation of each part of FIG. 1, 2, 3...Power input terminal, 4,5...Analog comparison voltage input terminal, 10...Output terminal, M1
~M13...MOS transistor.
Claims (1)
差を増幅するための第１の増幅回路と、上記第１
の増幅回路の出力電圧を増幅するための第２の増
幅回路とからなり、上記第１の増幅回路は、それ
ぞれのソースが上記定電流源に接続され、ゲート
にそれぞれ上記第１、第２の入力電圧が入力され
る第１、第２のトランジスタと、それぞれ該第
１、第２のトランジスタのドレインに直列に挿入
された負荷用の第３、第４のトランジスタとを有
し、上記第３、第４のトランジスタのゲートがそ
れぞれ第２、第１のトランジスタのドレインに接
続されて、正帰還の増幅動作を行うようにした電
圧比較器において、上記第１の増幅回路に、制御
信号に応じて一時的に、上記第３、第４のトラン
ジスタのゲートに、それぞれ上記第１、第２のト
ランジスタのドレイン電圧を与えるためのスイツ
チ回路を設けたことを特徴とする電圧比較器。 ２ 前記定電流回路は、所定電位の第１の電圧電
源と、該電位との差が一定であるバイアス電位を
有する第２の電圧電源と、ソースが上記第１の電
圧電源に接続され、ゲートが上記第２の電圧電源
に接続される少なくとも１つのトランジスタとか
ら構成され、該トランジスタのドレインから出力
される電流を前記第１、第２の増幅回路に供給す
ることを特徴とする特許請求の範囲第１項記載の
電圧比較器。 ３ 前記スイツチ回路は、前記制御信号がONレ
ベルの場合には上記第３、第４のトランジスタの
ゲートを、前記第１、第２のトランジスタのドレ
インに接続し、上記制御信号がOFFレベルの場
合には上記第３、第４のトランジスタのゲート
を、上記第２、第１のトランジスタのドレインに
接続することを特徴とする特許請求の範囲第１項
または第２項記載の電圧比較器。 ４ 前記第１、第２のトランジスタがＰ型の
MOSトランジスタで構成され、前記第３、第４
のトランジスタがＮ型のMOSトランジスタで構
成されることを特徴とする特許請求の範囲第１
項、第２項または第３項記載の電圧比較器。[Claims] 1. A constant current circuit, a first amplifier circuit for amplifying the voltage difference between the first and second input voltages, and the first
a second amplifier circuit for amplifying the output voltage of the amplifier circuit, and the first amplifier circuit has a source connected to the constant current source, and a gate connected to the first and second amplifier circuits, respectively. The third transistor has first and second transistors to which an input voltage is input, and third and fourth transistors for load, which are inserted in series with the drains of the first and second transistors, respectively. , a voltage comparator in which the gate of the fourth transistor is connected to the drains of the second and first transistors, respectively, to perform a positive feedback amplification operation, the first amplifier circuit is connected to the drains of the second and first transistors, respectively. 1. A voltage comparator characterized in that a switch circuit is provided for temporarily applying the drain voltages of the first and second transistors to the gates of the third and fourth transistors, respectively. 2. The constant current circuit includes a first voltage power source having a predetermined potential, a second voltage power source having a bias potential with a constant difference between the potential, a source connected to the first voltage power source, and a gate connected to the first voltage power source. and at least one transistor connected to the second voltage power supply, and supplies current output from the drain of the transistor to the first and second amplifier circuits. Voltage comparator according to range 1. 3. The switch circuit connects the gates of the third and fourth transistors to the drains of the first and second transistors when the control signal is at an ON level, and connects the gates of the third and fourth transistors to the drains of the first and second transistors when the control signal is at an OFF level. 3. The voltage comparator according to claim 1, wherein the gates of the third and fourth transistors are connected to the drains of the second and first transistors. 4 The first and second transistors are P-type.
The third and fourth transistors are composed of MOS transistors.
Claim 1, wherein the transistor is an N-type MOS transistor.
The voltage comparator according to item 1, 2 or 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58177990A JPS6070816A (en) | 1983-09-28 | 1983-09-28 | Voltage comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58177990A JPS6070816A (en) | 1983-09-28 | 1983-09-28 | Voltage comparator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6070816A JPS6070816A (en) | 1985-04-22 |
| JPH0310247B2 true JPH0310247B2 (en) | 1991-02-13 |
Family
ID=16040607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58177990A Granted JPS6070816A (en) | 1983-09-28 | 1983-09-28 | Voltage comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6070816A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104925843A (en) * | 2015-06-03 | 2015-09-23 | 清华大学 | Method for preparing flake-shaped α-Al2O3 pearlescent pigment base material by using composite aluminum salt |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2628228B1 (en) * | 1988-03-04 | 1990-09-14 | Thomson Composants Milit Spaci |
-
1983
- 1983-09-28 JP JP58177990A patent/JPS6070816A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104925843A (en) * | 2015-06-03 | 2015-09-23 | 清华大学 | Method for preparing flake-shaped α-Al2O3 pearlescent pigment base material by using composite aluminum salt |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6070816A (en) | 1985-04-22 |
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