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JPH0310253B2 - - Google Patents
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JPH0310253B2 - - Google Patents

Info

Publication number
JPH0310253B2
JPH0310253B2 JP13517484A JP13517484A JPH0310253B2 JP H0310253 B2 JPH0310253 B2 JP H0310253B2 JP 13517484 A JP13517484 A JP 13517484A JP 13517484 A JP13517484 A JP 13517484A JP H0310253 B2 JPH0310253 B2 JP H0310253B2
Authority
JP
Japan
Prior art keywords
accumulator
value
constant
algorithm
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13517484A
Other languages
Japanese (ja)
Other versions
JPS6115427A (en
Inventor
Mitsuo Takemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP13517484A priority Critical patent/JPS6115427A/en
Publication of JPS6115427A publication Critical patent/JPS6115427A/en
Publication of JPH0310253B2 publication Critical patent/JPH0310253B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03012Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03038Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、変復調装置の受信自動等化器におけ
る相関値演算方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a correlation value calculation method in a reception automatic equalizer of a modulation/demodulation device.

(従来の技術) 一般に、MSアルゴリズム(Mean Squre
Algorithm)による複素トランスバーサル型自動
等化器のN番目のタツプ係数は次の第1式及び第
2式で与えられる。
(Prior art) Generally, MS algorithm (Mean Square
The Nth tap coefficient of the complex transversal automatic equalizer according to the algorithm is given by the following first and second equations.

CN=CN -1−A (YN -1×EY -1+XN -1×EX -1) ……(1) DN=DN -1−A (XN -1×EY -1+YN -1×EX -1) ……(2) ここで、CN、DNはそれぞれ実軸、虚軸でのN
番目のタツプ係数、CN -1、DN -11はそれぞれ1サ
ンプル過去の実軸、虚軸でのN番目のタツプ係
数、XN -1、YN -1はそれぞれ1サンプル過去の実
軸、虚軸でのN番目の遅延タツプデータである。
また、EX -1、YY -1はそれぞれ1サンプル過去の
自動等化器の出力値とその尢度判定結果による理
想値との誤差を実軸、虚軸に射影したものであ
る。さらに、Aは設定定数で、タツプ係数のおき
かえ利得となる。すなわち、Aを大きな値に設定
すれば第1式及び第2式によるタツプ係数のおき
かえは高速で行われ、小さな値に設定すれば低速
かつ微細に行われる。通常では、自動等化器の初
期立上り時にAは大きな値に設定され、定時収束
状態では小さな値に設定される。
C N =C N -1 -A (Y N -1 ×E Y -1 +X N -1 ×E X -1 ) ...(1) D N =D N -1 -A (X N -1 ×E Y -1 +Y N -1 ×E X -1 ) ...(2) Here, C N and D N are N on the real axis and imaginary axis, respectively
The N-th tap coefficients, C N -1 and D N -1 1 are the N-th tap coefficients on the real and imaginary axes of one sample past, respectively, and X N -1 and Y N -1 are the actual actual ones of one sample past, respectively. This is the Nth delay tap data on the axis and imaginary axis.
Further, E X -1 and Y Y -1 are the errors between the output value of the automatic equalizer one sample past and the ideal value based on the result of the likelihood judgment, respectively, projected onto the real axis and the imaginary axis. Further, A is a setting constant, which is a tap coefficient replacement gain. That is, if A is set to a large value, the tap coefficients are replaced at high speed according to the first and second equations, and when A is set to a small value, the replacement is performed slowly and minutely. Normally, A is set to a large value when the automatic equalizer initially starts up, and is set to a small value when it converges on time.

第1次式及び第2式のそれぞれ右辺第2項が相
関値演算部分である。自動等化器の定常収束状態
において、EX -1、EY -1が小さな値となり、また前
述のようにAも小さな値となるので、相関値演算
部分は非常に小さな値となる。これらの演算の具
体例として第5図に示す。10は乗算器で、Mビ
ツトのYN -1、XN -1とMビツトのEY -1、EX -1、A
を順に乗算する。11は累算器で、乗算器10か
らの出力を記憶し、かつ出力しながら順次加算も
しくは減算する。この動作の手順を第6図に示
す。
The second term on the right side of each of the first and second equations is a correlation value calculation part. In the steady convergence state of the automatic equalizer, E X -1 and E Y -1 become small values, and as mentioned above, A also becomes a small value, so the correlation value calculation part becomes a very small value. A specific example of these calculations is shown in FIG. 10 is a multiplier, which has M bits Y N -1 , X N -1 and M bits E Y -1 , E X -1 , A.
Multiply in order. 11 is an accumulator that stores the output from the multiplier 10 and sequentially adds or subtracts the output while outputting it. The procedure of this operation is shown in FIG.

(発明が解決しようとする問題点) しかしながら、ここでの乗算、累算は2の補数
表示で行われるので、前述のように相関値演算結
果が非常に小さな値となると、2の捕数−LSB
特性を示す第7図からわかるように−1/2LSB
分のオフセツトが発生し、これに伴つて演算誤差
を生じ自動等化器の収束が劣化する欠点があつ
た。
(Problem to be Solved by the Invention) However, since the multiplication and accumulation here are performed in two's complement representation, if the correlation value calculation result becomes a very small value as described above, the two's catch - LSB
As can be seen from Figure 7, which shows the characteristics, -1/2LSB
This has the disadvantage that an offset of 100% is generated, which causes arithmetic errors and deteriorates the convergence of the automatic equalizer.

(問題点を解決するための手段) 本発明は、これらの問題点に鑑みなされたもの
で、相関値演算の初期に予め累算器に定数を加え
ることにより演算結果において1/2LSBのオフ
セツトを除去し、かつMSアルゴリズムにおける
タツプ係数おきかえ利得に対応する値Aを小さな
値に設定した時の収束誤差の増大を抑えることが
できる相関値演算方法を提供することを目的とす
る。
(Means for Solving the Problems) The present invention was devised in view of these problems, and by adding a constant to the accumulator in advance at the beginning of correlation value calculation, an offset of 1/2 LSB is added to the calculation result. It is an object of the present invention to provide a correlation value calculation method that can suppress the increase in convergence error when the value A corresponding to the tap coefficient replacement gain in the MS algorithm is set to a small value.

(作用) MSアルゴリズムにおけるタツプ係数おきかえ
利得に対する値をAとすると、累算器に定数K=
2-(M+1)/Aを加算入力し、演算結果として従来の
積和出力に2-(M+1)=1/2LSBが加えられたもの
が得られることになり、Aを小さな値に設定でき
ることより1/2LSBのオフセツトによりS/N
比劣化での収束誤差の発生を抑える。
(Operation) If the value for the tap coefficient replacement gain in the MS algorithm is A, then the accumulator has a constant K=
2 -(M+1) /A is added and inputted, and as a result of the calculation, 2 -(M+1) = 1/2LSB is added to the conventional product-sum output, so A is set to a small value. Since it can be set to 1/2 LSB offset, S/N can be reduced.
Suppresses the occurrence of convergence errors due to ratio deterioration.

(実施例) 第1図は、本発明の一実施例を示す構成図であ
る。第5図における従来の構成と本実施例の構成
との相違する点は、累算器11へ定数Kが加算入
力されている点である。このKは2-(M+1)/Aで表
わされる定数である。ここで、Mは乗算器10及
び累算器11の入出力点での2進数に対するビツ
ト長である。よつて、乗算器10は内部演算にお
いて最大2Mビツト長であり、切り捨てによつて
出力Mビツトを出力している。この動作の手順を
第2図に示す。同図と従来の方法の手順つまり第
6図と異なる点は、No.1及びNo.5において従来方
法では累算器クリアを行つていたが、その代わり
に定数Kを累算器に加算入力している。最終的な
積和出力は以下のようになる。
(Embodiment) FIG. 1 is a configuration diagram showing an embodiment of the present invention. The difference between the conventional configuration in FIG. 5 and the configuration of this embodiment is that a constant K is added and input to the accumulator 11. This K is a constant expressed as 2- (M+1) /A. Here, M is the bit length for the binary number at the input/output points of the multiplier 10 and the accumulator 11. Therefore, the multiplier 10 has a maximum length of 2M bits in internal calculations, and outputs an output of M bits by rounding down. The procedure of this operation is shown in FIG. The difference between this diagram and the conventional method procedure, that is, Figure 6, is that in No. 1 and No. 5, the conventional method clears the accumulator, but instead adds a constant K to the accumulator. I am typing. The final product-sum output is as follows.

A(YN -1×EY -1+XN -1×EX -1+K)=A(YN -1×EY -1
+XN -1×EX -1)+AK =A(YN -1×EY -1+XN -1×EX -1)+2-(M+1) (ここで、K=2-(M+1)/A) A(XN -1×EY -1−YN -1×EX -1+K)=A(XN -1×EY -1
−YN -1×EX -1)+AK =A(XN -1×EY -1−YN -1×EX -1)+2-(M+1) (ここで、K=2-(M+1)/A) 結果として、従来の積和出力に2-(M+1)=1/
2LSBが加えられることとなる。したがつて、本
実施例の2の補数−LSB特性を示す第3図から
わかるように、第7図でみられた−1/2LSB分
のオフセツトが解消されている。
A(Y N -1 ×E Y -1 +X N -1 ×E X -1 +K) = A(Y N -1 ×E Y -1
+X N -1 ×E X -1 ) +AK = A ( Y N -1 ×E Y -1 +X N -1 × E +1) /A) A(X N -1 ×E Y -1 −Y N -1 ×E X -1 +K) = A(X N -1 ×E Y -1
−Y N -1 ×E X -1 ) + AK = A ( X N -1 ×E Y -1 −Y N -1 × E (M+1) /A) As a result, the conventional product-sum output is 2 - (M+1) = 1/
2LSB will be added. Therefore, as can be seen from FIG. 3 showing the 2's complement LSB characteristic of this embodiment, the -1/2LSB offset seen in FIG. 7 has been eliminated.

Aが小さな値(A≪1)であると、前述のよう
に相関値演算結果が非常に小さな値となり1/
2LSBに対するS/N比が劣化する。しかし、本
実施例ではKが逆比例して大きな値となりMビツ
トに対して十分な精度が得られ、1/2LSBの補
正が正確に行われるのでS/N比は劣化しない。
If A is a small value (A≪1), as mentioned above, the correlation value calculation result will be a very small value and will be 1/
The S/N ratio for 2LSB deteriorates. However, in this embodiment, K is inversely proportional to a large value, sufficient accuracy is obtained for M bits, and 1/2LSB correction is performed accurately, so that the S/N ratio does not deteriorate.

この結果、設定定数A−自動等化器の収束誤差
特性を示す第4図からわかるように、従来方法と
比較してAが小さな値(A≪1)であつても1/
2LSBのオフセツトS/N比劣化での収束誤差の
発生を抑えることができる。
As a result, as can be seen from Fig. 4, which shows the setting constant A - convergence error characteristics of the automatic equalizer, even if A is a small value (A≪1) compared to the conventional method, 1/
It is possible to suppress the occurrence of convergence errors due to the deterioration of the 2LSB offset S/N ratio.

(発明の効果) 以上、説明したように、本発明によれば、相関
値演算の初期に予め累算器に定数を加えることに
より演算結果において1/2LSBのオフセツトを
除去し、かつMSアルゴリズムにおけるタツプ係
数おきかえ利益に対する値Aを小さな値に設定し
た時の収束誤差の増大を抑えることができる。こ
れに伴つて、Aを小さな値に設定できるので、自
動等化器が本来応答してはいけない伝送路からの
白色雑音、位相ジツタ、インパルス雑音等の影響
を軽減することができる。さらに、従来の方法に
較べて、累算器の初期の操作においてクリア動作
を行つていたがこの代りに定数Kを加算入力する
のみであるので演算処理ステツプ数を追加変更す
る必要がないという利点もある。
(Effects of the Invention) As described above, according to the present invention, by adding a constant to the accumulator in advance at the beginning of the correlation value calculation, the 1/2 LSB offset is removed from the calculation result, and the MS algorithm It is possible to suppress an increase in convergence error when the value A for tap coefficient replacement profit is set to a small value. Along with this, since A can be set to a small value, it is possible to reduce the influence of white noise, phase jitter, impulse noise, etc. from the transmission path to which the automatic equalizer should not originally respond. Furthermore, compared to the conventional method, instead of performing a clearing operation in the initial operation of the accumulator, only the constant K is added and input, so there is no need to add or change the number of processing steps. There are also advantages.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す構成図、第2
図は第1図の演算手順を示す説明図、第3図は本
実施例の2の補数−LSB特性を示す図、第4図
は本実施例の設定定数A−自動等化器の収束誤差
特性を示す図、第5図は従来の相関値演算の具体
例を示す構成図、第6図は第5図の演算手順を示
す説明図、第7図は従来例の2の補数−LSB特
性を示す図である。 10……乗算器、11……累算器。
FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
The figure is an explanatory diagram showing the calculation procedure of Figure 1, Figure 3 is a diagram showing the two's complement-LSB characteristic of this embodiment, and Figure 4 is the setting constant A of this embodiment - convergence error of automatic equalizer Figure 5 is a configuration diagram showing a specific example of conventional correlation value calculation, Figure 6 is an explanatory diagram showing the calculation procedure of Figure 5, and Figure 7 is two's complement-LSB characteristic of the conventional example. FIG. 10...multiplier, 11...accumulator.

Claims (1)

【特許請求の範囲】[Claims] 1 入出力がMビツト(Mは2以上の整数)であ
る乗算器と該乗算器の出力を累積加算する累算器
からなり2の補数表示で相関値演算を行うMSア
ルゴリズムによる自動等化器において、前記MS
アルゴリズムにおけるタツプ係数おきかえ利得に
対する値をAとして前記累算器に定数K=
2-(M+1)/Aを加算入力したことを特徴とする相関
値演算方法。
1. An automatic equalizer using the MS algorithm, which consists of a multiplier whose input/output is M bits (M is an integer of 2 or more) and an accumulator that cumulatively adds the outputs of the multiplier, and which calculates correlation values in two's complement representation. In the above MS
Assuming that the value for the tap coefficient replacement gain in the algorithm is A, a constant K=
A correlation value calculation method characterized in that 2 -(M+1) /A is added and input.
JP13517484A 1984-07-02 1984-07-02 Correlation value operating method Granted JPS6115427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13517484A JPS6115427A (en) 1984-07-02 1984-07-02 Correlation value operating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13517484A JPS6115427A (en) 1984-07-02 1984-07-02 Correlation value operating method

Publications (2)

Publication Number Publication Date
JPS6115427A JPS6115427A (en) 1986-01-23
JPH0310253B2 true JPH0310253B2 (en) 1991-02-13

Family

ID=15145560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13517484A Granted JPS6115427A (en) 1984-07-02 1984-07-02 Correlation value operating method

Country Status (1)

Country Link
JP (1) JPS6115427A (en)

Also Published As

Publication number Publication date
JPS6115427A (en) 1986-01-23

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