JPH0311040B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to EEPROM (Electrically Erasable
A method of storing contents in memory that can be updated, retains the contents even when the power is turned off, and limits the number of times the contents can be updated, such as Programmable Read Only Memory. It is related to.

[Conventional technology]

In general, in control devices and data processing devices, semi-fixed data or variable data that is generated sequentially during operation is referred to later in RAM.
(Random Access Memory.) In order to ensure that the contents do not disappear even if the power is cut off, the RAM is maintained in an operating state by a backup power source such as a battery, but if the battery is replaced or Since it requires a switching circuit to a backup power source, EEPROM has recently been used.

[Problem that the invention seeks to solve]

However, the current EEPROM has a limit on the number of times its contents can be updated, so if you store data at a random address like general RAM, and update the contents at the same address while storing the data,
A problem arises in that it is impossible to update the content for a short period of time.

[Means for solving problems]

In order to solve the above-mentioned problem, the present invention is constructed by the following means.

That is, in a method of storing contents in a memory such as an EEPROM, when storing data for the first time, the data is stored at a specific address in the storage area of the memory, and an end mark is stored at the next and subsequent addresses, respectively. When storing the next data, the contents are updated and stored at the address on the preceding side where the end mark was stored, and the end mark is stored at the address next to the address on the subsequent side where the end mark was stored. Similar storage operations are repeated as necessary.

[Effect]

Therefore, data is first stored at a specific address in the storage area, then the content is updated to the address on the preceding side where the end mark is stored, and the next data is stored. The above operations are repeated accordingly, and the number of updates of the contents at each address becomes approximately equal, and even if the power is cut off during storage, the validity of the contents can be determined without any problem.

〔Example〕

Hereinafter, details of the present invention will be explained with reference to figures showing examples.

FIG. 2 is a block diagram of a device using EEPROM, which includes a processor such as a microprocessor (hereinafter referred to as CPU) 1, fixed memory (hereinafter referred to as ROM) 2, variable memory (hereinafter referred to as RAM) 3,
EEPROMs 4 to 6 and interfaces (hereinafter referred to as I/Fs) 7 and 8 are arranged around the periphery, and these are connected by a bus bar. machine or keyboard,
A terminal device such as a cathode ray tube display device is connected, and a printer (hereinafter referred to as
PRT) 9 is connected.

Here, CPU 1 executes instructions in ROM 2, performs control operations according to input data via I/F 7, accesses necessary data to RAM 3, and also accesses EEPROMs 4 to 6. Then, edit the printout data using the patterns of characters, symbols, etc. stored in EEPROM 4 to 6, and then print it via I/F 8.
The data is sent to the PRT9, thereby causing predetermined data to be printed.

Please note that the patterns of characters, symbols, etc.
You will be given what you need via
It is used after being stored in EEPROM 4 to 6.

FIG. 1 is a diagram showing the storage status of data in EEPROMs 4 to 6. In this example, these are divided into a code area CE and a data area DE, and the data area DE shows patterns of characters, symbols, etc. Data DT ₀ to DT _o are sequentially stored, and from the first address #0 to the last address #n+2 of the code area CE used as a storage area, data codes DC ₀ to DT o corresponding to the data DT ₀ to DT _o are stored sequentially.
DC _o and end mark EM are stored, and a valid mark AM indicating that data codes DC ₀ to DC _o are valid is stored at address #r other than code area CE and data area DE. It has become a thing.

That is, when storing the first data, as shown in (A), data code DC ₀ is stored in the first address #0 as a specific address, and an end mark is stored in the next address #1 and the address #2 following this. E.M.
On the other hand, the data code DC ₀ and the corresponding data DT ₀ are stored in a concatenated manner over multiple addresses with the starting address of the data area DE as a reference.

Note that the * mark indicates that the data has been newly stored.

Next, as shown in (B), when storing the next data, update the contents to address #1 on the preceding side where the end mark EM of the code area CE is stored, and store the data code DC ₁ . , the end mark is stored in the next address #3 of the next address #2 where the end mark EM is stored, and the end mark is stored in the data area.
Data DT ₁ is stored in each address following data DT ₀ in DE, and the same operation is repeated until the final address #n+2.

Then, finally, as shown in (C), the final address #n+2
and end mark to address #n+1 immediately before this
EM is stored, and the data code DC _o is stored in the address #n immediately before the leading address #n+1 where the end mark EM is stored, and the data area DE
Then, data DT _o is stored on the final address side.

Therefore, in code area CE, addresses #0 and #n+2 are used once each, and addresses #1 to #n
+1, each address is stored twice, and in the data area DE, each address is stored once, so that the number of times of storage can be averaged.

Also, when reading the contents, first check the valid mark AM at address #r, and if it is normal, read from address #0 to the preceding address where end marks EM are normally stored consecutively. The data code up to the immediately previous address is valid, and the data in the data area DE may be read and used according to the data code.

However, if the end marks EM are not stored consecutively, this is due to a power outage, etc. when storing the subsequent end mark EM, and the end mark EM is not stored consecutively. The data code up to the address after subtracting the number is valid.

In contrast to the above, when clearing the contents and storing them again, either invert each bit of the valid code AM at the same time as clearing, or clear each bit to make sure that all the contents have been cleared. Can be displayed.

Figure 3 is a flowchart of the storage operation by CPU 1. First, the question "Is there AM at address #r?"
Check 101 and if this is NO then “DC ₀
→Data code to address #0 by #0”111
DC ₀ is stored and the data is set by “DT ₀ →DE”112.
After storing DT ₀ in data area DE, “EM→#
1 and #2” 113, store the end mark EM in addresses #1 and #2, and store the valid mark “AM”.
→ Store at address r by #r”114.

Also, when step 101 is YES, “DC _i
→The i-th data code DC _i is stored at the leading address where the end mark EM is stored, and the i-th data
After storing DT _i by “DT _i →DE”122,
End mark “EM→EM stored rear address +1”
At step 123, the end mark EM is stored at the next address after the address where the end mark EM is stored, and steps 101 and subsequent steps are repeated as necessary via the main routine.

FIG. 4 is a flowchart showing a similar read operation.
If YES, end mark “EM continuous?” 2
02 is checked, and in response to YES, it is determined that the contents from the head address "#0 to the address immediately before the leading EM are valid" 211, and a data area "corresponding data reading of DE" 212 is performed.

In addition, if step 202 is NO, the contents from the first address "#0 to EM address -2 are valid" 2
21 is made, and the process moves to step 212.

On the other hand, when step 201 is NO,
“Content invalid” 231 is determined.

FIG. 5 is a storage situation diagram showing another embodiment, which is the same as FIG. 1, but the code area CE is composed of the first address #0 to the last address #n, and the data code DC ₁ and later, end code EM, and
The start mark SM is stored, and addresses #0 to #n are used cyclically from #n to #0.

Note that the data area DE is also used cyclically.

That is, when storing the first data, as shown in (A), the start mark SM is stored in the first address #0 and the next address #1, and the data code DC ₁ is stored in the third address #2. , and store the end mark EM in the next address #3 and the address #4 following this, respectively, and store the data code DC ₁ and the corresponding data DT ₁ in the data area.
Continuously stores data at multiple addresses based on the first address of DE.

Note that, as in FIG. 1, the * mark indicates that the data has been newly stored.

Next, as shown in (B), when storing the next data, update the contents to address #3 on the preceding side where the end mark EM of the code area CE is stored, and store the data code DC ₂ . The end mark EM is stored in the next address #5 after the address where the end mark EM is stored, and the data DT ₂ is stored in the data area DE at each address following data DT ₁ .
From then on, similar storage operations are performed at the final address #n
Repeat until.

Then, as shown in (C), data code DC _o-3 is finally stored at address #n-2, which is two addresses before the final address #n, and an end mark is placed at the final address #n.
EM is stored, and data DT _o-3 is stored in the data area DE.

Also, when storing subsequent data, the data code is sent to the address #n-1 immediately before the final address #n.
At the same time as storing DC _o-2 , update the contents of the end mark EM to the first address #0 and the start mark SM to the next address #2 of the next address #1 where the start mark SM is stored. On the other hand, the data code DC _o-2 and the corresponding data DT _o-2 are stored in the data area DE, resulting in the state of (D).

Furthermore, when storing data, as shown in (E), data code DC o-1 is stored in the leading address #n where the end mark EM is stored, and data code DC _o-1 is stored in the address #0 where the end mark EM is stored. The end mark EM is stored at the next address #1, and the start mark SM is stored at the next address #3 after the address #2 where the start mark SM is stored. Repeating the operation as necessary will sequentially pass the data code DC _o through the state of (F) and the data
The data after DT _o are stored sequentially and cyclically, and the contents are thereby updated.

Note that 2 bytes are used for data codes DC ₀ to DC _o and DC ₁ onwards, and valid marks AM,
As start mark SM and end mark EM, codes are used that are different from data codes DC ₀ to DC _o and DC ₁ onwards, and data DT ₀ to DT _o and DT ₁ onwards are each made up of 72 bytes. Therefore, the number of addresses and storage capacity of each area CE, DE and space are determined according to the number of bytes.

Therefore, in the case of Figure 5, the code area CE
, if (A) to (F) are one cycle, address #
0, #2, #3 three times each, address #1, #4, #n
is subjected to the storage operation twice, and each of the other addresses is subjected to the storage operation once.If the same cycle is repeated as necessary, the number of times the contents of each address are updated will be approximately equal.

Also, when reading the contents, check each start code SM, and if these are normal, read the address next to these or two end marks.
The data code up to the address immediately before the address where EM is normally stored is valid, and this is stored as address #0.
~#n, and further from #n to #0, the data in the data area DE may be read out and used according to the data code.

In other words, if the start mark SM and end mark EM are stored normally, the data code and data are also normal. If an abnormality occurs during storage due to a power cut, etc., the start code SM or end mark EM will not be stored normally. It will not be stored.

Therefore, by using the same procedure, the contents can be checked when the power is turned off and turned on again, and it is possible to determine with high reliability whether the contents are valid or not.

FIG. 6 is a flowchart of the storage operation by the CPU 1. It judges "first data?" 301, and if this is YES, "SM→#0/#1"
The start mark SM is stored in addresses #0 and #1 by 311, and the data code DC ₁ is stored in address #2 by "DC ₁ → #2" 312.
Data DT ₁ is stored in the data area DE by “DT ₁ → DE” 313, and then “EM → # 3・# 4” 3
14, the end mark EM is stored at addresses #3 and #4.

If step 301 is NO, address “#n” is
After storing EM? ”Check 302, NO of this
Accordingly, the i-th data code “DC _i → EM stored first address” 321 is used to store the end mark EM at the first address stored, and the corresponding data “DT _i →DE” 322 is used to store the end mark EM. and stores it in the data area DE, and then moves the end mark EM to the address next to the last address where it is stored, including the circular order, by "EM→EM stored last address + 1" 323. Store.

In addition, in response to YES in step 302, the start mark "SM→Stored rear address of SM+1"
331, and as in steps 321 and 322, "DC _i → EM stored leading address 332," DT _i →
Perform “DE”333 and end mark “EM→SM”
334, and then repeats steps 301 and subsequent steps through the main routine.

FIG. 7 is a flowchart showing a similar read operation. First, a start mark "SM present?" 401 and an end mark "EM present?" 402 are checked in the code area CE.
If YES, start mark “SM consecutive?” 4
11 and the end mark "EM continuous?" 412, and in response to these YES, it is determined that "contents from the next address of the succeeding SM to the address immediately before the preceding EM are valid" 421, and the data area "DE" is checked. The corresponding data readout ``422'' is performed.

In addition, when step 412 is NO, “Successor
It is determined that the contents from the next address of SM to address -2 of EM are valid" 431, and the process moves to step 422.

On the other hand, in response to NO in step 411, the end mark "EM continuous?" 441 is checked and this is confirmed.
If YES, start mark “SM address +2
Contents valid from to the address immediately before the succeeding EM” 45
1, and the process moves to step 422.

If step 441 is NO, the start mark is determined to be "Contents valid from address +2 of SM to address -2 of EM" 461, and step 422 is determined.
Move to.

Regarding the above, if either step 401 or 402 is NO, it is determined that "content is invalid" 471,
Step 401 and subsequent steps are immediately repeated via the main routine.

However, in Figures 1 and 5, since the number of bytes after data DT ₀ to DT _o and DT ₁ is large, a data area DE is provided separately from the code area CE, but data DT ₀ to DT If the number of bytes after _o and DT ₁ is small, use only code area CE,
Data DT ₀ - DT _o and DT ₁ onwards may be stored as data codes DC ₀ - DC _o and DC ₁ onwards, and when the configuration shown in Fig. 1 or 5 is used, data codes DC ₀ - _{DC o} and data to DC ₁ or later
Add the storage address code from DT ₀ to DT _o and DT ₁ onwards, or CPU1 adds the data code DC ₀ to
The storage address of data DT ₀ to DT o and _{DT 1} and later is determined according to DC _o and DC ₁ and later, and the data area
The storage addresses may be determined sequentially in the DE, and the configuration shown in FIG. 2 can be arbitrarily selected depending on the conditions, and various modifications are possible.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, in a memory such as an EEPROM where the number of times content can be updated is limited, the content is updated almost equally for each address, and the number of times content is updated to a specific address is increased. In addition, the end mark EM will not disappear even if the power is cut off while data is being stored in the EEPROM, and the validity determination can be made without any problems. A remarkable effect can be obtained as a method of storing contents in memory.

[Brief explanation of the drawing]

The figures show an embodiment of the invention, FIG.
Diagram showing how data is stored in EEPROM,
Figure 2 is a block diagram of a device using EEPROM.
Figure 3 is a flowchart of the storage status by the CPU.
FIG. 4 is a flowchart showing a similar readout situation, FIG. 5 is a diagram similar to FIG. 1 showing another embodiment, and FIGS. 6 and 7 are flowcharts corresponding to FIG.
FIG. 4 is a diagram similar to FIG. 1...CPU (processor), 4 to 6...
EEPROM (memory), CE...Code area (storage area), DE...Data area, DC ₀ to DC _o ...
Data code, AM...Valid mark, SM...Start mark, EM...End mark, DT ₀ ~
DT _o ...Data.

Claims (1)

[Scope of Claims] 1. A method for storing contents in a memory whose contents can be updated, retains the contents even when the power is turned off, and whose number of contents can be updated is limited. When storing data for the first time, the data is stored at a specific address in the storage area of the memory, and an end mark is stored at the next address and the address following this, and when the next data is stored, the end mark is stored at the next address. The content is updated and the data is stored at the address on the preceding side where the end mark was stored, and the end mark is stored at the address next to the address on the subsequent side where the end mark was stored. A method for storing contents in memory, which is characterized by repeating according to the timing.