JPH0311129B2 - - Google Patents

Description

[Detailed description of the invention] This invention is a normally-on type shot key gate.
This invention relates to a logic circuit including an inverter using a FET as a driver.

Logic circuits consisting of Schottky gate FETs using GaAs are suitable for ultra-high-speed digital circuits because the carrier mobility of GaAs is greater than that of Si. Among these, logic circuits using normally-on Schottky gate FETs are capable of high-speed operation.

Figure 1a shows a normally-on type shot key gate.
It is well known as a logic circuit using FET.
This circuit is called BFL (Buffered Follower Logic), and b is its logic diagram. _Q1 ～ _Q5
are all normally on type. Q ₁ , Q ₄ , Q ₅ , Q ₈
is the current source load, Q ₂ and Q ₆ are the inverter G ₁ ,
The G ₂ driver, Q ₃ and Q ₇ act as source followers. D ₁ to _{D 6} are Schottky diodes that perform level shifting operations. Logic amplitude is +0.5V ~
-2V is about 2.5V.

One drawback of this circuit is that V _DD (positive) and V _SS (negative)
This means that two power supplies are required.

The logic circuit shown in Figure 2, which uses a normally-off Schottky gate FET, is considered as a circuit that operates with a single power supply. This circuit is DCFL
(Direct Coupled Function Logic). Q ₁₁ and Q ₁₃ are normally-on FETs as current loads, and Q ₁₂ and Q ₁₄ are normally-off FETs as drivers. The circuit has an E/D configuration. In addition to the advantage that this logic circuit operates with a single V+ power supply, it has a simple configuration and requires a small number of elements. but
Since forward rotation is applied between the gate and source of Q ₁₂ and Q ₁₄ , the gate voltage is clamped to the Schottky forward voltage (approximately 0.8V). Therefore, when considering the rise in low levels, the logic amplitude can only be about 0.6V, and the noise margin voltage becomes extremely small. Furthermore, when considered at the LSI level,
In order to create hundreds to thousands of transistors on the same chip, it is necessary to take into account variations in pinch-off voltage and changes in on-voltage due to differences in the number of fan-outs, and the noise margin voltage becomes smaller and smaller. By the way, there is also a report that, assuming the noise margin voltage is 0, the allowable variation in pinch-off voltage for a 100-element IC is about 20 mV (1982 Institute of Electronics and Communication Engineers National Conference ``FET Threshold Voltage for Normally-Off GaAs ICs''). ``Hirayama et al.''

In view of the above-mentioned points, the present invention is a logic circuit including an inverter that drives a normally-on type shot key gate FET, which is capable of sufficiently increasing the logic amplitude and can be operated with a single power supply. It provides:

The present invention is a normally-on type shot key gate.
In a logic circuit that includes a circuit in which multiple inverters are connected in series, each of which has an FET as a driver and its drain connected to the high potential end of a power supply via a load, (1) the sources of the driver FETs of multiple inverters are commonly connected; (2) at least one Schottky diode or resistor is connected between this source and the low potential end of the power source to float the source potential above the low potential end; and (2) the plurality of inverters are connected at a level It is characterized by being connected in cascade via a shift circuit, thereby making it possible to achieve the above object.

FIG. 3 shows a principle diagram of the logic circuit of the present invention.
Q ₂₁ to Q ₂₃ are normally-on type shot key gate FETs whose pinch-off voltage is approximately equal to −V _SS .
A driver consisting of two drivers whose sources are commonly connected. V _SS is a constant voltage to raise the source potential of these FETs from ground potential. Also
V _L is a constant voltage for level shifting circuit from drain potential to gate potential.

Q ₂₄ -Q ₂₆ are current source loads of Q ₂₁ -Q ₂₃ , respectively.

Next, consider the relationship between voltage and current shown in Figure 3. When the input gate voltage of this circuit is initially close to ground potential, the gate-source voltage of _Q21 is approximately equal to -V _SS , and its pinch-off voltage is -V _SS , so
Q ₂₁ is pinched off and the current flowing is almost 0.
It is. At this time, the drain voltage of Q ₂₁ is approximately 0.8V+
It becomes V _SS +V _{L. This} is because the gate-source junction of the next stage FET- _Q22 is a Schottky junction and is biased in the forward direction, so the gate of _Q22 has a Schottky _voltage (approx.
This is because the voltage is clamped to a higher voltage (0.8V + V _SS ) by 0.8V). Therefore, the drain-source voltage V _DS of Q ₂₁ is approximately 0.8 V + V _L. This state is point A in the V _{DS -ID} characteristic diagram shown in FIG.

Next, consider the state of transistor _Q22 . Q ₂₂ is in the on state because its gate is 0.8V higher than its source, and the current in the load Q ₂₅ becomes the drain current of Q ₂₂ and flows through the channel. Therefore, its drain potential drops to a potential V _SS that is approximately equal to the source potential, and V _DS is approximately zero. If this state is shown in FIG. 4, which shows the relationship between V _DS and _ID , it becomes point B, and the current flowing is the current I _L of the load Q ₂₅ . Here, the current of load Q ₂₄ flows into the source through the gate of Q ₂₂ .

Next, by adding a positive potential to the input end of this circuit, the input and output characteristics shown in FIG. 5 are obtained.
Here, the threshold voltage is 0.8+V _L /2, and the logic amplitude is approximately 0.8 V+V _L volts. Here, the pinch-off voltage is |V _P |≦
The relationship |V _L | holds true.

From the above, it is clear that the logic circuit of the present invention is a logic circuit suitable for high-speed operation that uses a normally-on type FET as a driver, operates with a single power supply, and has a logic amplitude of 0.8V or more. .

Next, specific examples of the present invention will be described. FIG. 6 shows an embodiment of the invention. Components that have the same function as those in Figure 3 are given the same symbols. Current source loads Q ₂₄ to _{Q 26} are active loads that connect the gate and source of normally-on Schottky gate FETs.

Shot key diodes D ₂₁ to _{D 23} are used to obtain a constant voltage voltage V _L for level shifting, and the shift voltage is the forward voltage of the shot key (approximately 0.8 V).
It is. Furthermore, in order to keep this level shift voltage constant, a normally-on type shot key gate is used as a current source with a smaller current value than _Q24 to _Q26 .
FETQ ₂₇ to Q ₂₉ are connected. Further, the Schottky diode _D31 is also used as a constant voltage V _SS that makes the commonly connected source potential of the driver FETs more positive than the ground potential, and its forward voltage (approximately 0.8 V) is used. Here, the current flowing through this diode D ₃₁ is always the current source load Q ₂₄ ~ _{Q 26}
Since it is the sum of the currents, it is constant and operates as a constant voltage.

The pinch-off voltage of the FET in this circuit is approximately -0.8V, and the logic amplitude is approximately 1.6V.

7 to 12 show essential parts of an embodiment that is a modification of FIG. 6. In FIG. 7, a resistor _R1 is used as a constant voltage source that determines the source potential.
The current flowing through R ₁ is constant because it is the sum of all current source loads ΣIi, so the source potential is R ₁・ΣIi
becomes. In addition, a resistor is used as a constant voltage source for level shift.
_R2 is used. In order to turn off the FET, the current value due to Q ₂₇ is I ₂ and the relationship is |R ₂ · ₂ | |V _P |.

In Figure 8, two Schottky diodes D ₃₁₁ and D ₃₁₂ are used to raise the source potential, and two Schottky diodes are also used for level shifting.
Using D ₂₁₁ and D ₂₁₂ , the logic amplitude is set to 0.8 + 2V _SS (
2.4V). The pinch-off voltage V _P has the relationship |V _P | |2V _SS |.

FIG. 9 shows a configuration for achieving better constant current operation by floating the drain potential of the current source FET-Q ₂₇ by V _SS from the ground potential.
The gate potential operates from V _SS to 0.8+2V _SS , and the logic amplitude is 0.8+V _SS (1.6V).

In FIG. 10, a Schottky diode _D32 is inserted antiparallel to _D31 in the circuit of FIG. 6. Since this diode _D32 is reverse-biased, it functions as a capacitor, and performs a decoupling capacitor operation to absorb the ripples slightly generated in the source potential of _Q21 during the switching operation.

FIG. 11 is an example in which level shifting is performed using FET- _QL . The pinch-off voltage of FET-Q _L is almost 0V, and the current value at that time is
It is set to be almost equal to that of FET-Q ₂₇ . By using level shift of the source follower, the drive ability to the next stage is further increased.

FIG. 12 shows an example in which a combination of a source follower and a Schottky diode _D21 similar to that in FIG. 11 is used for level shifting.

Furthermore, although not shown, a level shift using the breakdown voltage of a Schottky diode is also conceivable.

Furthermore, a combination of the above circuits is naturally possible.

As described above, according to the present invention, using the normal normally-on Schottky gate FET process,
Due to the normally-on FET configuration, the logic amplitude is
It is possible to realize high-speed digital circuits that are large at 0.8V or more and operate with a single power supply.

[Brief explanation of the drawing]

Figures 1a and b are a logic circuit (BFL) with a conventional normally-on shot key gate FET configuration and its logic diagram, and Figure 2 is a diagram of a logic circuit (DCFL) with a conventional normally-off shot key gate FET configuration. , Fig. 3 is a diagram showing the principle configuration of the present invention, and Fig. 4 is an I _D - for draining the operation.
The V _DS characteristic diagram, Figure 5, is also the input/output characteristic diagram, Figure 6.
The figure is a logic circuit diagram of one embodiment of the present invention, and FIGS. 7 to 12 are diagrams showing main parts of other embodiments of the present invention. Q ₂₁ , Q ₂₂ , Q ₂₃ ... Driver FET, Q ₂₄ , Q ₂₅ ,
Q ₂₆ ... Current source load FET, D ₃₁ , D ₂₁ , D ₂₂ , D ₂₃ ...
...Schottky diode, Q ₂₇ ...Current source
FET, R ₁ , R ₂ ... Resistor, Q _L ... Source follower
FET.

Claims (1)

[Scope of Claims] 1. A logic circuit including a circuit in which a plurality of inverters each having a normally-on type Schottky gate FET as a driver and a drain thereof connected to a high potential end of a power supply via a load are connected in series, the sources of the driver FETs of the inverters are commonly connected, and at least one Schottky diode or resistor is connected between the sources and the low potential end of the power source to float the source potential above the low potential end;
The logic circuit is characterized in that the plurality of inverters are connected in series via a level shift circuit. 2. The logic circuit according to claim 1, wherein the level shift circuit comprises at least one diode or resistor and has a current source between its terminal end and the low potential end.