JPH0311543B2 - - Google Patents
Info
- Publication number
- JPH0311543B2 JPH0311543B2 JP19216581A JP19216581A JPH0311543B2 JP H0311543 B2 JPH0311543 B2 JP H0311543B2 JP 19216581 A JP19216581 A JP 19216581A JP 19216581 A JP19216581 A JP 19216581A JP H0311543 B2 JPH0311543 B2 JP H0311543B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon oxide
- insulating layer
- oxide film
- etching
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 15
- 238000001020 plasma etching Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 4
- 239000005368 silicate glass Substances 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 34
- 239000004020 conductor Substances 0.000 description 14
- 239000007789 gas Substances 0.000 description 14
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- 229920000642 polymer Polymers 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000001282 organosilanes Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
発明の技術分野
本発明は、段差を有する下地表面に形成された
絶縁層を平坦化する方法に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for planarizing an insulating layer formed on a base surface having steps.
発明の技術的背景とその問題点
半導体集積回路の如き小形電子装置を製作する
場合、絶縁層と導体層とを順次形成すると共に写
真食刻法等により上記絶縁層および導体層を所定
のパターンに加工するため、いくつかの膜層の厚
さになぞらえた高さ変化が生ずる。この高さ変化
は装置表面に非常に極端な段違いを生じさせ、と
きにはオーバーハングした縁となることもある。
そして、このような段違いがある表面上に導体
層、例えばアルミニウム膜を真空蒸着等の手段で
付着させた場合、段差の側面でアルミニウム膜が
薄くなつたり、段差が急峻で微細なホール状にな
つているところでは全く付着しない状態となり、
導体層の断線が生じ、製品の歩留りを悪くする
他、製品使用時の故障率を高めることにもなる。Technical background of the invention and its problems When manufacturing a small electronic device such as a semiconductor integrated circuit, an insulating layer and a conductive layer are sequentially formed, and the insulating layer and conductive layer are formed into a predetermined pattern by photolithography or the like. Due to processing, height changes occur that resemble the thickness of several membrane layers. This height change creates very extreme unevenness in the surface of the device, sometimes resulting in overhanging edges.
If a conductor layer, such as an aluminum film, is deposited on a surface with such a step by means such as vacuum evaporation, the aluminum film may become thinner on the sides of the step, or the step may become steep and form a fine hole. It will not adhere at all in places where it is
Disconnection of the conductor layer occurs, which not only reduces the yield of the product but also increases the failure rate during product use.
従来、上述した導体層の断線を防止するために
は、導体層を形成する前の絶縁膜表面をなだらか
にする方法として、例えばSiO2に燐を含ませた
ガラス層を1000〔℃〕以上の加熱処理によつて塑
性流動させる所謂ガラスフロー法、或いはオルガ
ノシラン等の有機系物質を塗布し焼結する所謂塗
布法が用いられている。 Conventionally, in order to prevent the above-mentioned disconnection of the conductor layer, as a method of smoothing the surface of the insulating film before forming the conductor layer, for example, a glass layer containing phosphorus in SiO 2 was heated to a temperature of 1000 [℃] or more. The so-called glass flow method, in which plastic flow is caused by heat treatment, or the so-called coating method, in which an organic material such as organosilane is applied and sintered, is used.
しかし、前記ガラスフロー法では、高温処理が
必要なために、導体層として低融点金属、例えば
アルミニウム等が形成された後、さらに導体層を
設けるための相互間の絶縁膜には適用できず、ま
た半導体基板内に予め導入されている不純物、例
えば燐、砒素、硼素がガラスフローの高温処理過
程で再分布するため半導体装置の高密度化高速化
に限界がある等の欠点がある。また、前記塗布法
では緻密な絶縁膜を得るのが困難なため、吸湿性
が大きく、さらにピンホールが多い等のためアル
ミニウム等の導体層が腐蝕したり配線相互間にリ
ーク電流が生じたりする欠点があつた。 However, since the glass flow method requires high-temperature treatment, it cannot be applied to an insulating film between layers to further provide a conductor layer after a low melting point metal such as aluminum is formed as a conductor layer. Further, impurities introduced in advance into the semiconductor substrate, such as phosphorus, arsenic, and boron, are redistributed during the high-temperature treatment process of glass flow, so there is a drawback that there is a limit to the high density and high speed of semiconductor devices. In addition, since it is difficult to obtain a dense insulating film using the above coating method, the coating method has high hygroscopicity, and furthermore, due to the large number of pinholes, conductor layers such as aluminum may corrode and leakage current may occur between wiring lines. There were flaws.
発明の目的
本発明の目的は、段差を有する下地表面に形成
された絶縁層を確実に平坦化することができ、半
導体装置の信頼性向上および導体層の断線防止等
に寄与し得る絶縁層の平坦化方法を提供すること
にある。OBJECTS OF THE INVENTION An object of the present invention is to provide an insulating layer that can reliably flatten an insulating layer formed on a base surface having a step, and that can contribute to improving the reliability of a semiconductor device and preventing disconnection of a conductor layer. An object of the present invention is to provide a flattening method.
発明の概要
本発明者等は、絶縁層の段差をなだらかにする
ことを目的として鋭意研究を重ねた結果、Ｃ、
Ｆ、Ｈを含む混合ガスを反応性ガスとする反応性
イオンエツチング法を用いて絶縁層を全面エツチ
ングすればよいことを見出した。すなわち、本発
明者等の実験によれば、C3F8とのH2と混合ガス
を用いた反応性イオンエツチング法により急峻な
段差を有した酸化シリコン膜を全面エツチングし
たところ、酸化シリコン膜の急峻な段差がなだら
かになることが判つた。これは、エツチング時に
生じるＣ−Ｆポリマが絶縁膜の平坦部に付着され
易く、段差周縁部には付着され難いためである。
つまり、絶縁膜の平坦部に付着されたポリマによ
り絶縁膜の平坦部のエツチングが阻外され、絶縁
膜の周縁部が他より速くエツチングされるためで
ある。また、本発明者等の実験によれば、反応性
ガスとして添加するＨの添加量によつてポリマの
生成量が可変し、これにより絶縁膜の周縁部の傾
斜を可変し得ることが判明した。本発明はこのよ
うな点に着目し、段差を有する下地表面上に酸化
シリコン膜或いは不純物を含むシリケートガラス
膜からなる絶縁層を形成したのち、Ｃ、Ｆ、Ｈを
含む混合ガスを反応性ガスとする反応性イオンエ
ツチング法を用い上記絶縁層を全面エツチングす
るようにした方法である。Summary of the Invention As a result of extensive research aimed at smoothing the level difference in the insulating layer, the inventors discovered that C.
It has been found that the entire surface of the insulating layer can be etched using a reactive ion etching method using a mixed gas containing F and H as a reactive gas. That is, according to experiments conducted by the present inventors, when a silicon oxide film having steep steps was etched over the entire surface by a reactive ion etching method using a mixed gas of H 2 and C 3 F 8 , the silicon oxide film It was found that the steep differences in height became gentler. This is because the C-F polymer produced during etching tends to adhere to the flat portions of the insulating film and is difficult to adhere to the peripheral portions of the steps.
In other words, the etching of the flat part of the insulating film is blocked by the polymer attached to the flat part of the insulating film, and the peripheral part of the insulating film is etched faster than the other parts. In addition, according to experiments conducted by the present inventors, it was found that the amount of polymer produced can be varied depending on the amount of H added as a reactive gas, and thereby the slope of the peripheral edge of the insulating film can be varied. . The present invention focuses on such points, and after forming an insulating layer made of a silicon oxide film or a silicate glass film containing impurities on a base surface having steps, a mixed gas containing C, F, and H is converted into a reactive gas. In this method, the entire surface of the insulating layer is etched using a reactive ion etching method.
発明の効果
本発明によれば、絶縁層の段差をなだらかにす
ることができるので、導体層の断線防止および半
導体装置の信頼性向上をはかり得る。また、低温
工程のみで高温処理が必要なガラスフロー法と同
程度の効果が得られ、さらに有機物質膜を用いる
必要がないので、導体層の腐蝕や配線間クリーク
電流が生じることも防止できる。Effects of the Invention According to the present invention, it is possible to make the level difference in the insulating layer gentle, thereby preventing disconnection of the conductor layer and improving the reliability of the semiconductor device. In addition, the same effect as the glass flow method, which requires high-temperature processing, can be obtained using only a low-temperature process, and since there is no need to use an organic material film, corrosion of the conductor layer and leakage current between wiring can be prevented.
発明の実施例
第１図乃至第３図は本発明の一実施例を示す工
程断面図である。まず、第１図に示す如く素子が
形成された基板１の上に熱酸化法により酸化シリ
コン膜２を披着した後、酸化シリコン膜２に必要
な接続孔を開けて、この孔も含め酸化シリコン膜
２上に第１導体層として、例えばアルミニウム膜
３を形成する。アルミニウム膜３はスパツタ法や
電子ビーム蒸着法により披着し、そのパターニン
グはCCl4とCl2との混合ガスを用いた反応性イオ
ンエツチング法により行なう。続いて、この配線
パターン上に、例えばSiH4とO2ガスを用いた減
圧気相成長法或いはSiH4とN2Oガスを用いたプ
ラズマ気相成長法により酸化シリコン膜４（絶縁
層）を披着する。なお、第１図には、アルミニウ
ム膜３の膜厚を約１〔μｍ〕、アルミニウム配線層
の巾を約２〔μｍ〕、隣接するアルミニウム配線層
の間隔を約３〔μｍ〕とし、酸化シリコン膜４を
約２〔μｍ〕被着した場合の断面状態を示してい
る。そして、この状態では酸化シリコン膜４には
比較的急峻な段差が生じている。Embodiment of the Invention FIGS. 1 to 3 are process sectional views showing an embodiment of the present invention. First, as shown in FIG. 1, a silicon oxide film 2 is deposited on a substrate 1 on which elements are formed by a thermal oxidation method, and then the necessary connection holes are made in the silicon oxide film 2, and the oxidation including these holes is performed. For example, an aluminum film 3 is formed on the silicon film 2 as a first conductor layer. The aluminum film 3 is deposited by sputtering or electron beam evaporation, and patterned by reactive ion etching using a mixed gas of CCl 4 and Cl 2 . Next, a silicon oxide film 4 (insulating layer) is formed on this wiring pattern by, for example, a low pressure vapor phase epitaxy method using SiH 4 and O 2 gas or a plasma vapor phase epitaxy method using SiH 4 and N 2 O gas. to show off. In addition, in FIG. 1, the thickness of the aluminum film 3 is approximately 1 [μm], the width of the aluminum wiring layer is approximately 2 [μm], the interval between adjacent aluminum wiring layers is approximately 3 [μm], and silicon oxide is shown. The cross-sectional state is shown when approximately 2 [μm] of film 4 is deposited. In this state, a relatively steep step is formed in the silicon oxide film 4.
次に、C3F8とH2との混合ガスを反応性ガスと
する反応性イオンエツチング法を用い、第２図に
示す如く前記酸化シリコン膜４の表面層を約１
〔μｍ〕の厚さエツチングする。このエツチング
は、平行平板電極の内、高周波印加側の電極に試
料を置き、C3F8流量20〔c.c.／min〕、H2流量２〜
10〔c.c.／min〕、RFpower50〜200〔Ｗ〕、圧力0.005
〜0.05〔Torr〕の範囲の条件で行なつた。エツチ
ング後、残存せしめた酸化シリコン膜４の表面は
なだらかな状態となる。これは、C3F8とH2との
混合ガスを用いた反応性イオンエツチング法によ
り酸化シリコンをエツチングした場合、段差縁部
のエツチング速度は平坦部のエツチング速度に比
べて大きいという現象を見出したことに基づいて
いる。つまり、陰極降下電圧によりグロー放電中
から引出されたイオン種が酸化シリコン膜４の表
面に対して斜めに衝突するほどエツチング進行を
阻害するＣ−Ｆポリマが付着し難くなるためと考
えられる。また、H2の添加はＦを減少させＣ−
Ｆポリマ生成の役を果たしているので、H2の添
加量が10〔％〕未満では、Ｃ−Ｆポリマがほとん
ど生成せず、エツチングは場所によらず垂直方向
に均一に行なわれ、段差縁部はなだらかにならな
い。また、H2添加量が増加するにつれ、化坦部
でのエツチング速度は減少し、エツチング後の段
差縁部の傾斜角は小さくなり、なだらかになる。
例えばH2添加量が２〔c.c.／min〕、６〔c.c.／min〕
に対して傾斜角はそれぞれ約70〔°〕50〔゜〕とな
る。 Next, using a reactive ion etching method using a mixed gas of C 3 F 8 and H 2 as a reactive gas, the surface layer of the silicon oxide film 4 is etched by about 100 ml, as shown in FIG.
Etch to a thickness of [μm]. In this etching, the sample is placed on the high-frequency application side of the parallel plate electrodes, and the C 3 F 8 flow rate is 20 [cc/min] and the H 2 flow rate is 2 to 20 [cc/min].
10 [cc/min], RFpower 50 to 200 [W], pressure 0.005
The test was carried out under conditions in the range of ~0.05 [Torr]. After etching, the surface of the remaining silicon oxide film 4 becomes smooth. This is due to the discovery of the phenomenon that when silicon oxide is etched using a reactive ion etching method using a mixed gas of C 3 F 8 and H 2 , the etching rate at the edge of the step is higher than that at the flat area. It's based on that. In other words, this is considered to be because the more obliquely the ion species extracted from the glow discharge due to the cathode drop voltage collide with the surface of the silicon oxide film 4, the more difficult it becomes for the C--F polymer, which inhibits the progress of etching, to adhere. Also, addition of H2 decreases F and C-
Since it plays the role of producing F polymer, if the amount of H 2 added is less than 10%, almost no C-F polymer is produced, and etching is performed uniformly in the vertical direction regardless of the location, and etching is performed uniformly in the vertical direction regardless of the location. It is not gentle. Furthermore, as the amount of H 2 added increases, the etching rate at the etched portion decreases, and the inclination angle of the step edge after etching becomes smaller and gentler.
For example, the amount of H2 added is 2 [cc/min], 6 [cc/min]
The angle of inclination is approximately 70 [°] and 50 [°], respectively.
次に、第３図に示す如く第２導体層として、例
えばアルミニウム膜５を前述した方法により形成
する。かくして形成された配線層は全体に亘つて
略一様な膜厚となり、断線もなく極めて良好なも
のであつた。さらに腐蝕や配線間のリーク電流等
も全く見られなかつた。 Next, as shown in FIG. 3, for example, an aluminum film 5 is formed as a second conductor layer by the method described above. The wiring layer thus formed had a substantially uniform thickness throughout, and was extremely good with no disconnections. Furthermore, no corrosion or leakage current between wiring was observed.
なお、本発明は上述した実施例に限定されるも
のではない。例えば、前記第３図に示した工程に
おいて、エツチング後の酸化シリコン膜４上に再
度酸化シリコン膜を披着した後、第２導体層を形
成してもよい。また、前記酸化シリコン膜４をエ
ツチングする際の条件として実施例では、C3F8
流量20〔c.c.／min〕に対し、H2添加量を２〜10
〔c.c.／min〕とした場合について説明したが、H2
添加量を更に多くした場合、即ち10〔c.c.／min〕
を越える場合は、酸化シリコン膜４の平坦部はエ
ツチングされずＣ−Ｆポリマが付着するが、段差
縁部はエツチングされなだらかな形状になるの
で、第１図に示した工程で酸化シリコン膜４の厚
さを約１〔μｍ〕として、エツチング後、平坦部
に付着したＣ−Ｆポリマを酸素プラズマで除去す
れば第２図と同様の状態になるので、H2添加量
が多い場合でも本発明は有効である。さらに、実
施例では第１導体層の上に被着した酸化シリコン
膜４に対する本発明の効果について述べたが、本
発明は半導体装置の製造工程で生ずるすべての段
差に適用することが可能である。また、実施例で
は酸化シリコン膜の場合について述べたが、不純
物として例えば燐、硼素、砒素等を少なくとも１
種類以上添加したシリケートガラス膜を用いても
よい。さらに、エツチングガスとしてはC3F8＋
H2の混合ガスの他にCF4＋H2、C2F6＋H2或いは
CHF3を用いることも可能である。その他、本発
明の要旨を逸脱しない範囲で、種々変形して実施
することができる。 Note that the present invention is not limited to the embodiments described above. For example, in the step shown in FIG. 3, a silicon oxide film may be deposited again on the etched silicon oxide film 4, and then the second conductor layer may be formed. In addition, in the embodiment, the conditions for etching the silicon oxide film 4 are C 3 F 8
For a flow rate of 20 [cc/min], the amount of H2 added is 2 to 10
Although we explained the case of [cc/min], H 2
If the amount added is further increased, i.e. 10 [cc/min]
If the silicon oxide film 4 exceeds the etching angle, the flat part of the silicon oxide film 4 will not be etched and the C-F polymer will adhere to it, but the step edges will be etched and have a gentle shape. If the C-F polymer adhering to the flat part is removed with oxygen plasma after etching with a thickness of approximately 1 [μm], the same state as shown in Fig. 2 will be obtained, so even if the amount of H 2 added is large, The invention is valid. Furthermore, although the embodiment described the effect of the present invention on the silicon oxide film 4 deposited on the first conductor layer, the present invention can be applied to all steps that occur in the manufacturing process of semiconductor devices. . In addition, although the case of a silicon oxide film was described in the embodiment, at least one impurity such as phosphorus, boron, arsenic, etc.
A silicate glass film containing more than one kind of additives may be used. Furthermore, as an etching gas, C 3 F 8 +
In addition to H 2 mixed gas, CF 4 + H 2 , C 2 F 6 + H 2 or
It is also possible to use CHF 3 . In addition, various modifications can be made without departing from the gist of the present invention.
第１図乃至第３図は本発明の一実施例を示す工
程断面図である。
１……基板、２……酸化シリコン膜、３，５…
…アルミニウム膜、４……酸化シリコン膜（絶縁
層）。
1 to 3 are process cross-sectional views showing one embodiment of the present invention. 1...Substrate, 2...Silicon oxide film, 3, 5...
...Aluminum film, 4...Silicon oxide film (insulating layer).
Claims (1)
いは不純物を含むシリケートガラス膜からなる絶
縁層を形成する工程と、Ｃ、Ｆ、Ｈを含む混合ガ
スを反応性ガスとする反応性イオンエツチング法
を用い上記絶縁層を全面エツチングする工程とを
具備したことを特徴とする絶縁層の平坦化方法。 ２ 前記反応性ガスとして、C3F8とH2との混合
ガスを用い、これらの流量比（H2／C3F8）を10
〔％〕以上の範囲に設定したことを特徴とする特
許請求の範囲第１項記載の絶縁層の平坦化方法。[Claims] 1. A step of forming an insulating layer made of a silicon oxide film or a silicate glass film containing impurities on a base surface having steps, and a reaction using a mixed gas containing C, F, and H as a reactive gas. 1. A method for planarizing an insulating layer, comprising the step of etching the entire surface of the insulating layer using a reactive ion etching method. 2 As the reactive gas, a mixed gas of C 3 F 8 and H 2 is used, and the flow rate ratio (H 2 /C 3 F 8 ) of these is 10.
The method for planarizing an insulating layer according to claim 1, wherein the amount is set to a range of [%] or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19216581A JPS5893259A (en) | 1981-11-30 | 1981-11-30 | Flattening method for insulating layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19216581A JPS5893259A (en) | 1981-11-30 | 1981-11-30 | Flattening method for insulating layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5893259A JPS5893259A (en) | 1983-06-02 |
| JPH0311543B2 true JPH0311543B2 (en) | 1991-02-18 |
Family
ID=16286764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19216581A Granted JPS5893259A (en) | 1981-11-30 | 1981-11-30 | Flattening method for insulating layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5893259A (en) |
-
1981
- 1981-11-30 JP JP19216581A patent/JPS5893259A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5893259A (en) | 1983-06-02 |
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