JPH0311683B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a power amplifier, and particularly to a power amplifier used as a high-output transistor amplification element.

(Prior Art) Recently, many high-output, high-frequency transistors have been developed, and their applications are being studied. Among these transistors, GaAS field effect transistors (hereinafter referred to as FETs) can be said to be the most suitable amplification element for high output and high frequency. This conventional
Figure 1 shows a power amplifier circuit with multiple stages of cascaded FETs. In the figure, FETs 1 each of which is always biased at a constant voltage value from a gate voltage terminal 4 and a drain voltage terminal 5 are connected in cascade in multiple stages, and a high-frequency signal is input to the input terminal 2 of a power amplifier in the first stage. , are amplified in multiple stages to a desired level, and are output from the output terminal 3.

In such conventional power amplifiers, even if the high-frequency input signal is a pulse, the gate of each FET,
Since the drain current remains at a constant value, DC power is wasted even when there is no high-frequency input signal, resulting in low power usage efficiency. on the other hand,
The power consumption of the power amplifier can be improved by supplying power to the gate voltage terminal 4 and drain voltage terminal 5 so as to turn on/off the gate voltage and drain voltage of the FET in synchronization with the pulse of the high-frequency input signal. . However, in this case too, when the drain voltage is increased to the rated value and a large peak drain current is passed in order to increase the output power of the power amplifier, the average channel temperature of each FET rises to near the rated temperature depending on the ambient temperature. Sometimes.
In such power amplifiers, when the repetition rate of the input pulse increases or the pulse width becomes wider,
Since the average channel temperature mentioned above increases further,
The drawback was that the reliability of the power amplifier decreased.

(Object of the Invention) The object of the present invention is to eliminate these drawbacks, maintain the average channel temperature of the FET constant even with variations in input pulse repetition rate and pulse width, and improve reliability with low power consumption. The object of the present invention is to provide a power amplifier that does not cause power degradation.

(Configuration of the Invention) The configuration of the power amplifier of the present invention includes a divider that divides a high-frequency input signal into two, an amplifier circuit to which one of the two divided signals is input, and a detector to which the other is input.
A detection circuit that detects the pulse repetition rate and pulse width of the high-frequency input signal from the detected signal, and a detection circuit that is used in the amplification circuit even if the pulse repetition rate and pulse width vary.
a signal generating circuit that generates a drain voltage from the detection circuit that always keeps the drain voltage of the FET in an optimal state so that the channel temperature of the FET is constant; used in the circuit
It is configured to include a control circuit that supplies the FET.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing a power amplifier according to an embodiment of the present invention. In the same figure, the amplifier circuit 11
may be substantially similar to the conventional power amplifier shown in FIG. Now, the high frequency input signal input from the input terminal 12 is divided into two by the divider 16, one is input to the amplifier circuit 11, the other is input to the detector 17, and the detected signal is sent to the detection circuit 18. Sent. This detection circuit 18 detects the pulse repetition rate and pulse width from the detected signal, and each detected data is supplied to the next signal generation circuit 19.
In the signal generation circuit 19, the amplifier circuit 11 is also used. The pulse repetition rate and pulse width that set the average channel temperature of the FET to a certain set temperature and the value of the drain voltage shown in Figure 3 are memorized, and the average channel temperature is calculated from the detected data of the pulse repetition rate and pulse width. The signal generating circuit 19 generates the optimum drain voltage to keep it constant. The optimum drain voltage obtained by the signal generation circuit 19 is converted into a pulse corresponding to the pulse of the high frequency input signal in the control circuit 20, and the pulsed optimum drain voltage is applied to the FET of the amplifier circuit 11. .

In the above embodiment, a part of the high frequency input signal of the power amplifier is extracted and detected in order to detect the state of the input pulse, but in addition to this, a pulse synchronized with the pulse of the high frequency input signal is received from the outside. A circuit that detects the repetition rate and width from the pulse may be used.

(Effects of the Invention) As explained above, according to the present invention, the pulse repetition rate and pulse width of a high-frequency input signal are detected, and the drain voltage is automatically adjusted based on the detection results so that the average channel temperature of the FET is constant. Since the drain voltage is supplied to the drain of each FET after the drain voltage is turned ON/OFF according to the pulse corresponding to the pulse of the high frequency signal, the power consumption is low, and the repetition rate of the pulse and the pulse are When the voltage fluctuates, the peak value of the drain voltage of each FET changes as well, so the FET channel temperature can be maintained at an optimal state, and amplification can be achieved without sacrificing reliability, making it easier than the conventional constant via method. Since the temperature is lower, if the temperature is allowed to rise to the same level as in the conventional case, effects such as being able to output even higher power can be obtained.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional power amplifier, Figure 2 is a circuit diagram showing a conventional power amplifier.
The figure is a block diagram showing a power amplifier according to an embodiment of the present invention, and FIG. 3 is a characteristic diagram showing the relationship between the repetition rate of input pulses, the pulse width, and the optimum drain voltage of the FET. In the diagram, 1...FET, 2, 12... Input terminal, 3, 1
3...Output terminal, 4,14...Gate voltage terminal,
5, 15...Drain voltage terminal, 11...Amplifier circuit, 16...Distributor, 17...Detector, 18...
Detection circuit, 19... signal generation circuit, 20... control circuit.

Claims (1)

[Claims] 1 A divider that divides a high-frequency input signal into two, an amplifier circuit having a high-frequency power amplification element that amplifies one signal from the divider, and a detector that detects based on the other signal from the divider. , a detection circuit that detects the pulse repetition rate and pulse width of the high frequency input signal from the signal detected by the detector, and a detection circuit that detects the high frequency input signal based on the data of the pulse repetition rate and pulse width from this detection circuit The power amplifier includes a signal generation circuit that generates an optimal bias voltage to be applied to the power amplification element, and a control circuit that supplies the bias voltage to the high frequency power amplification element in response to pulses of the high frequency input signal. A power amplifier featuring: