JPH0312329B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention provides a keyboard device in which a keyboard portion and a main body portion into which key input information from the keyboard portion is input are separated, in which a signal line connects the keyboard portion and the main body portion, and This relates to a device that identifies on the main body side whether an input operation has been performed using a key. A keyboard device usually has a main body part 1 and a keyboard part 2 separated, as shown in FIG.
The structure is such that several signal lines 3 are used to connect them. An example of the configuration of a conventional keyboard section is shown in a block diagram in FIG. In the figure, the keyboard section includes a keyboard 5 in which keys 4 are arranged in a matrix (by operating the keys 4, two
(the space between the signal lines is closed), the output latch 6
and the input latch 7,
8 data bus lines (D ₀ to D ₇ ), output latch select signal OSEL, input latch select signal
A total of 10 signal lines, one for each ISEL, connect the keyboard section and the main body section (not shown).
Although this conventional method has a simple hardware configuration, there are as many as 10 signal lines, so it is easy to make mistakes in connecting the signal lines, and the connectors used to connect the signal lines are special. Even if the lines were folded into a single line, the signal line would be quite thick, which had the disadvantage of posing a major obstacle when moving the keyboard section. Therefore, the conventional configuration shown in FIG. 3 is a configuration in which the number of signal lines is reduced and only one signal line is used to connect the main body and the keyboard. The one shown in the figure connects a keyboard 5 on which keys 4 are arranged in a matrix to the input/output terminals of a microprocessor unit (MPU) 8, and generates a clock signal from a clock generation circuit 10 using a crystal oscillator 9. This is a configuration in which the MPU 8 operates. This configuration allows MPU
By matching the operation program of 8 and the operation program of the main unit, it became possible to connect only one input/output signal line (SI/SO). However, with this method, although the number of signal lines is small, an operation program is required not only for the main body but also for the keyboard, making the operation program complicated. There are disadvantages such as not only the generation circuit 10 is required, but also the frequency accuracy thereof requires high frequency accuracy. The present invention eliminates the above-mentioned drawbacks of the prior art,
To provide a keyboard device in which the number of signal lines connecting a main body part and a keyboard part can be reduced to a certain extent just by using simple hardware. In order to achieve the above object, the present invention provides a keyboard device in which a keyboard section and a main body section into which key input information from the keyboard section is input are separated. A first scanning means is provided to scan each key of the keyboard section to identify which key has been inputted, and the main body section counts (scans) the clock signal and outputs the count value. providing a second scanning means consisting of a counter;
First, a synchronizing signal for starting scanning is sent to the first scanning means and the second scanning means, so that scanning by both scanning means is started simultaneously, and the key on which the input operation was performed is identified in the first scanning means. When it is done,
The identification output is sent from the first scanning means to the second scanning means to hold the scanning (count) output by the second scanning means at that time, and key input operation information on the keyboard section is obtained from the held output. can be determined from the main body. The present invention will be explained below using the drawings. FIG. 4 is a block diagram showing one embodiment of the present invention. In the figure, the keyboard section 2 receives a clock signal (pulse) input from the main body section 1.
Frequency divider circuit 11 that divides CLOCK, frequency divider circuit 1
Decoder circuit 12, 8 bits with three divided outputs Q _D , Q _E , Q _F of 1/16, 1/32, and 1/64 divided from 1 as 3 inputs A, B, and C. input data (A~
key scanning identification means consisting of a parallel-to-serial conversion circuit 13 that serially outputs Q _H) one bit at a time;
The keyboard 5 is arranged in a matrix at the intersection of the output line of the decoder 12 and the input line of the parallel-to-serial conversion circuit 13. Frequency divider circuit 1
1 is a circuit that generates frequency division value outputs (Q _C , Q _D , Q _E , Q _F ) as shown in Table 1 based on the count value of the clock pulse.

【table】

[Table]
The decoder circuit 12 decodes the input values of the input terminals A, B, and C, and as shown in Table 2, the output level of only one terminal among the output terminals _Q0 to _Q7 is "L".
This is a circuit that generates the decoded output.

[Table] The parallel-to-serial conversion circuit 13 takes in 8-bit parallel data (A to H) using the _QC output of the frequency divider circuit 11 every 8 input clock pulses, and serially converts the data into 1 bit for each clock pulse. This is a circuit that outputs from the Q _H terminal. In addition, the keyboard interface circuit of main unit 1 receives input clock pulses.
The scanning means is composed of two circuits: a counter circuit 14 that counts CLOCK, and a latch circuit 15 that latches the output of the counter circuit 14 at that point in time in response to the data signal DATA from the keyboard section 2. Here, the output terminal Q of the decoder circuit 12. The operation when the key 4 arranged at the intersection with the input terminal A of the parallel-to-serial conversion circuit 13 is pressed will be explained using the timing chart shown in FIG. First, a clear signal, which is a scanning synchronization signal, is sent from the main body 1 side.
CLEAR(b) goes from “H” level to “L”
level, the clear state is canceled and the frequency divider circuit 11 and counter circuit 14 receive the clock pulse
Start counting. Output terminal of frequency divider circuit 11
Since the output levels of Q _C , Q _D , and Q _E change as shown in FIG. The output level of _Q0 is at the "L" level. At the initial point when the output terminal _Q0J is at the "L" level, 8-bit parallel data is loaded into the parallel-to-serial converter circuit 13 triggered by a level change (H→L) of the _QC output of the frequency divider circuit 11. , among the input terminals A to H of the parallel-to-serial conversion circuit 13, only the input terminal A becomes "L" level. If this state is output as serial data, the clock pulse a
When the count value is 7, the "L" level becomes the scanning synchronization signal DATA (Fig. 5e) and the serial conversion circuit 1
It is output from the Q _H terminal of 3. Therefore, in the main body 1, when the counter circuit 14 counts 7, that is, when the output terminals Q _A of the counter circuit 14,
When the output levels f, g, h (see Fig. 5) of Q _B and Q _C reach the "H", "H", "H" level, the latch circuit 15 is connected to the synchronizing signal DATA (see Fig. 5). e), the latch circuit 15 detects that the key placed at the intersection of the output terminal Q ₀ of the decoder circuit 12 and the input terminal A of the parallel-to-serial conversion circuit 13 has been pressed.
This can be seen from the latch output. The operation when pressing the key 4 placed at the intersection of the output terminal Q ₀ of the decoder circuit 12 and the input terminal A of the parallel-to-serial conversion circuit 13 has been explained above, but the following will be summarized once again with a different expression. Explain in detail. The output terminal _Q0 of the decoder circuit 12 is at a low level until the first 8th clock pulse after the start of operation, and thereafter becomes a high level. Even if you keep pressing key 4, as soon as the level of output terminal Q ₀ changes from low level to high level, key 4
Pressing will no longer be recognized. That is, the output terminals of the decoder circuit 12 are Q ₀ , Q ₁ ,
Q ₂ , Q ₃ , . . . fall to a low level in the order of eight clock pulses, and so-called scanning is performed. Regarding the output terminal Q ₀ , if the key 4 is pressed while the output terminal Q ₀ is at low level, the state changes to the level change of the Q _C output of the frequency dividing circuit 11 ( The signals are read in parallel into the parallel-to-serial conversion circuit 13 at the timing of H→L), and are counted based on the position on the clock where the key 4 is pressed. Even if the key 4 is held down for a long time, false detection will not occur, but if the period of time that the key 4 is held down is too short, theoretically, detection will be missed. However, this occurs depending on the clock cycle. In the present case, one scanning period is 8 clocks each for Q ₀ , Q ₁ , ..., Q ₇ , that is, 8 x 8 = 64 clocks, so if the clock frequency is 1 MHz, one clock is Since this is 1 microsecond, one scanning period ends in 64 microseconds. If the key 4 is not held down at least during one scanning period of 64 microseconds, detection may be missed. However, human movements, no matter how fast, are on the order of milliseconds, so this keyboard device can respond sufficiently. Another embodiment of the main body side of the present invention is shown in FIG. In the figure, a counter circuit 14, a flip-flop circuit 16, and a gate circuit 17 constitute scanning means. The flip-flop circuit 16 is
When the scanning synchronization signal DATA from the keyboard section is input, the output level of the output terminal is changed from "H" level to "L" level, and the gate circuit 17 is activated.
Turn it off. Therefore, the clock signal input to the counter circuit 14 starts counting and then receives the scanning synchronization signal DATA from the keyboard section.
It will be limited to the period until it is input. In this embodiment, the final count value (information representing the pressed position of the key) is input to the address terminals (A ₀ to A ₅ ) of the ROM circuit 18, and the code is written according to the contents stored in advance in the ROM. The pressed position of the key is transferred to the data terminal (D ₀
It is configured to output from ~ _D7 ). Furthermore, by using the output signal CLOCK' of the gate circuit 17 as the clock signal supplied to the keyboard section, it is possible to read a plurality of key inputs. Scan synchronization signal CLEAR from the main unit side
The counting operation of the counting circuit 14 that started counting is stopped by the DATA signal, which is a scanning synchronization signal from the keyboard section, and at the same time, a strobe signal is sent to notify the central processing unit (not shown) of the main body that a key has been input. is generated from the terminal of flip-flop 16. The central processing unit reads the code of the key at this time and generates a count continuation signal for searching for the next key input. This count continuation signal is logically summed with the clear signal CLEAR by the OR circuit 19, and the logical sum output is output from the flip-flop circuit 16.
Input to CLEAR terminal. That is, the counting circuit 14 that started counting by the clear signal CLEAR stops counting every time the data signal DATA is input, or continues counting by the counting continuation signal, so that the central processing unit can You can know the key input. FIG. 7 is a block diagram showing another embodiment of the keyboard portion of the present invention. A frequency divider circuit 11 that divides the clock signal CLOCK (pulse) input from the main body, 1/2 frequency division, 1/4 frequency division from the frequency divider circuit 11
The three divided outputs Q _A , Q _B , Q _C of frequency division and 1/8 frequency division are
A decoder circuit 12 with inputs A, B, and C, and three frequency division outputs Q _D , Q _E , Q _F of 1/16 frequency division, 1/32 frequency division, and 1/64 frequency division from the frequency dividing circuit 11. The present embodiment is comprised of a key scanning identification means consisting of a multiplexer 20 with 8 inputs and 1 output, which has 3 inputs A, B, and C as select signals, and a keyboard 5 in which keys 4 are arranged in a matrix. Since the frequency divider circuit 11 and the decoder circuit 12 have already been described when explaining the embodiment of FIG. 4, their explanation will be omitted here. The multiplexer 20 selects a signal according to the signal level input to the select signal input terminals A, B, and C.
This circuit selects any one of input data D ₀ to D ₇ as shown in Table 3. Clear signal which is a scanning synchronization signal from the main unit side
When CLEAR goes to "L" level, the clear state is released and the frequency dividing circuit 11 starts the frequency dividing operation. Each time the clock pulse CLOCK is input, only one of the output terminals _Q0 to _Q7 of the decoder 12 goes to the "L" level, and the clock pulse goes around once every eight clock pulses.

[Table] Since the multiplexer 20 switches the data input terminals D ₀ to D ₇ to be selected and outputs them to the output terminal Y every 8 clock pulses, scanning of the keys of the keyboard 5 is completed with 64 clock pulses. As described above, according to the present invention, in a keyboard device in which the keyboard portion and the main body portion are separated, the number of signal lines connecting the keyboard portion and the main body portion is small, which may cause obstacles when moving the keyboard portion. The hardware of the keyboard interface circuit is simple.The clock signal on the keyboard and the clock signal on the main body are the same, and there is no need for a special clock signal for the keyboard, making it economical. This has advantages such as simple input software. Further, it goes without saying that the advantages of the conventional embodiments shown in FIGS. 2 and 3 are directly incorporated into the present invention. Note that in the above-described embodiments, explanations and illustrations of the ground line common to the power supply line and each signal line are omitted.

[Brief explanation of the drawing]

Fig. 1 is a perspective view of a keyboard device, Fig. 2 is a block diagram showing an example of the structure of a conventional keyboard section, Fig. 3 is a block diagram showing an example of the structure of another conventional keyboard section, and Fig. 4 is a block diagram showing an example of the structure of a conventional keyboard section. A block diagram showing one embodiment of the present invention, FIG. 5 is a timing chart of signals of each part to explain the operation of the embodiment of FIG. 4, and FIG. 6 is a block diagram showing another embodiment of the present invention. , and FIG. 7 is a block diagram showing still another embodiment of the present invention. Description of symbols, 1...Main unit, 2...Keyboard section, 3...Signal line, 4...Key switch,
5... Keyboard, 11... Frequency dividing circuit, 12...
Decoder circuit, 13... Parallel-to-serial conversion circuit, 14...
Counter circuit, 15... Latch circuit, 16... Flip-flop circuit, 17... Gate circuit, 20
...Multiplexer.

Claims (1)

[Scope of Claims] 1. A keyboard device in which a keyboard portion and a main body portion into which key input information from the keyboard portion is input are separated, the keyboard portion including:
A first scanning means is provided which scans each key of the keyboard section in synchronization with an input clock signal to identify which key has been inputted, and the main body section is provided with a means for counting (scanning) the clock signal. A second scanning means comprising a counter for outputting the count value is provided, and first, a synchronizing signal for starting scanning is sent to the first scanning means and the second scanning means to start scanning by both scanning means. When the first scanning means identifies a key that has been inputted, the identification output is sent from the first scanning means to the second scanning means, and the second scanning at that point is performed. A keyboard device characterized in that a scanning (count) output by the means is held, and key input operation information on the keyboard part can be determined from the held output in a main body part. 2. In the keyboard device according to claim 1, the first scanning means comprises a frequency dividing circuit that divides the frequency of an input clock signal, and a decoding circuit that decodes the frequency divided output from the frequency dividing circuit. , and a multiplexer circuit that receives different decoded outputs from the decoder circuit to the data input terminal at different timings depending on which key is input operated, and the second scanning means counts the input clock signal. A keyboard device comprising: a counter; and means for holding a count value in the counter when an output signal from the multiplexer circuit arrives.