JPH0312338B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access scheme in a memory system having multiple memory banks and multiple read/write ports.

In general, a general-purpose computer or MIMD (Multiple Iestruction
In the memory system of a supercomputer with a multiple data (Multiple Data) architecture (hereinafter abbreviated as a MIMD supercomputer), the memory system connected to each processor is designed to have as small a memory space as possible and to improve processing performance. I have a request.

As mentioned above, when trying to configure a small memory space, it is necessary to share memory for instructions and memory for data. It is necessary to separate it from memory.

Furthermore, among application programs executed on general-purpose computers or MIMD type supercomputers, there are programs with a large amount of programs but with a small amount of data, and conversely, programs with a small amount of programs but with a large amount of data. Even in application programs, it is necessary to configure a memory system that improves memory usage efficiency.

Due to these circumstances, program memory and
In order to make the memory space as small as possible and improve processing performance by sharing data memory, the instruction area and data area are separated, and each application program has its own instruction area and data area. There was a need for a method of configuring a memory system that could be freely changed.

[Conventional technology and problems]

There are two types of memory systems used in conventional general-purpose computers or MIMD-type supercomputers: those in which program memory and data memory are shared, and those in which they are separated. .

In a common memory system, there is an advantage that the memory system itself can be made smaller.
Since the data cannot be retrieved when issuing a succession of instructions, it has the disadvantage that it cannot cope with the increase in speed of the data processing system.

A memory system with a separate memory system can cope with speeding up the data processing system, but with a conventional system in which the sizes of instruction memory and data memory are fixed, the program size and the amount of data vary depending on each application program. , and the amount of data are different, so there is a problem that the efficiency of using the memory is reduced.

In view of the above-mentioned conventional drawbacks, the present invention provides a processor in a high-speed computer or a MIMD type supercomputer that has separate memory for instructions and memory for data, in which the memory of each processor is configured with a plurality of banks, It is an object of the present invention to provide a method of allocating, for example, program memory and data memory of optimum size in consecutive bank units for each program executed by each processor, and accessing them simultaneously.

[Means for solving problems]

This purpose is a high-speed computer that has separate memory for instructions and memory for data, or
In a memory system connected to each processor of a MUMD type supercomputer and having multiple memory banks and multiple read/write ports, for example, a program memory area/ A configuration designation register is provided to continuously designate the data memory area in bank units, and depending on the contents of the configuration designation register, the program memory area/data access area can be exclusively specified for each port. This is achieved by the memory access method according to the present invention that allocates in bank units and controls simultaneous access.

[Effect]

That is, according to the present invention, a high-speed computer or
The memory for each processor of the multiple processors of a MIMD type supercomputer is configured into multiple banks, and for each port that accesses the memory, for example, the program memory area/data memory area is contiguously arranged in banks. A configuration designation register is provided that is specified in units, and the optimal program memory area and data memory area are allocated to each program according to its contents.
This has the advantage that a plurality of access areas, such as a program area and a data area, of an optimal size can be allocated consecutively to each program and can be accessed simultaneously.

[Examples] Examples of the present invention will be described in detail below with reference to the drawings.
FIG. 1 is a diagram schematically showing an embodiment of the present invention;
FIG. 2 is a block diagram showing an embodiment of the address path, FIG. 3 is a block diagram of an embodiment of the data path, and FIG. 4 is a block diagram of an embodiment of the address path. FIG. 3 is a diagram showing an example of detecting an exceptional event.

In FIG. 1, 1 is a bank (0 to 15) constituting the memory system, 2 and 3 are ports for accessing the memory, and address A part 21, data A part 22, address B part 31, data B Part 3
It consists of 2. 4 is an access control circuit, 5
1 is a configuration designation section related to the present invention, which is composed of a configuration designation register 51, a configuration designation circuit 52, and an address exception check circuit 53. Further, A is an address line, AE is a bank enable signal, and D is a data line.

In this embodiment, 2 ports, 16 banks,
Consider a memory system with 1MB/bank.

Now, when memory access is performed from memory access ports A2 and B3 to each bank 1, the configuration designation circuit 52 and access control circuit 4 are activated according to the contents of the configuration designation register 51, and each port 2 , 3, the banks designated by the configuration designation register 51 are controlled to be accessed independently.

The details of the above operation are shown in FIGS. 2 and 3, with FIG. 2 relating to address path control and FIG. 3 relating to data path control.

First, referring to FIG. 2, the operation of the address path when the present invention is implemented will be explained.

In Figure 2, 1 to 4, 21, 22, 31,
32, 51, 52, A, D, and AE are the same as those explained in FIG. 21 and 31 are bank numbers (hereinafter referred to as BN-A and BN-B), respectively.
and the address in the bank (hereinafter BA-A, BA-B
). 41 is an adder (ADD), 42 is a decoder (DEC), 43 is an OR circuit, 44 is a multiplexer (hereinafter referred to as MPX),
521 is a decoder & logic circuit (hereinafter referred to as DECL),
The above configuration specification register (hereinafter referred to as CSR) 51
Of the output lines that decode the value set in and set a specific data pattern in the 16-bit configuration control register corresponding to each bank described later, the output on the left side (that is, the smaller number side) of the decoded value Line “0”
Then, the output line on the right side (that is, the higher number side) including the decoded value is output as "1". 522 is a 16-bit configuration control register (hereinafter referred to as CSBR) corresponding to the number of memory banks, and its output signal controls the multiplexer (MPX) 4.
4, and when the output signal is "0", selects the address (BA-A) of port A2 and outputs "1".
At this time, it operates to select the address of port B3 (BA-B).

Now, in CSR51, set the offset value (for example, 1 to 14) that specifies the boundary of BN-B31 of port B3.
is set (generally, when compiling a program, the sizes of the program's data area and instruction area are known, so the above offset value can be set in the CSR 51 in advance before program execution). Due to the above output conditions of the DECL521 logic circuit, the CSBR522, which is composed of 16 bits, has "0" on the left side of the bit position corresponding to the CSR value, and "0" on the right side including the corresponding bit position. "1" is set.

Address section 21 of each port A2, port B3,
31 contains a 4-bit bank number register (BN-A, BN-B) (specifying 16 banks) and a 20-bit bank address register (BA-A, BA-B) (specifying each byte of IMB). There is B).

Furthermore, port B3 has an adder (ADD) for adding the offset value to the BN-B31.
There are 41.

The bank number (BN-A) 21 and the bank number (BN-B) 31 plus the offset value CSR51 are decoded by the decoder (DEC) 42, and one of the 16 decode outputs is attached. each of which is connected to an OR circuit 43 for each port.
The bank enable signal AE is passed through the bank and activates each bank.

Address in the above bank (BA-A21, BA-
B31) is sent to each bank as an address A through the MPX 44 which is selectively controlled by the CSBR 522 for each bank, and only the bank that has received the bank enable signal AE is accessed by the address A. That will happen.

The above are the main operations of each functional block.
The overall operation is explained as follows.
That is, if we consider the case where each instruction of a certain program is read from port A2 and operand data is read from port B3, as described above, when the program is coil piled, each instruction area and data area are Since the size of the program is known, the offset value corresponding to each size is set in the CSR51 before executing the program.
By setting this, the CSBR 522 operates so that the bit specifying the instruction area becomes "0" and the bit specifying the data area becomes "1".

Therefore, when fetching each instruction, the above CSBR
Only the address in the bank selected by the bit set to 0 in bit 522 is sent to the bank as address A, and when the instruction is executed to read the operand data, the above
Only the address within the bank selected by the bit set to "1" in CSBR 522 is sent as address A to the bank.

On the other hand, from port A2, bank number BN-A for reading instructions is sent to its side decoder (DEC) 4.
2, and is sent to the bank through the OR circuit 43 as a bank enable signal AE. Also, from port B3, bank number BN-B for reading operand data is CSR51.
The adder (ADD) 41 adds the offset value to the offset value set in sent to the bank.

In other words, the offset value specifies the boundary bank number of the operand data area, and even if the memory addresses of instructions and data in the program have independent address spaces, the offset value This allows the memory space that can be accessed by the two ports to be divided into banks.

In this way, the address A in the bank and the bank enable signal AE are selectively controlled by the offset value set in the CSR51, so the bank for the instruction (corresponding to port A2) of the program and the operand When the bank for data (port B3 compatible) is accessed,
The information is automatically segmented and accessed, and this switching operation is the main focus of the present invention.

Next, as shown in FIG. 3, the data portions (data A22, data B32) of each port A2 and port B3 are
The selection control will be explained.

Data section of port A2 and port B3 (data A
22, Data B32) is also CSBR
The bidirectional selector selected by 522 (hereinafter
It is controlled to be connected to a data input/output section (not shown) of each bank through a BSEL (BSEL) 45.

That is, the BSEL 45 to which the bit of CSBR 522 is connected selects the data line (data A22) of port A2, and the BSEL 45 to which the bit of CSBR 522 is connected selects the data line of port A2 (data A22).
It is controlled to select the data line (data B32) of port B3. Therefore, the address section 2
The operation is exactly the same as the selection control of Nos. 1 and 31.

Next, details of the address exception check circuit 53 mentioned in FIG. 1 are shown in FIG. 4.

In this figure, 21, 31, and 51 are the same as those explained in FIGS. 2 and 3. 531 is an adder (ADD), 532 and 533 are comparators (CMP1, CMP2), and 534 is a NOR circuit.

If BN-A21≧CSR51 (offset value) or BN-B31+CSR51 (offset value) > total number of banks (=16), the memory bank numbers (BN-A21, BN -B31)
However, the value of the comparator (CMP1, CMP2) becomes "1" and the output of the NOR circuit 534 becomes "0" because it exceeds the area of each instruction and data determined when compiling the program. It is controlled to generate an address exception signal.

In the above embodiment, as is clear from FIG. 2, the access processing from port A2 is assumed to start from bank 0, and the access from port B3 is assumed to start from the bank number set as the offset value in CSR51. As described above, considering the gist of the present invention, the method of giving an offset value is not limited to specifying the access area from port B3. For example, in order to specify the access area from port A2, CSR5 above
1, and setting an offset value for port A2 in the register;
It goes without saying that the starting bank number for access from port A2 may be determined.

In addition, although this embodiment has been explained using an example of two ports, even if there are three or more ports, by providing a plurality of the above configuration specification registers, switching control of bank access from each port can be performed. Needless to say, there is nothing that can be done.

Furthermore, in this embodiment, memory access from two ports has been explained as accessing instruction and operand data, but this need not be limited to this embodiment. For example, memory access ports from multiple processors may be used. It is clear that it is good to do so.

〔Effect of the invention〕

As explained above in detail, the memory access method of the present invention configures the memory for each processor in a plurality of processors of a high-speed computer or a MIMD type supercomputer into a plurality of banks, and accesses the memory. For example, a configuration designation register is provided to sequentially specify the program memory area/data memory area in bank units, and the program memory area/data is specified for each port according to the contents of the configuration designation register. Multiple access areas, such as memory areas, are exclusively allocated in bank units and accessed simultaneously, so even memory with a small memory space can be accessed without reducing the processing performance of the processor. , it is possible to allocate banks optimally for each application program, and has the effect of not reducing memory usage efficiency.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an outline of an embodiment of the present invention, FIG. 2 is a block diagram of an embodiment of the address path, and FIG. 3 is a block diagram of an embodiment of the data path. The diagram shown in FIG. 4 is a diagram showing an example of detecting an address exception event when the present invention is implemented. In the drawing, 1 is a bank (0 to 15) constituting the memory system, 2 and 3 are ports for accessing the memory, and 21 is an address section A (BN-
A, BA-A), 31 is the address B part (BN-B,
BA-B), 22 is data A section (data A), 32
is a data B section (data B), 4 is an access control circuit, 5 is a configuration specification section, 51 is a configuration specification register (CSR), 52 is a configuration specification circuit, 53 is an address exception check circuit, 41 is an adder (ADD) , 42
is a decoder (DEC), 43 is an OR circuit, 44 is a multiplexer (MPX), 45 is a bidirectional selector (BSEL), A is an address line, AE is a bank enable signal, D is a data line, 521 is a decoder & logic circuit ( DECL), 522 is a configuration control register,
531 is an adder (ADD), 532 and 533 are comparators (CMP1, CMP2), and 534 is a NOR circuit.

Claims (1)

[Claims] 1. In a memory system having a plurality of memory banks and a plurality of read/write ports, a configuration designation register is provided that successively specifies a plurality of access areas for each port in bank units, and the configuration designation register Depending on the contents of the above multiple access areas for each port,
A memory access method characterized in that the memory banks are controlled to be exclusively allocated in bank units and accessed simultaneously.