JPH0312340B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output device for a programmable controller, and more particularly to an input/output device that can exchange input/output data with a controller main body by serial data transmission.

Recently, relatively large-scale centralized control systems using programmable controllers are often seen in control systems for general mechanical plants and the like. In such a centralized control system,
In many cases, various input devices, such as limit switches, temperature switches, proximity switches, photoelectric switches, etc., and various output devices, such as motors, plungers, solenoid valves, etc., are each connected to a central control device by separate signal lines. In this case, in systems where there are a large number of these input/output devices and each input/output device is dispersed over a relatively wide space, the wiring space and wiring cost that connect each input/output device and the central control unit become a major problem. Therefore, there is a strong desire to simplify signal transmission during this time by applying appropriate multiplex transmission.

Various multiplex transmission systems have been known in the past, and some have been used to transmit input/output data in programmable controllers. However, in the conventional multiplex transmission system, a unique address is assigned to each terminal, and each terminal has a circuit for determining the address, and the transmission control procedure including this address determination circuit is extremely complicated and sophisticated.
Therefore, it is an expensive device. Of course, there is some significance in using such an advanced circuit system, but
The input/output data transmission system in the programmable controller has many unnecessary functions, and therefore cannot adequately meet the above-mentioned demands.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to configure an input/output device separately from the controller main body, and to connect the required number of input/output devices to the controller main body through serial data lines. By simply connecting with two signal lines, the and clock signal line, there is no need for an address discrimination circuit on the input/output device side, and the output data from the controller main body to the input/output device can be transferred without going through troublesome transmission control procedures. An object of the present invention is to provide an input/output device for a programmable controller that can transfer and transmit input data from the input/output device to the controller main body.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

Figure 1 shows a programmable system to which this invention is applied.
1 is a block diagram showing the overall schematic configuration of a controller system. FIG. This programmable controller is divided into a controller body 1 and a plurality of input/output devices 2, 2, . . . . In this embodiment, a plurality of input/output devices 2, 2,...
have exactly the same configuration. Each input/output device 2 is connected to various input devices such as limit switches 4
It does not have one input terminal and four processing terminals to which various output devices such as motors and plungers are connected. The signals applied to each input terminal are called external input signals, and these signals are applied to IN1 to IN4, IN5 to IN8, IN
Assign a different number from 9 to IN12. Similarly, the signal output from the output terminal of the input/output device 2 is called an external output signal, and this signal is
4. Assign separate identification numbers to OUT5 to OUT8 and OUT9 to OUT12.

The controller main body 1 includes a CPT 3 (central processing unit) that serves as the center of overall control, a system program memory 4 that stores system programs executed by the CPU 3, and a temporary storage area for various variable data by the CPU 3. A system data memory 5 to be used, a user program memory 6 in which a sequence control program arbitrarily set by the user is stored, and an input/output memory serving as a buffer memory for input/output data corresponding to external input/output signals in the input/output device 2. It is provided with a memory 7 and an input/output port 8 serving as an interface for providing output data from the controller main body 1 to the input/output device 2 and for taking input data from the input/output device 2 into the controller main body 1.

As is well known, the execution operation of a user program in this type of programmable controller basically involves sequentially reading out user instructions from the user program memory 6, and executing the input/output memory 7 stored in the input/output memory 7 according to each user instruction. It is to perform arithmetic processing between output data and update the output data in the input/output memory 7 according to the result of the calculation,
In addition, an input update operation that writes input data from the input/output device 2 to a predetermined area of the input/output memory 7 in synchronization with the execution of the user program, and transfers output data of the predetermined area of the input/output memory 7 to the input/output device 2 An output update operation is performed, and as a result, a sequence state specified by the user program is created in the relationship between the input data applied to the input/output device 2 and the output data outputted from the input/output device 2. The input/output data transmission according to the present invention is the input/output data transmission performed between the controller main body 1 and the input/output device 2 in order to perform the above-mentioned input update operation and output update operation.

The controller body 1 includes a serial data input/output terminal SDT and a clock signal output terminal CKT as terminals for data transmission. The signal applied to the serial data input/output terminal SDT is the receiver 9
is applied to input port P1 via. The signal from the output port P2 is outputted to the serial data input/output terminal SDT via the driver 10. This driver 10 is inhibited by a signal from output port P3. A clock signal outputted from output port P4 is outputted via driver 11 to clock signal output terminal CKT.

The input/output device 2 has a left serial data input/output terminal SDL, a right serial data input/output terminal SDR, and a clock signal input terminal as terminals for data transmission.
Has CKL. In the three input/output devices 2, each other's right serial data input/output device SDR and left serial data input/output terminal SDL are connected by a serial data line 12, and each other's clock signal input terminal CKL is connected by a clock signal line 13. , these two transmission lines 12,1
3, the three units are connected in series. Also, the left serial data input/output terminal of the leftmost input/output device 2
SDL is also connected to the serial data input/output terminal SDT of the controller main body 1 by a serial data line 12,
The clock signal input terminal CKL is also connected to the clock signal output terminal CKT of the controller body 1 via a clock signal line 13. That is, the three input/output devices 2 are connected in series to the controller body 1 via the serial data line 12, and are connected in parallel to the clock signal line 13. Further, the right serial data input/output terminal SDR of the rightmost input/output device 2 is opened, and another input/output device 2 can be further connected in series to this open right serial data input/output terminal SDR.

FIG. 2 shows a detailed circuit diagram of one input/output device 2. As shown in FIG. As shown in the figure, this input/output device 2 includes a 4-bit unidirectional shift register 14,
Parallel output terminals Q1 to Q4 of this shift register 14
A latch circuit 15 connected to the latch circuit 15, a driver 16 that outputs the output of the latch circuit 15 in parallel as external output signals OUT1 to OUT4, and an external input signal
A receiver 17 receives signals IN1 to IN4 in parallel and applies them to the parallel input terminals D1 to D4 of the shift register 14, a receiver 19 receives a signal applied to the left serial data input/output terminal SDL, and a left serial data input/output terminal. A gated driver 20 that sends a signal to SDL, a receiver 21 that receives a signal applied to the right serial data input/output terminal SDR, a gated driver 22 that sends a signal to the right serial data input/output terminal SDR, and a clock signal. input terminal
a receiver 23 that receives a signal applied to CKL;
Left serial data input/output terminal for the serial input terminal SI and serial output terminal Q4 of the shift register 14
A switching circuit (consisting of the gated drivers 20, 22 and logic gates G1, G2, G3) that inverts the connection relationship between SDL and the right serial data input/output terminal SDR, and a clock signal input terminal
A control circuit 18 detects that the level of the signal applied to CKL is fixed for a certain period of time or more, and generates a latch signal for the latch circuit 15, a parallel input read signal for the shift register 14, and an inverted signal for the switching circuit. Be prepared.

The signal applied to the clock signal input terminal CKL is received via the receiver 23 and is input as the shift clock signal CK to the shift register 14 as well as to the control circuit 18.

In the control circuit 18, when the period of the clock signal outputted from the controller body 1 to the clock signal line 13 is TO, the clock signal is stopped and the signal level of the signal line 13 is fixed at H level or L level. This is to detect that a certain period of time T1 or more, which is sufficiently larger than the clock period TO, has continued. This detection is performed by an EOR circuit 25, a timer circuit 26, and a flip-flop 27. Flip-flop 27 is initially reset by power-on reset circuit 50 when power is turned on. The output Q of the flip-flop 27 and the output signal a of the receiver 23 (signal on the clock line 13) are input to the EOR circuit 25, the output signal b of which is input to the timer circuit 26, and the output signal c of the flip-flop 27 causes the flip-flop 27 to be activated. It is now controlled in reverse.

The timer circuit 26 outputs an output signal c when the input signal b goes to the L level and remains at the L level continuously for the above-mentioned fixed time T1, and the flip-flop 27 is inverted. Therefore, when the flip-flop 27 is reset and Q=H, the timer circuit 26 outputs the clock signal line 13.
The flip-flop 27 acts to detect when the signal a of
When Q is reset and Q=L, it acts to detect that the signal a on the clock signal line 13 has been fixed at the L level for a period of time T1 or more.

The output of the flip-flop 27 becomes a control signal for the switching circuit. In other words, flip-flop 27
has been reset and Q=L,=H,
The driver 20 and logic gate G2 are disabled, and the driver 22 and logic gate G1 are activated. In this state, the left serial data input/output terminal
The signal applied to SDL is input to the serial input terminal SI of the shift register 14, and the signal from the serial output terminal Q4 of the shift register 14 is led to the right serial data input/output terminal SDR. On the contrary, flip-flop 27 is set and Q=H,=L
In this case, the signal applied to the right serial data input/output terminal SDR is inputted to the serial input terminal SI of the shift register 14, and the signal from the serial output terminal Q4 of the shift register 14 is applied to the left serial data input/output terminal.
Derived to SDL.

Further, when the Q output of the flip-flop 27 rises to the H level, it is detected by a differentiation circuit 28 for detecting a rising edge, and the output pulse of this differentiation circuit 28 is applied as a latch signal T to the latch circuit 15.
The Q output of the flip-flop 27 is slightly delayed by a delay circuit 29, and the delayed output is input to a differentiation circuit 30 for rising edge detection, and the output pulse from this differentiation circuit 30 is used as the parallel input read signal LSD of the shift register 14. applied.

Furthermore, the output signal a of the receiver 23 is input to a differentiation circuit 51 for rising and rising edge detection, and a minute pulse is generated at a change point of the signal a. The pulse output from the differentiating circuit 51 becomes a trigger signal for the timer circuit 52. This timer circuit 52 is disconnected from the clock signal line 1 due to a failure in the controller main body 1.
This is to detect that the signal 3 has been fixed at a constant level for a long time, and when the signal a has been fixed for a fixed time T3 or more, which is sufficiently longer than the set time T1 of the timer circuit 26, the timer circuit 52 outputs the signal a. A signal is generated. The output signal of this timer circuit 52 is inputted to an OR gate 53 together with the output signal of the power-on reset circuit 50, and the output of the OR gate 53 becomes a reset signal for the flip-flop 27 and a reset signal for the latch circuit 15. These differentiating circuit 51 and timer circuit 52 constitute a reset circuit that detects an abnormality in controller body 1 and returns control circuit 18 and latch circuit 15 to their initial states.

Next, the transmission operation of input/output data on the controller main body 1 side will be explained. Controller body 1
is from port P4 of input/output port 8 to driver 1
A predetermined number of clock signals are sent to the clock signal line 13 via the clock signal line 13 to shift the shift register 14, and at the same time, output data is sequentially serially transmitted from the port P2 to the serial data line 12 via the driver 10 in synchronization with this. These output data are set in the shift register 14 by outputting them to
After that, the level of the clock signal line 13 is maintained for a certain period of time T.
By fixing 1 or more, the above shift register 1
The output data set to 4 is latched in the latch circuit 15, and the receiver 1
7 is read into the shift register 14, the switching circuit is inverted, and then a predetermined number of clock signals are sent to the clock signal line 13 to shift the shift register 14 again, and the shift register 14 is set. The input data is sequentially input into the controller main body 1 from the port P1 of the input/output port 8 via the serial data line 12 and the receiver 9. This operation is performed by the CPU 3 executing an input/output data transfer routine stored in the system program memory 4.

FIG. 3 is a flowchart showing an outline of the input/output data transmission routine. A detailed explanation of the data transmission operation according to this flowchart:
In the first step 301, the output port P4 is set to L level. In the next step 302, the address of the last output data OUT12 is set. In the next step 303, the output data of the set address is
Output OUT12 from output port P2. In addition,
At this time, it goes without saying that the driver 10 is activated by the signal from the output port P3.

In the next step 304, the signal at the output port P4 is set to H level. In the next step 305, time T, which is slightly shorter than the period T0 of the clock signal, is counted. At step 306 after T time has elapsed, the signal at output port P4 is set to L level. next step
In 307, it is determined whether transmission up to output data OUT1 has been completed. If the transmission has not been completed, proceed to step 308 and set the address of the output data to 1.
and set the address of output data OUT11. Then, the process returns to step 303.

Above steps 303→304→305→306→307→308
is repeated for the output data OUT12 to OUT1, so that each output data is output from the controller main body 1 in synchronization with the clock signal.

When the above-described output data transmission operation is completed, the process proceeds from step 307 to step 309, and the signal at output port P4 is set to H level. In the next step 310, the time T1 required to operate the control circuit 18 is counted. As a result, the signal level of the clock signal line 13 is fixed at the H level for more than T1 time, the control circuit 18 is operated, the output data set in the shift register 14 is latched in the latch circuit 15, and the driver 16 is latched. At the same time, the input data from the receiver 17 is read into the shift register 14, and the connection relationship of the switching circuit is reversed.

On the controller main body 1 side, in the next step 311, the address of the first input data IN1 is set.
In the next step 312, the process waits for the delay time T2 of the delay circuit 29. Further, the driver 10 is inhibited by a signal from the output port P3. In the next step 313, the input data applied to the input port P1 is read and stored at the set address. In the next step 314, the signal at the output port P4 is set to L level. In the next step 315, the above-mentioned time T is counted. In the next step 316, the signal at the output port P4 is set to H level. In the next step 317, it is determined whether data up to input data IN12 has been captured. If it has not been completed, the process advances to step 318, where the address of the input data is incremented and the address of the second input signal IN2 is set. Thereafter, the process returns to step 313. In addition, the second
As shown in the figure, the numbers of the parallel input terminals D1 to D4 of the shift register 14 and the input terminals IN1 to IN4 are reversed.

Above steps 313→314→315→316→317→318
is repeated for the input data IN1 to IN12, so that each input signal set in the shift register 14 is sequentially taken into the input port P1,
The data are sequentially written into predetermined areas of the input/output memory 7.
When this input data capture operation is completed, the process advances from step 317 to step 319, and the output port P4
signal to H level. In the next step 320, the time T1 required to operate the control circuit 18 is counted. This returns the control circuit 18 and the switching circuit to their initial states. The above operations are performed in parallel with the execution of the user program.

By the way, if the clock signal line 13 is disconnected or the clock signal transmission system of the controller body 1 is broken, the clock signal input terminal of the input/output device
The signal applied to CKL is for a long time (time T3
(above)) When the level remains fixed at a certain level, the abnormality is detected by the reset circuit consisting of the differential circuit 51 and the timer circuit 52 described earlier, and the latch circuit 15 is reset by the detection signal, and the output is output. When the signals OUT1 to OUT4 all go to L level, the flip-flop 27 of the control circuit 18 is reset and returned to its initial state.

As explained in detail above, according to the programmable controller input/output device according to the present invention, the controller main body and the required number of input/output devices are simply connected using two signal lines, a serial data line and a clock signal line. This allows bidirectional signal transmission of input data input and output data transmission, making the installation of transmission lines extremely simple and inexpensive. In addition, the input/output device does not need a circuit to judge addresses or a control circuit to handle complicated transmission control procedures; it simply detects when the clock signal is stopped and the clock signal line level is fixed above a certain level. All you need to do is provide a very simple control circuit consisting of a timer circuit, flip-flop, etc. for detection.
The configuration of the transmission control section in the input/output device is extremely simple and can be manufactured at low cost. In particular, in the device of the present invention, if an abnormality occurs such as a failure in the clock signal transmission system of the controller body or a break in the clock signal line, the latch circuit that provides the external output signal is reset to the initial state, and the control circuit is reset to the initial state. It will be reset to the state
The device to be controlled will not be thrown into confusion, and it will be safe and it will be easy to recover from an abnormality.

[Brief explanation of drawings]

Figure 1 shows a programmable system to which this invention is applied.
FIG. 2 is a block diagram showing the general structure of the controller system, FIG. 2 is a block diagram showing the specific structure of the input/output device, and FIG. 3 is a flowchart showing the outline of the input/output data transmission routine executed by the controller main body. 1... Controller main body, 2... Input/output device,
12...Serial data line, 13...Clock signal line, 14...Shift register, 15...Latch circuit, 16...Driver, 17...Receiver, 18
... Control circuit, 51 ... Differential circuit, 52 ... Timer circuit, SDL ... Left serial data input/output terminal,
SDR...Right serial data input/output terminal, CKL...Clock signal input terminal, SI...Series input terminal, Q4...
...Series output terminal, Q1-Q4...Parallel data output terminal, D1-D4...Parallel data input terminal, LD...
Parallel data read signal.

Claims (1)

[Claims] 1. Two serial data input terminals A and B, a clock signal input terminal, a shift register shifted by the clock signal applied to this clock signal input terminal, and a parallel output terminal connected to the shift register. a latch circuit, a driver that derives the output of the latch circuit in parallel as an external output signal, and a receiver that receives an external input signal in parallel and applies it to the parallel input terminal of the shift register;
Either the signal applied to the input terminal A is a serial input to the shift register and the serial output of the shift register is output to the input/output terminal B, or the signal applied to the input/output terminal B is input to the shift register. a switching circuit that switches the serial input of the shift register to a state where the serial output of the shift register is output to the input/output terminal A, and detects that the level of the signal applied to the clock signal input terminal is fixed for a certain period of time T1 or more. , the latch signal of the above latch circuit,
A control circuit that generates a parallel input read signal of the shift register and an inverted signal of the switching circuit detects that the level of the signal applied to the clock signal input terminal is fixed for a certain period of time that is sufficiently longer than the time T1. , a reset circuit for returning the latch circuit and the control circuit to an initial state.