JPH0312394B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to semiconductor memories.

The degree of integration of semiconductor memories has been improved along with advances in microfabrication technology. In particular, dynamic memory has the advantage of having a simple memory cell structure, allowing for high integration and low cost.
However, since the memory cells are dynamic circuits, the contents of the memory cells must be refreshed even during standby, making the external control system complicated. In order to improve this drawback, pseudo-static memories have been developed that incorporate internal refresh circuits and automatically perform refresh during standby. However, since the timer circuit used in the conventional internal refresh circuit divides the frequency of the oscillator output, the timer period varies greatly due to process variations (current capability, capacitance value, etc. of transistors). As a result, even if the timer period is the longest, the timer period must be shorter than the refresh period of the memory cell, and the drawback is that the timer period is usually shorter than necessary, resulting in increased power consumption. It was hot.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory that overcomes the above-mentioned drawbacks.

The present invention is characterized in that an external clock is used as the input or output of the timer circuit so that the timer cycle is not affected by process variations, thereby reducing power consumption.

This will be explained in detail below using the drawings.

A conventional example of a timer circuit is shown in FIG. A three-stage inverter oscillator section consisting of transistors Q ₁ to _{Q 6} and capacitors C ₃ and C ₄ , a charge pump section consisting of transistors Q ₇ to _{Q 9} and capacitors C ₁ and C ₂ , and a transistor Q ₁₀ and Q ₁₁ . It consists of an output inverter section. Transistors Q ₁ , Q ₃ , Q ₅ ,
Q ₇ and Q ₁₀ are P-channel transistors, and transistors Q ₂ , Q ₄ , Q ₆ , Q ₈ , Q ₉ , and Q ₁₁ are N-channel transistors. The oscillator period is the transistor
Process variations in the current capacity of Q ₁ to _{Q 6} and capacitance values of capacitances C ₃ and C ₄ , and process variations in the threshold voltages and capacitances C ₁ and C ₂ of transistors Q ₇ to _{Q 9} . It varies depending on the As a result, even when the timer period is the longest, it is necessary to make the timer period shorter than the refresh period of the memory cell, which usually results in a disadvantage that the timer period becomes shorter than necessary and power consumption increases.

An embodiment of the present invention is shown in FIG. Buffer section and transistors consisting of transistors Q ₁₂ and Q ₁₃
It consists of a charge pump section consisting of _Q7 to _Q9 and capacitors _{C1 and C2} , and an output inverter section consisting of transistors _Q10 and _Q11 . Transistor Q ₇ ,
Q ₁₀ and Q ₁₂ are P-channel transistors, and transistors Q ₈ , Q ₉ , Q ₁₁ , and Q ₁₃ are N-channel transistors. The buffer section is connected to an external clock (e.g.
WE), and compared to the case of FIG. 1, the process variation of the oscillator period is reduced. Another embodiment is shown in FIG. The timer circuit consists of an N-bit counter, the input of which is connected to an external clock. In this case, the timer period is N times the period of the external clock and is not affected by process variations. Another embodiment is shown in FIG. It consists only of an output inverter section consisting of transistors Q ₁₀ and Q ₁₁ , and the timer period is the same as that of the external clock, so it is not affected by process variations like the previous embodiment.

Thus, in the present invention, the timer period is not or only slightly affected by process variations. Therefore, the timer period can always be set close to the refresh period of the memory cell, and power consumption can be reduced.

I explained the case of CMOS circuit above, but
It is also possible to configure it with only N-channel or P-channel transistors.

[Brief explanation of the drawing]

Figure 1 shows a conventional example of a timer circuit, Figure 2 shows a conventional example of a timer circuit.
1, 3 and 4 are diagrams each showing an embodiment of a timer circuit according to the present invention. Q ₁ , Q ₃ , Q ₅ , Q ₇ , Q ₁₀ , Q ₁₂ ... P channel transistor, Q ₂ , Q ₄ , Q ₆ , Q ₈ , Q ₉ , Q ₁₁ , Q ₁₃ ...
...N-channel transistor, C ₁ , C ₂ , C ₃ , C ₄ ...
...Capacity, 1...N-bit counter, _P ...Internal clock signal, WE...External clock signal, _φ1 ...
...Timer output signal.

Claims (1)

[Claims] 1. In a pseudo-static memory that includes a timer circuit, an internal address counter, and an internal refresh control clock generation circuit, the timer circuit is configured with a frequency divider circuit or an inverter circuit that receives an external clock as input, and the timer period is A pseudo-static memory characterized in that the clock is determined in proportion to the cycle of the external clock.