JPH0312500B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error control method in a data transmission line.

In data transmission, in order to efficiently transmit highly reliable information, it is necessary to protect the information from errors caused by interference on the communication path, such as line noise. For this reason, data communication systems always perform some form of error control. Error control methods include automatic repeat request (ARQ) and unidirectional error correction (FEC).

The ARQ method is currently widely used. This is because it is easy to implement and
This is because it has overwhelmingly superior reliability compared to FEC, etc.

However, the ARQ method has the disadvantage that if even one bit error occurs in one frame, the entire frame must be retransmitted, and is relatively slow. To compensate for this drawback, a hybrid system has been proposed that is located between the ARQ system and the FEC system, in which all errors that can be corrected are corrected on the receiving side, and only errors that cannot be corrected are retransmitted by the sending side. There is. however,
The error detection ability of the hybrid system is inferior to that of codes dedicated to detection, and furthermore, the addition of an error correction function has the disadvantage of complicating the hardware of the device.

In addition, the PSK method, which is currently widely used,
In digital modulation and demodulation methods such as QAM, input data information is differentially encoded to ensure long-term stability of the demodulator and a high-quality phase correction loop. When differential encoding is performed, an error in one element spreads to an error in two elements, so even if Gray encoding is applied, at least 2-bit errors will occur. Therefore, an error in one element within one frame results in a 2-bit error, and an error in two elements results in a 4-bit error.
When an FEC method or a hybrid method is applied, it is necessary to perform encoding with excellent error correction ability, and the size of the decoder becomes extremely complex.

The present invention solves the above-mentioned drawbacks of the prior art, and adds a simple peripheral circuit to the demodulator used in the conventional ARQ method, thereby adding error correction capability in addition to the conventional error detection capability. The purpose of this study is to provide an error control method that allows

In order to achieve this objective, the error control method of the present invention is such that on the transmitting side, the information data to be transmitted is block encoded using an error detection code, then modulated and sent out to the transmission path, and on the receiving side, the received signal is demodulated. An error control method using automatic retransmission requests that controls errors by obtaining reception judgment data, detecting errors for each block of the reception judgment data, and requesting the transmitter to retransmit blocks in which errors are detected. When demodulating the received signal, the reception status of each bit of the received signal is stored for one block, and for the block in which the error was detected, the reception status of each bit corresponding to the block is stored. Based on the reception status information, the bits that are most likely to be erroneous in the block, the bits that are the second most likely to be erroneous, and the bits that are the third most likely to be erroneous are identified. Find the positions of several bits that are likely to be present, and from the combination of these found several bit positions,
Error, 2 errors, ... n Estimate error patterns for error correction, correct the received signal sequence based on the estimated error pattern, and create corrected received signal sequences of the same number as the estimated error patterns. Then, these corrected received signal sequences are input into the error detection decoder again, and the presence or absence of errors in each corrected received signal sequence is checked. If no error is detected, the error is detected. The error-corrected received signal sequence is output as an error-corrected signal sequence, and if errors are detected in all sequences,
The feature is that the sending side is requested to retransmit the corresponding block.

A detailed explanation will be given below with reference to the drawings. Figure 1 shows
A conceptual diagram of the conventional ARQ method is shown. The present invention relates to 5 demodulators and 6 error detectors. Here, we will briefly explain the conventional ARQ method. 1 is the information source. Encoder No. 2 performs block coding including (n-k) check bits, which can determine k-bit information from No. 1 using a generating polynomial. If the transmission code string is F(x), then F
(x) is composed of k bits of information and (n-k) bits of check bits, and is expressed as the following equation.

F (x) ⁼ M (x) , G(x) are generator polynomials that create check bits. Q(x) is M(x)・x ^nk is G(x)
R(x) is the quotient when divided by , and R(x) indicates the remainder at that time, that is, the check bit. Also, M(x), R(x)
is input data information a ₀ ~ _{a k-1} , test bit b ₀ ~
By using b _ok-1 , it can be expressed by the following equation.

M(x)=a ₀ +a ₁ x+a ₂ x ² +... +a _k-1 x ^k-1 ...(2) R(x)=b ₀ +b ₁ x+b ₂ x ² +... +b _ok-1 x ^nk-1 ...(3) Therefore, check bits R are added to the information code string M(x) so that the transmission code string F(x) is divisible by G(x).
This means that (x) is added. Now, if an error occurs due to noise on the transmission path of 4, the error code string E(x) at that time is expressed by the following equation.

E(x)=e ₀ +e ₁ x+e ₂ x ² +... +e _o-1 x ^n-1 ...(4) However, e _i is 1 if the i-th bit is incorrect; If not, it is 0. Therefore, by using equation (4), the received code string F'(x) can be expressed by the following equation.

F'(x)=F(x)+F(x)...(5) Next, the received code sequence F'(x) is checked by the error detector 6 to determine whether it is divisible by the generator polynomial G(x). The received block is checked for errors.
If the remainder is 0, it is understood that there is no error in that frame, and the frame is output as is to the decoder 7. If the remainder is not 0, there is an error in the frame, and a retransmission request is sent to the transmitting side through the return path 602. Through such operations, highly reliable data transmission can be achieved. However, in the method described above, if one frame consists of 1000 bits, for example, even if there is a 1-bit error, it is necessary to retransmit 1 frame, or 1000 bits. .

The present invention corrects errors of up to 3 to 4 bits by utilizing the correlation between error elements and the received signal state at that time, as described below.
This is to compensate for the above drawbacks. Furthermore, it is relatively easy to implement the present invention into an apparatus.

In the No. 5 demodulator, the received signal is judged by a hard threshold that only determines whether it is 1 or 0 based on the threshold.
This is a hard decision, and does not take into account the analog information that the received signal has before making the decision.

However, in cases where the transmission path can be modeled using white noise, such as a satellite line, there is a very strong correlation between errors and the analog information at that time. The analog information here refers to the distance from the received signal level to the nearest determination threshold. Therefore, the shorter the distance, the greater the probability that the received signal is erroneous, and conversely, the longer the distance, the greater the probability that the received signal is correctly received. Hereinafter, the distance representing analog information will be referred to as analog weight.

FIG. 2 shows the result of calculating the relationship between the error bit M and the analog weight at that time for a binary case. Here, the vertical axis indicates the probability of correct error correction, and the horizontal axis M indicates the number of bits for error correction within one block. In other words, in Fig. 2, it is assumed that an n-bit received signal is hard-determined, and m-bit errors occur in it, and then the analog weight of the m-bit error bits is determined from the smaller of the n analog weights. This is the result of calculating the probability for m3, M10, and Mm when they are all included in the Mth number. As you can see from the figure,
It can be seen that where the S/N (signal power to noise power ratio) is high to some extent, there is a very large correlation between the error bit and the analog weight at that time.

In the present invention, error correction is performed by using both the analog weight and the error detection ability of the code. In other words, the hard-decision frame-by-frame data is checked for the presence or absence of errors within the frame using an error detector, and if there are no errors, it is output as demodulated data, and the error detector detects the presence of an error. For example, perform the following operations to correct errors.

By setting e _i of the order corresponding to the smallest bit, second smallest bit, third smallest bit, etc. among the n-bit analog weights to 1, an error pattern as shown in equation (4) is created. For example, when considering the two smallest analog weights and the corresponding orders are m ₁ and m ₂ , the estimated error pattern is expressed by the following equation.

E ₁ (x) = x ^m1 E ₂ (x) = x ^m2 E ₃ (x) = x ^m1 + x ^m2 ...(6) Also, the number of analog weights to be considered is m ₁ , m ₂ , m ₃
The estimated error pattern in the case where only errors of up to 2 bits are corrected is expressed as follows.

E ₁ (x)=x ^m1 E ₂ (x)=x ^m2 E ₃ (x)=x ^m3 E ₄ (x)=x ^m1 +x ^m2 E ₅ (x)=x ^m1 +x ^m3 E ₆ (x)= x ^m2 + x ^m3 ...(7) Next, hard decision demodulated data expressed by equation (5)
F″(x) obtained by adding the estimated error patterns expressed as equations (6), (7), etc. to F′(x) is expressed by the following equation.

F''(x)=F(x)+E(x)+E _i (x)...(8) (i=1~l) Here, if the error pattern E that occurs on the transmission path is
Assuming that the same thing as (x) exists in E _i (x),
F″(x) becomes the transmission data string of F(x) from the relationship of the following equation, and error correction has been completed.

E (x) + E _i (x) = 0 ... (9) F'' (x) = F (x) ... (10) If E _i (x) does not have the same thing as E (x) In this case, it can be seen that {E(x) + E _i (x)} is not divisible by G(x) and a remainder is generated, making it impossible to perform error correction.In this case, the conventional ARQ method and Similarly, a retransmission request is made to the sending side.

Here, the degree of deterioration of the error detection ability due to the error correction of the present invention will be described.

For example, when a Hamming code with a minimum distance of 4 obtained by a generator polynomial of degree (nk) is used as an error detection code, the rate at which an error detector does not detect an error is 1/2 ^nk-1 or less. Therefore, the error detection ability when error correction is performed using the method described above is expressed by the following equation.

P=(l+1)/2 ^nk-1 (11) where l indicates the number of estimated error patterns. Therefore, when l is small, error correction is possible with almost no deterioration in error detection ability.

FIG. 3 shows the calculation results (curve b) of the block error rate according to the present invention. Calculation example is n=1000, n-
The case where k=16 and l=6 will be shown. The figure also shows the conventional block error rate (curve a). From the figure, when compared at S/N=10 dB, it can be seen that the method of the present invention improves the block error rate by about 3000 times as compared to the conventional method.

Additionally, this method can be applied to Selective Repeat ARQ
method, SETRAN ARQ method, Go-Back-N
Figure 4 shows a comparison of throughput characteristics (transmission efficiency) when applied to the ARQ method.
In Figure 4, solid line a is the conventional Selective Repeat ARQ.
The characteristics of the system, the black dots are the characteristics when the present invention is applied to this ARQ method, and the dotted line b is the conventional SETRAN
The characteristics of the ARQ method, the × points are the characteristics when the present invention is applied to this ARQ method, and the dashed line c is the conventional Go
−Back−N The characteristics of the ARQ method, the white point is this
These are the characteristics when the present invention is applied to the ARQ method.
In addition, in each graph of Fig. 4, the number of response delay blocks N
(The number of blocks to be retransmitted going back to when an error occurred) is N=128. From FIG. 4, it can be seen that by applying the present invention, the throughput characteristics of each ARQ method are significantly improved.

Next, an embodiment according to the present invention will be described.
FIG. 5 shows a schematic diagram of the receiving section of the present invention. In the demodulator No. 51, the received signal is converted into
At the same time as making a hard decision, an operation is performed to extract analog weights for each element. The analog weight storage section 52 stores the number of analog weights in descending order and the reception determination result at that time. The error pattern estimator 53 estimates an error bit pattern from the reception determination result of the element with a small analog weight obtained in 52. The error bit patterns estimated here are E ₁ (x), E ₂ (x),
In equation (7), only one element is required, such as E ₁ (x), E ₂ (x), E ₃ (x), etc. The remainder calculation unit 54 divides the polynomial of the error bit pattern obtained in 53 by the generator polynomial G(x) to obtain the remainder. The remainder pattern synthesizer in 55 uses the remainder obtained in 54 to calculate E ₃ (x) in equation (6) and E ₄ in equation (7).
(x), E ₅ (x), and E ₆ (x) are divided by G(x), and the remainders are synthesized.
This is synthesized using the following relationship.

E ₃ (x) = x ^m1 + x ^m2 ... (12) E ₃ (x) / G (x) = Q _n1 (x) + Q _n2 (x) +R _n1 (x) + R _n2 (x) / G (x )...(13) However, Q _n1 (x) and Q _n2 (x) are the quotients when x ^m1 and x ^m2 are respectively divided by G (x), and R _n1 (x) and R _n2
(x) is the remainder at that time. Therefore, the remainder when E ₃ (x) is divided by G (x) is independently E ₁ (x) and E ₂
It is the sum of the remainders when (x) is divided by G(x). From this, in the 55 remainder pattern synthesizer,
This means that the remainders for all error patterns corresponding to equation (6) have been found.

The data storage section 56 stores hard decision data for one frame. The remainder calculation unit No. 57 calculates the remainder when one frame's worth of hard-decision data code string is divided by G(x). With 59 determiners, 55
This is a circuit that finds a remainder pattern that becomes 0 from the sum of the remainder obtained from A retransmission request is sent to the sending side through 602. Further, when there is a remainder pattern that becomes 0, the SW 61 is set to the a side, and information about which pattern is output from the remainder pattern synthesizer 55 is output. The estimated error pattern synthesizer No. 62 combines all the error patterns corresponding to equations (6) and (7), and selects one of them from the information No. 59. This makes it possible to select the same error pattern E(x) that is thought to have occurred on the transmission path.

Next, the operation of equation (8) is performed by the adder 63, and the hard decision data is error-corrected based on the relationship of equation (9), and is sent to the decoder through 601 as demodulated data.

Since the present invention observes analog weights on an element-by-element basis, even if differential coding is performed in the modulator, the error pattern estimator of 53
The error bit pattern across the elements can be estimated.

For example, in the case of synchronous detection differential 4-phase PSK method,
Assuming that whenever a certain element makes an error, it always makes an error in the adjacent judgment area (this is how errors occur in places where the S/N is high), then the error bit pattern across the two elements is shown below. There are only 4 ways.

Similarly, in the case of synchronous detection differential 8-phase PSK, there are only 9 ways shown below.

Therefore, by looking at the hard decision results and the state of the analog weights, the error bit pattern created in step 53 can be easily created.

As described in detail above, the present invention
By simply adding a simple circuit to the ARQ demodulator and error detector, it is now possible to use information before judgment on the received signal, such as the analog weight of the error-detected frame, instead of just detecting errors. Since this is an error control method that can also perform error correction, a communication method with high reliability and transmission capability can be obtained with a simple circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an outline of the conventional ARQ method, FIG. 2 is a diagram showing the result of calculating the relationship between the error bit M and the analog weight at that time for a binary case, and FIG. FIG. 4 is a diagram showing block error rate characteristics for /N.
FIG. 5 is a diagram showing throughput characteristics when applied to the ARQ method, and is a schematic diagram showing an embodiment of the demodulator and error detector according to the present invention. 51... Demodulator, 52... Analog weight storage unit, 53... Error pattern estimator.

Claims (1)

[Claims] 1. On the transmitting side, the information data to be transmitted is block encoded with an error detection code, then modulated and sent to the transmission path, and on the receiving side, the received signal is demodulated to obtain reception judgment data, Demodulating the received signal in an error control method using an automatic retransmission request, in which errors are detected for each block of the reception judgment data, and errors are controlled by requesting the transmitter to retransmit blocks in which errors are detected. At this time, the reception status of each bit of the received signal is stored for one block, and for the block in which the error has been detected, the reception status information stored for each bit corresponding to the block is used to determine the reception status within the block. The bits that are most likely to be wrong in the block, the second most likely to be wrong, the third most likely to be wrong, etc. The positions of several bits are determined, and from the combination of the positions of these several bits, 1 error, 2 errors are detected.
Error, ... n Estimate an error pattern for error correction,
The received signal sequence is corrected based on the estimated error pattern, the same number of corrected received signal sequences as the estimated error patterns are created, and then these corrected received signal sequences are sent to the error detection decoder again. and checks whether there are any errors in each corrected received signal sequence, and if no errors are detected,
The corrected received signal sequence in which no error was detected is output as an error-corrected signal sequence, and when errors are detected in all sequences, the transmission side is requested to retransmit the corresponding block. Error control method.