JPH0312832B2 - - Google Patents
Info
- Publication number
- JPH0312832B2 JPH0312832B2 JP8518784A JP8518784A JPH0312832B2 JP H0312832 B2 JPH0312832 B2 JP H0312832B2 JP 8518784 A JP8518784 A JP 8518784A JP 8518784 A JP8518784 A JP 8518784A JP H0312832 B2 JPH0312832 B2 JP H0312832B2
- Authority
- JP
- Japan
- Prior art keywords
- charging
- voltage
- signal
- circuit
- detection output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 20
- 238000007599 discharging Methods 0.000 claims description 16
- 239000003990 capacitor Substances 0.000 description 13
- 230000007423 decrease Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Television Receiver Circuits (AREA)
Description
【発明の詳細な説明】
本発明はテレビジヨン受像機のVIFにおける
AGC回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides
This concerns the AGC circuit.
(従来例の構成とその問題点)
従来のVIF・AGC回路とその周辺ブロツク図
を第1図に示す。チユーナからのIF信号が1よ
り入力され、2のIFアンプで増幅される。この
アンプはゲインをコントロールでき、そのコント
ロールは端子24から電圧を加えることにより行
なう。一定出力まで増幅された信号3は検波器4
によつてビデオ信号として25に検波出力され
る。更にアンプ5で増幅され、その出力はVBと
して次の差動アンプに加わる。トランジスタ6,
11で構成される差動アンプの一端は電圧VCで
固定され、他端は信号VBの同期信号先端部を検
出する。それは検波出力25が2Vp-pになる時に
その増幅された信号VBの同期信号先端電圧がVC
となりそれに合わせている。ここで同期信号の先
端がVCよりも下がるとトランジスタ11のコレ
クタに電流が流れコンデンサ18から電荷を放電
させる。又VB同期信号部以外の電位はVCよりも
高いのでトランジスタ6に電流が流れ抵抗7、ダ
イオード8の電位降下により抵抗9とトランジス
タ10はカレントミラーとして働き、その電流は
コンデンサ18に流れ充電される。この変化を詳
しく記したのが第2図でコンデンサの端子電圧
VAは第2図bに示すように充放電により上下す
る。特に第2図aの送信ビデオ信号の等価パルス
期間及び垂直同期期間は同期信号のパルス幅と本
数が異なりコンデンサ18への充放電の様子も変
化する。すなわち信号期間は同期信号の間隔が長
く充放電はこの期間をもとに設計され一定を保つ
が等価パルスが始まると同期信号の間隔がせまく
なり充電期間が短かくなる。するとコンデンサ1
8の電圧VAは第2図bのごとく徐々に下がる。
更に垂直同期パルス期間となると充放電期間が逆
転しVBは特に下がる。しかしどんどん下がるの
ではなく途中で一定となる。それはこのVB電圧
をトランジスタ23、及び抵抗22、ダイオード
21、ツエナーダイオード20を介して端子24
からIFアンプへ導きゲインコントロールを行な
う為である。1からIF入力が小さくなると検波
出力25も小さくなりトランジスタ6へ加わる信
号の同期信号先端もVCより高くなる。するとコ
ンデンサ18から放電されなくなり電圧VAの電
位は高くなり、この電圧VAはIFアンプのゲイン
を増幅し検波器4の検波出力25も増し一定を保
つ。逆にIF入力が大きいとAGC電圧が下がりIF
アンプのゲインを下げる。このようにAGC回路
が動作し、検波出力25を一定に保つ。しかし、
前述したようにこの方式では波形の一部(垂直同
期パルス前後)はAGC電圧が下がる為、この電
圧でIFアンプをコントロールすると検波出力2
5は第2図cのごとく(わかりやすくする為負極
生で図示した)垂直同期期間が下がり忠実な波形
再生をしない。その結果、垂直同期が不安定にな
つたり、垂直同期パルスの最初のステツプパルス
を用いたゴースト検出、又、AGC電圧の変動に
よるIFアンプの変化がSIFに出力に位相変化とな
つて音声S/Nが劣化する。この問題を改善する
方法として第1図の抵抗19を小さくすれば良く
なるが弱電界時の検波出力25が劣化してしま
う。(Conventional configuration and its problems) Figure 1 shows a conventional VIF/AGC circuit and its peripheral block diagram. The IF signal from the tuner is input from 1 and is amplified by IF amplifier 2. The gain of this amplifier can be controlled by applying a voltage from the terminal 24. The signal 3 amplified to a constant output is sent to the detector 4
The signal is detected and output to 25 as a video signal. It is further amplified by amplifier 5, and its output is applied to the next differential amplifier as VB . transistor 6,
One end of the differential amplifier constituted by 11 is fixed at the voltage V C , and the other end detects the synchronization signal tip of the signal V B. That is, when the detection output 25 becomes 2V pp , the synchronous signal tip voltage of the amplified signal V B is V C
It's in line with that. Here, when the tip of the synchronizing signal falls below V C , a current flows to the collector of the transistor 11 and discharges the charge from the capacitor 18 . Also, since the potential other than the V B synchronization signal section is higher than V C , current flows through transistor 6 and due to the potential drop across resistor 7 and diode 8, resistor 9 and transistor 10 act as a current mirror, and the current flows to capacitor 18 and charges it. be done. Figure 2 shows this change in detail, showing the terminal voltage of the capacitor.
V A rises and falls due to charging and discharging, as shown in Figure 2b. In particular, in the equivalent pulse period and the vertical synchronization period of the transmitted video signal shown in FIG. That is, the signal period has a long interval between synchronizing signals, and charging and discharging are designed based on this period and remain constant, but when the equivalent pulse starts, the interval between synchronizing signals becomes narrower and the charging period becomes shorter. Then capacitor 1
8 voltage V A gradually decreases as shown in Figure 2b.
Furthermore, during the vertical synchronization pulse period, the charging/discharging period is reversed and V B particularly drops. However, it does not go down gradually, but becomes constant in the middle. It transfers this V B voltage to terminal 24 through transistor 23, resistor 22, diode 21, and Zener diode 20.
This is to guide the signal from the signal to the IF amplifier for gain control. 1, as the IF input becomes smaller, the detection output 25 also becomes smaller, and the tip of the synchronization signal applied to the transistor 6 also becomes higher than V C . Then, the capacitor 18 is no longer discharged and the potential of the voltage V A becomes high, and this voltage V A amplifies the gain of the IF amplifier and the detection output 25 of the detector 4 also increases and remains constant. Conversely, if the IF input is large, the AGC voltage will decrease and the IF input will decrease.
Lower the amplifier gain. The AGC circuit operates in this manner to keep the detection output 25 constant. but,
As mentioned above, in this method, the AGC voltage drops in a part of the waveform (before and after the vertical synchronization pulse), so if you control the IF amplifier with this voltage, the detection output 2
5, as shown in FIG. 2c (illustrated with negative polarity for ease of understanding), the vertical synchronization period is reduced and faithful waveform reproduction is not possible. As a result, vertical synchronization becomes unstable, ghost detection using the first step pulse of the vertical synchronization pulse, and changes in the IF amplifier due to AGC voltage fluctuations result in phase changes in the SIF output, resulting in audio S/S/ N deteriorates. One way to improve this problem is to make the resistor 19 in FIG. 1 smaller, but the detection output 25 at the time of a weak electric field deteriorates.
(発明の目的)
本発明は上記の欠点を除去し、忠実な検波波形
を保ち、弱電界感度を上げるAGC回路を提供す
るものである。(Objective of the Invention) The present invention provides an AGC circuit that eliminates the above-mentioned drawbacks, maintains a faithful detected waveform, and increases weak electric field sensitivity.
(発明の構成)
本発明は、VIFブロツク中の尖頭値形AGC回
路であつて、VIF信号を映像検波して得られたテ
レビジヨン信号の同期信号の先端を第1の基準電
圧と比較する第1のコンパレータと、前記第1の
コンパレータからの前記同期信号の先端と第1の
基準電圧の電位差に比例した第1の検出出力電流
が充電あるいは放電される充放電回路と、前記充
放電回路の充電電位と第2の基準電圧とを比較す
る第2のコンパレータと、前記第2のコンパレー
タからの前記充放電回路の充電電位の第2の基準
電圧との電位差に比例した第2の検出出力電流
を、前記充放電回路へ充電される前記第1の検出
出力電流に加算する電流加算手段とを備え、前記
充放電回路の充電電圧でVIFブロツクのIFアンプ
のゲインをコントロールするようにしたものであ
る。(Structure of the Invention) The present invention is a peak value type AGC circuit in a VIF block, which compares the leading edge of a synchronization signal of a television signal obtained by video detection of a VIF signal with a first reference voltage. a first comparator; a charging/discharging circuit in which a first detection output current proportional to the potential difference between the tip of the synchronizing signal from the first comparator and a first reference voltage is charged or discharged; and the charging/discharging circuit. a second comparator that compares the charging potential of the charging and discharging circuit with a second reference voltage, and a second detection output that is proportional to the potential difference between the charging potential of the charging and discharging circuit and the second reference voltage from the second comparator. and current adding means for adding a current to the first detection output current that is charged to the charging/discharging circuit, and the gain of the IF amplifier of the VIF block is controlled by the charging voltage of the charging/discharging circuit. It is.
(実施例の説明)
以下本発明の一実施例について第3図を参照し
て説明する。(Description of Embodiment) An embodiment of the present invention will be described below with reference to FIG. 3.
チユーナからのIF信号入力1はIFアンプ2と
検波器4を通し映像検波出力25として現われ
る。更にそれをアンプ5で増幅し第1のコンパレ
ータを形成するトランジスタ6,11からなる作
動アンプのトランジスタ6側ベースへ入力する。
映像信号VBの同期信号先端がトランジスタ11
のベースに加わる電圧VCより下がると(検波出
力25が予め定めた振幅、例えば2Vp-pを越えた
時)トランジスタ11は導通し、トランジスタ6
はカツトオフとなりダイオード8、抵抗7,9そ
してトランジスタ10も電流は流れず、トランジ
スタ11が導通するとその電流はコンデンサ18
からの放電電流として行なわれコンデンサ18の
端子電圧VAは降下する。しかし、水平同期信号
は幅が4μsecしかなく、すぐ放電は停止する。次
に映像信号VBは映像期間にはいるがその電圧は
VCよりも高いので今度はトランジスタ6が導通
し電流i6が流れ、抵抗7,9に電流が流れる(抵
抗9(抵抗値R2)に流れる電流i10は抵抗7(抵
抗値R1)の抵抗比で決まるi10≒i6×R1/R2)とトラ
ンジスタ10を通しコンデンサ18に充電電流と
なり電圧VAは上昇する。しかし充電電流はその
一部が充電合流抵抗19にも分流される。この映
像期間は長く徐々に充電電圧が上昇する。次の水
平同期信号がくれば又放電となり、VA電圧は一
定を保つが、等価パルス期間及び垂直同期パルス
期間は上記の充放電期間が異なりVA電圧は降下
し、段差を作り、弊害をもたらす。ここで、コン
デンサ18の充電分流抵抗19を小さくしてゆく
と充電分流が増す為コンデンサ18への充電電流
が減少する。すると水平同期期間のVAレベルが
下がり垂直同期期間との段差はなくなり当初の弊
害は減少する。ところが電波の入力が減少し、
AGC電圧VCが上昇し、IFアンプ2のゲインを一
杯近くにすると、検波出力25にノイズが増し、
水平同期信号部の前後がノイズにより恰も水平同
期信号パルス幅が広くなつた形となる。すると今
までコンデンサ18への充放電がバランスをと
り、IFのゲインをコントロールしていたのが上
記の為放電電流が増す。すなわちAGC電圧VAが
下がりIFアンプ2のゲインも最大にならない。
本発明はこの弱電界時、電圧VAが上昇しその電
圧VAが抵抗17と28の交点で決まる電圧VDを
起すことをトランジスタ30,32の第2のコン
パレータで検出し、トランジスタ32を導通さ
せ、その電流でトランジスタ29も導通させると
抵抗27(抵抗値R3とする)は抵抗9とは並列
接続となり充電電流
i10≒i6×R1/R2×R3/R2+R3となり増加する。 An IF signal input 1 from the tuner passes through an IF amplifier 2 and a detector 4 and appears as a video detection output 25. Further, it is amplified by an amplifier 5 and inputted to the base of the transistor 6 side of an operational amplifier consisting of transistors 6 and 11 forming a first comparator.
The tip of the synchronization signal of the video signal V B is the transistor 11
When the voltage applied to the base of the transistor 6 falls below V C (when the detected output 25 exceeds a predetermined amplitude, for example, 2V pp ), the transistor 11 becomes conductive, and the transistor 6
is cut off, and no current flows through diode 8, resistors 7 and 9, and transistor 10. When transistor 11 becomes conductive, the current flows through capacitor 18.
This occurs as a discharge current from the capacitor 18, and the terminal voltage V A of the capacitor 18 drops. However, the width of the horizontal synchronization signal is only 4 μsec, and the discharge immediately stops. Next, the video signal V B enters the video period, but its voltage is
Since it is higher than V C , transistor 6 conducts and current i 6 flows, and current flows through resistors 7 and 9 (current i 10 flowing through resistor 9 (resistance value R 2 ) is equal to resistor 7 (resistance value R 1 ). i 10 ≒ i 6 ×R 1 / R2 ), which is determined by the resistance ratio of i 10 ≒ i 6 ×R 1 /R2), and a charging current flows into the capacitor 18 through the transistor 10, and the voltage V A increases. However, part of the charging current is also shunted to the charging merging resistor 19. This video period is long and the charging voltage gradually increases. When the next horizontal synchronization signal comes, the discharge occurs again, and the V A voltage remains constant, but the above charging and discharging periods are different during the equivalent pulse period and the vertical synchronization pulse period, and the V A voltage drops, creating a step and causing harmful effects. bring. Here, as the charging shunt resistor 19 of the capacitor 18 is made smaller, the charging shunt increases, so the charging current to the capacitor 18 decreases. Then, the V A level during the horizontal synchronization period decreases, and the difference between it and the vertical synchronization period disappears, and the initial adverse effects are reduced. However, the input of radio waves decreased,
When the AGC voltage V C rises and the gain of IF amplifier 2 is set close to full, noise increases in the detection output 25.
The horizontal synchronizing signal pulse width appears to be wide due to noise before and after the horizontal synchronizing signal section. Then, the discharge current increases because the charging and discharging to the capacitor 18 has been balanced and the IF gain has been controlled as described above. That is, the AGC voltage V A decreases and the gain of the IF amplifier 2 does not reach its maximum.
The present invention uses the second comparators of the transistors 30 and 32 to detect that the voltage V A rises during this weak electric field and that the voltage V A generates the voltage V D determined by the intersection of the resistors 17 and 28. When the current is made conductive and the transistor 29 is also made conductive, the resistor 27 (resistance value R 3 ) is connected in parallel with the resistor 9 and the charging current i 10 ≒i 6 ×R 1 /R 2 ×R 3 /R 2 +R 3 and increases.
放電電流は変わらないのでAGC電圧VAは上昇
し、十分IFアンプを最大ゲインにもつてゆくこ
とができる。Since the discharge current remains unchanged, the AGC voltage V A rises, enough to bring the IF amplifier to its maximum gain.
(発明の効果)
以上のように本発明は映像信号の忠実な再生を
し、垂直同期の不安定さを減少し、垂直同期パル
スの最初のステツプパルスを用いたゴースト検出
の忠実性及びAGC電圧変動によるIFアンプの変
化がSIF出力に位相変化となつて音声S/N劣化
となることを防ぎ、第2のコンパレータからの充
放電回路の充電電位と第2の基準電圧との電位差
に比例した第2の検出出力電流を、AGC制御用
の充放電回路へ充電される第1の検出出力電流に
加算するようにしたので、AGC電圧をよく平均
化することができる。(Effects of the Invention) As described above, the present invention faithfully reproduces a video signal, reduces the instability of vertical synchronization, and improves the fidelity of ghost detection using the first step pulse of the vertical synchronization pulse and the AGC voltage. This prevents changes in the IF amplifier due to fluctuations from causing phase changes in the SIF output and deterioration of audio S/N. Since the second detection output current is added to the first detection output current that is charged to the charge/discharge circuit for AGC control, the AGC voltage can be well averaged.
第1図は従来例におけるAGC装置の回路図、
第2図は第1図の動作説明のための波形図、第3
図は本発明の一実施例におけるAGC装置の回路
図である。
2……IFアンプ、4……検波器、5……アン
プ、6,10,11,29,30,32……トラ
ンジスタ、7,9,17,27,28……抵抗、
18……コンデンサ、19……充電分流抵抗。
Figure 1 is a circuit diagram of a conventional AGC device.
Figure 2 is a waveform diagram for explaining the operation of Figure 1;
The figure is a circuit diagram of an AGC device in an embodiment of the present invention. 2...IF amplifier, 4...Detector, 5...Amplifier, 6, 10, 11, 29, 30, 32...Transistor, 7, 9, 17, 27, 28...Resistor,
18...Capacitor, 19...Charging shunt resistor.
Claims (1)
て、 VIF信号を映像検波して得られたテレビジヨン
信号の同期信号の先端を第1の基準電圧と比較す
る第1のコンパレータと、 前記第1のコンパレータからの前記同期信号の
先端と第1の基準電圧の電位差に比例した第1の
検出出力電流が充電あるいは放電される充放電回
路と、 前記充放電回路の充電電位と第2の基準電圧と
を比較する第2のコンパレータと、 前記第2のコンパレータからの前記充放電回路
の充電電位と第2の基準電圧との電位差に比例し
た第2の検出出力電流を、前記充放電回路へ充電
される前記第1の検出出力電流に加算する電流加
算手段とを備え、 前記充放電回路の充電電圧でVIFブロツクのIF
アンプのゲインをコントロールするように構成し
たAGC回路。[Claims] 1. A peak value type AGC circuit in the VIF block, which comprises a first circuit that compares the leading edge of the synchronization signal of the television signal obtained by video detection of the VIF signal with a first reference voltage. a charging/discharging circuit in which a first detection output current proportional to the potential difference between the tip of the synchronizing signal from the first comparator and a first reference voltage is charged or discharged; and charging/discharging circuit. a second comparator that compares the potential with a second reference voltage; and a second detection output current proportional to the potential difference between the charging potential of the charging/discharging circuit and the second reference voltage from the second comparator. , current adding means for adding to the first detection output current charged to the charging/discharging circuit, the IF of the VIF block is controlled by the charging voltage of the charging/discharging circuit.
AGC circuit configured to control amplifier gain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59085187A JPS60230775A (en) | 1984-04-28 | 1984-04-28 | AGC circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59085187A JPS60230775A (en) | 1984-04-28 | 1984-04-28 | AGC circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60230775A JPS60230775A (en) | 1985-11-16 |
| JPH0312832B2 true JPH0312832B2 (en) | 1991-02-21 |
Family
ID=13851651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59085187A Granted JPS60230775A (en) | 1984-04-28 | 1984-04-28 | AGC circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60230775A (en) |
-
1984
- 1984-04-28 JP JP59085187A patent/JPS60230775A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60230775A (en) | 1985-11-16 |
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