JPH0315337B2 - - Google Patents
Info
- Publication number
- JPH0315337B2 JPH0315337B2 JP59001977A JP197784A JPH0315337B2 JP H0315337 B2 JPH0315337 B2 JP H0315337B2 JP 59001977 A JP59001977 A JP 59001977A JP 197784 A JP197784 A JP 197784A JP H0315337 B2 JPH0315337 B2 JP H0315337B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- coating material
- substrate
- coating
- composition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/144—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations comprising foils
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
- H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Paints Or Removers (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
〔発明の利用分野〕
本発明は、素子面に形成されてなるはんだ電極
端子と基板端子とをはんだ接続した樹脂コーテイ
ング実装において、特に、チツプと電極端子基板
間の50〜200μmの間〓に樹脂を完全に満たすこと
により、耐湿信頼性の高い実装品を提供すること
にある。
〔発明の背景〕
従来、ガラス基板を用いた表示素子のSiチツプ
の実装において、第１図に示すように、ガラス基
板１上の端子にSiチツプ２をCCB４
（Contorolled Collapse Bonding）接合した後、
その周囲を低膨張エポキシ系樹脂（石英粉混入）
でコーテイングし、耐熱疲労性を向上することが
知られている。しかし、上記実装チツプをコート
する際に、通常の方法でコーテイングすると、Si
チツプとガラス基板間の間〓を上記樹脂で満すこ
とができず、ガラス基板に配線した回路に、上記
樹脂がコーテイングされない部分が生ずる。また
極端な場合は、第１図に示したように、Siチツプ
２をコーテイング材３でコーテイングし、コーテ
イング材を硬化するため加熱すると、コーテイン
グ材の粘度低下と共に、Siチツプとガラス基板間
の空〓の空気が体積膨張し、この空気の一部がコ
ーテイング膜を破つて外に飛散する。この結果、
空気の通路６が他の部分に比べ弱体化すると共
に、空気が飛散した部分に凹形の痕５が生ずる。
以上のようなコーテイングの場合は、耐湿テス
ト（70℃，95〜100％RH）を行うと、150〜200h
で回路間にリーク電流が発生し、誤動作するとい
う問題がある。この原因は、エポキシ樹脂から成
るコーテイング材は、水分を透過するためコーテ
イング層を透過しSiチツプとガラス基板間の空〓
に水分が入り、ガラス基板回路面で水分が結露す
るため回路間でリーク電流が生じ、誤動作する。
〔発明の目的〕
本発明の目的は、Siチツプとガラス基板との間
の50〜200μmの間〓に、低熱膨張エポキシ系コー
テイング材を満すコーテイング方法を見出すこと
により、耐熱疲労性及び耐湿信頼性を有する
CCBの樹脂コーテイング実装方法を提供するこ
とにある。
〔発明の概要〕
本発明を概説すれば、本発明は半導体素子チツ
プの実装方法に関する発明であつて、はんだバン
プを介して半導体素子チツプ上の端子と、配線を
形成した基板とをはんだ接合した、該基板とチツ
プとの間〓が50〜200μmである半導体素子チツプ
の実装方法において、熱硬化性エポキシ樹脂組成
物100部と石英粉30〜140部（体積）とから成るコ
ーテイング材組成物を、チツプの少なくとも一辺
を残して該チツプの周囲に塗布し、次いで該コー
テイング材組成物を加熱し粘度を下げて、配線を
形成した基板とチツプとの間〓に流し込み、該コ
ーテイング材で該50〜200μmの間〓を充てんする
工程を含むことを特徴とする。
その後前記コーテイング材組成物で、チツプ全
体を覆うようにコーテイングすることが望まし
い。
本発明者らは、上記目的を達成するため、以下
の検討を進めた。まず第２図に示したように、チ
ツプ全体を覆うようにコーテイング材組成物３を
塗布した。この際、Siチツプとガラス基板の間〓
が50〜200μmと狭いこと、コーテイング材組成物
は低熱膨張化のために多量の石英粉が混合されて
いるので見かけの粘度が高いこと、などにより、
チツプと基板の間〓にコーテイング材を充てんす
ることができず、第２図に示したようにチツプと
基板間に空〓ができる。この状態で加熱硬化する
と、空〓の空気が熱膨張し、第１図に示したよう
な前述の欠陥部が生じると共に、Siチツプとガラ
ス基板間にはコーテイング材は充てんされない。
次に、前述と同様にチツプ全体を覆うようにコ
ーテイング材組成物を塗布し、加熱硬化する途中
過程、すなわち、硬化に要する所定温度に達して
間〓の空気が十分に膨張し、コーテイング材の外
に空気が出た後で、かつ硬化する以前に、空気が
飛散した後の凹部欠陥を修正した。その結果、凹
部欠陥がなくなり、表面形状は良好となつた。し
かし、チツプと基板間の間〓はコーテイング材で
満すことができなかつた。
次に、第２図に示すようにコーテイング材組成
物を、チツプ全体が覆われるように塗布した後、
オートクレーブに入れ、加圧硬化を行つた（２
Kg／cm2、５Kg／cm2）。
その結果、コーテイング材は、Siチツプと基板
間の間〓にかなり入り込むようになつた。しかし
完全には満すことができなかつた。
次に、第２図に示すようにコーテイング材組成
物を塗布した後、減圧下で熱硬化を行つた。その
結果、ほとんど効果はみられなかつた。次に最初
に減圧下で加熱し、途中で加圧下に切換えて硬化
を行つた。その結果、チツプと基板間の空〓は非
常に小さくなつた。しかし空〓を完全無にするこ
とができず、気泡状となつて残つた。またこのよ
うな方法はオートクレーブを必要とするために、
バツチ処理となり、数多くのチツプをコートする
量産工程では採用がむずかしい等の欠点がある。
上記知見を基に、簡易でかつ量産工程の流れ作
業に適した方法で、チツプと基板間の間〓を完全
にコーテイング材で満すコーテイング方法を種々
検討し、本発明に達した。すなわち、第３図〜第
５図に示すように、チツプ周辺の一辺以上をコー
テイングせず、空気抜きを作り、かつ好ましくは
少量のコーテイング材組成物をチツプ高さとほぼ
同程度の高さに塗布し、加熱して、コーテイング
材組成物を溶融し粘度を下げる。この方法によれ
ば、Siチツプと配線が形成された基板間にコーテ
イング材が流れ、間〓は、コーテイング材で完全
に満される。なお、この後必要に応じてコーテイ
ング材組成物でチツプ全体を覆うように塗布し、
加熱硬化を行つても、基板とチツプ間の空〓の空
気は既にコーテイング材で完全に置換されている
ため、コーテイングに気泡が生ずる等の問題がな
かつた。
本発明において、石英粉が30体積部未満である
と、コーテイング材の熱膨張係数が大きく、はん
だ接合のはんだとの熱膨張差が大きくなるため、
ヒートサイクルテストではんだ断線が生じる。他
方、石英粉が140体積部を超えると、コーテイン
グ組成物の粘度が高くなり、50〜200μmの間〓へ
の充てんが極度に困難となる。な、本発明におけ
る熱硬化性エポキシ樹脂組成物とは、エポキシ樹
脂を含有する接合剤を意味し、したがつて、石英
粉以外の助剤、添加剤等を含有していてもよい。
また、チツプと基板間の間〓が50〜200μmであ
る理由は、本発明で使用する石英粉は、市販の常
用のものであるが、その平均粒径は７〜8μmで、
50μmのものを５％程度含有しているため、間〓
が50μm未満では充てんが困難である。他方、本
発明において、コーテイング材組成物を加熱し、
粘度を下げて間〓に流し込む際には、該組成物が
毛細管現象により間〓を充てんするため、200μm
を超えると、この毛細管現象力が少なくなり、充
てんが困難となるからである。
上記方法で、Siチツプと配線を形成した基板の
間〓をコーテイング材で完全に満した場合と、従
来法でコーテイングし、Siチツプと基板間が空〓
になつている場合と耐湿信頼性（回路面のリーク
電流）を調べた結果、本発明の方法によりコーテ
イングしたものは、耐湿信頼性が著しく向上し
た。
更に、本発明のコーテイング方法は、見かけ上
の粘度が高い材料の場合に限らず、いかなる材料
の場合も気泡をなくする効果は大きい。
〔実施例〕
以下、本発明を実施例により更に具体的に説明
するが、本発明はこれら実施例に限定されない。
実施例 １
(1) コーテイング材料（部は重量部を意味する）
エポキシ樹脂（EP828） 100.0部
ジシアンジアミド 10.0部
2P4MHZ（四国化成製） 5.0部
カツプリング剤 2.0部
（Ａ−187，日本ユニカ製）
上記組成物をらいかい機を用いて１〜２時間ら
いかい混練する。次に、得られた樹脂組成物（比
重1.0）の100ｇに対して、石英粉すなわちEMC
−Y40（龍森社、比重2.2）を242ｇ添加し、0.5〜
1.5時間らいかい混練する。そして最後に５〜20
分間減圧状態でらいかい混練して、コーテイング
材組成物に混入した空気を脱気して、コーテイン
グ材組成物を完成した〔樹脂組成物：石英粉＝
100：110（体積部）＝47.6：52.4（体積％）〕。
(2) 塗布方法
上記コーテイング材組成物を第３図に示したよ
うに、ガラス基板にSiチツプをCCB接合した試
験片のSiチツプの一辺にのみ、かつチツプの高さ
と同程度の高さにコーテイング３し、120℃５分
間加熱した。その結果、コーテイング材組成物
は、粘度が低下してチツプと基板の間〓に流れ、
チツプと基板間の空〓は気泡を生ずることなく、
コーテイング材で完全に満された。次に所定量の
コーテイング材組成物を所定の形状で、チツプ全
体を覆うように塗布し、120℃２時間保温して硬
化反応を完結し、樹脂コートした実装品を得た。
実施例 ２
実施例１のコーテイング材組成物を用い、実施
例１のCCB接続試験片を用い、第４図に示すよ
うにSiチツプの二辺に、チツプの高さと同程度の
高さにコーテイング３し、120℃５分間加熱した。
その結果、コーテイング材は、チツプと基板の間
〓に流れ、チツプと基板間の空〓は気泡を生ずる
ことなくコーテイング材で完全に満された。以後
の操作は実施例１と同じに行つた。
実施例 ３
実施例１のコーテイング材組成物及びCCB接
続試験片を用い、第５図に示すようにSiチツプの
三辺に、チツプの高さと同程度の高さにコーテイ
ング３し、120℃５分間加熱した。その結果、空
〓はコーテイング材で完全に置換されていた。以
後の操作は実施例１と同じに行つた。
実施例 ４
実施例１において、同じ樹脂組成物100ｇに対
して、同じ石英粉を308ｇ使用した〔すなわち樹
脂組成物：石英粉＝100：140（体積部）＝42：58
（体積％）〕以外は、実施例１と同じ操作を行つ
た。
その結果、コーテイング材は、チツプと基板の
間〓に流れ、チツプと基板間の空〓は気泡を生ず
ることなくコーテイング材で完全に満された。
実施例 ５
実施例１において、同じ樹脂組成物100ｇに対
して、同じ石英粉を66ｇ使用した〔すなわち樹脂
組成物：石英粉＝100：30（体積部）＝77：23（体積
％）〕以外は、実施例１と同じ操作を行つた。
その結果、コーテイング材は、チツプと基板の
間〓に流れ、チツプと基板間の空〓は気泡を生ず
ることなくコーテイング材で完全に満された。
比較例 １
実施例１と同じコーテイング材組成物及び
CCB接続試験片を用い、Siチツプの全体が覆わ
れるようにコーテイングし、加熱硬化した。その
結果、Siチツプと基板の間には空〓が生じてい
た。
次に本発明のコーテイング法で、Siチツプと基
板間をコーテイング材で満した場合と、比較例の
空〓となつている場合及びコーテイングしない裸
チツプの状態の三者について、−30℃80℃の温
度サイクル試験によるはんだ接続部の断線、70℃
95％RHでの湿気により、電極間のリーク電流に
よる耐湿試験の結果を表１に示す。
[Field of Application of the Invention] The present invention relates to resin coating mounting in which a solder electrode terminal formed on an element surface and a substrate terminal are connected by solder, and in particular, a resin coating is applied to the 50 to 200 μm between the chip and the electrode terminal substrate. The objective is to provide mounted products with high moisture resistance and reliability by completely satisfying the following requirements. [Background of the Invention] Conventionally, in mounting Si chips for display elements using glass substrates, as shown in FIG.
(Controlled Collapse Bonding) After bonding,
The surrounding area is made of low expansion epoxy resin (contains quartz powder)
It is known that this coating can improve thermal fatigue resistance. However, when coating the above-mentioned mounting chip using the usual method, Si
The gap between the chip and the glass substrate cannot be filled with the resin, and some parts of the circuit wired to the glass substrate are not coated with the resin. In extreme cases, as shown in Figure 1, if the Si chip 2 is coated with the coating material 3 and heated to harden the coating material, the viscosity of the coating material will decrease and the space between the Si chip and the glass substrate will be reduced. The air expands in volume, and a portion of this air breaks through the coating film and scatters to the outside. As a result,
The air passage 6 becomes weaker than other parts, and a concave mark 5 is created in the part where the air is scattered. In the case of the above coating, if you do a humidity test (70℃, 95-100% RH), it will last for 150-200 hours.
There is a problem in that leakage current occurs between circuits, resulting in malfunction. The reason for this is that the coating material made of epoxy resin allows moisture to pass through the coating layer, causing the void between the Si chip and the glass substrate to penetrate.
Moisture enters the glass substrate and condenses on the circuit surface of the glass substrate, causing leakage current between the circuits and causing malfunction. [Object of the Invention] The object of the present invention is to find a coating method that fills the area between 50 and 200 μm between a Si chip and a glass substrate with a low thermal expansion epoxy coating material, thereby improving thermal fatigue resistance and moisture resistance. have sex
The purpose of the present invention is to provide a resin coating mounting method for CCB. [Summary of the Invention] To summarize the present invention, the present invention relates to a method for mounting a semiconductor element chip, and includes a method for soldering a terminal on a semiconductor element chip and a substrate on which wiring is formed via solder bumps. , in a method for mounting a semiconductor chip in which the distance between the substrate and the chip is 50 to 200 μm, a coating material composition comprising 100 parts of a thermosetting epoxy resin composition and 30 to 140 parts (by volume) of quartz powder is used. , the coating material composition is applied around the chip, leaving at least one side of the chip, and then the coating material composition is heated to lower the viscosity and poured between the chip and the substrate on which the wiring is formed, and the coating material is applied to the periphery of the chip. It is characterized in that it includes a step of filling between 200 μm and 200 μm. Thereafter, it is desirable to coat the entire chip with the coating material composition. In order to achieve the above object, the present inventors conducted the following studies. First, as shown in FIG. 2, coating material composition 3 was applied to cover the entire chip. At this time, between the Si chip and the glass substrate
The coating material composition has a high apparent viscosity because it contains a large amount of quartz powder to reduce thermal expansion.
The coating material cannot be filled between the chip and the substrate, and a void is created between the chip and the substrate as shown in FIG. When heat-cured in this state, the empty air expands thermally, causing the aforementioned defective portion as shown in FIG. 1, and the space between the Si chip and the glass substrate is not filled with the coating material. Next, the coating material composition is applied to cover the entire chip in the same manner as described above, and the coating material composition is heated and cured during the process, that is, when the predetermined temperature required for curing is reached, the air in between is sufficiently expanded, and the coating material is heated. After the air came out and before it hardened, we fixed the recess defects after the air was blown out. As a result, there were no concave defects and the surface shape was good. However, the gap between the chip and the substrate could not be filled with the coating material. Next, as shown in FIG. 2, after applying the coating material composition so as to cover the entire chip,
Placed in an autoclave and hardened under pressure (2
Kg/cm 2 , 5Kg/cm 2 ). As a result, the coating material has come to penetrate considerably between the Si chip and the substrate. However, it was not completely satisfied. Next, as shown in FIG. 2, a coating material composition was applied and then thermally cured under reduced pressure. As a result, almost no effect was observed. Next, the material was first heated under reduced pressure, and then switched to pressurized midway through for curing. As a result, the space between the chip and the substrate has become extremely small. However, the sky could not be completely emptied and remained in the form of bubbles. Also, since this method requires autoclaving,
It has drawbacks such as batch processing, which makes it difficult to use in mass production processes that require coating a large number of chips. Based on the above knowledge, various coating methods were investigated to completely fill the gap between the chip and the substrate with a coating material using a method that is simple and suitable for the flow of mass production processes, and the present invention was achieved. That is, as shown in FIGS. 3 to 5, one or more sides around the chip are not coated, an air vent is created, and preferably a small amount of the coating material composition is applied to a height approximately equal to the height of the chip. , heating to melt the coating material composition and reduce its viscosity. According to this method, the coating material flows between the Si chip and the substrate on which wiring is formed, and the gap is completely filled with the coating material. After this, if necessary, apply a coating material composition to cover the entire chip.
Even when heat curing was performed, the air in the space between the substrate and the chip had already been completely replaced by the coating material, so there were no problems such as the formation of bubbles in the coating. In the present invention, if the amount of quartz powder is less than 30 parts by volume, the coefficient of thermal expansion of the coating material will be large, and the difference in thermal expansion with the solder of the solder joint will be large.
Solder breakage occurs during heat cycle tests. On the other hand, if the amount of quartz powder exceeds 140 parts by volume, the viscosity of the coating composition increases and it becomes extremely difficult to fill the coating composition between 50 and 200 μm. Note that the thermosetting epoxy resin composition in the present invention means a bonding agent containing an epoxy resin, and therefore may contain auxiliaries, additives, etc. other than quartz powder. Furthermore, the reason why the distance between the chip and the substrate is 50 to 200 μm is that the quartz powder used in the present invention is commercially available and has an average particle size of 7 to 8 μm.
Since it contains about 5% of 50μm particles,
If the diameter is less than 50 μm, filling is difficult. On the other hand, in the present invention, heating the coating material composition,
When lowering the viscosity and pouring into the gap, the composition fills the gap by capillary action, so
This is because if it exceeds this, the capillary action force decreases and filling becomes difficult. With the above method, there is a case where the space between the Si chip and the substrate on which wiring is formed is completely filled with the coating material, and a case where the space between the Si chip and the substrate is filled with the coating material using the conventional method.
As a result of investigating the moisture resistance reliability (leakage current on the circuit surface), it was found that the moisture resistance reliability of the coating coated by the method of the present invention was significantly improved. Furthermore, the coating method of the present invention is highly effective in eliminating air bubbles not only in the case of materials with high apparent viscosity but also in the case of any material. [Examples] Hereinafter, the present invention will be explained in more detail with reference to Examples, but the present invention is not limited to these Examples. Example 1 (1) Coating material (parts mean parts by weight) Epoxy resin (EP828) 100.0 parts Dicyandiamide 10.0 parts 2P4MHZ (Shikoku Kasei) 5.0 parts Coupling agent 2.0 parts (A-187, Nippon Unica) Above composition Knead the material for about 1 to 2 hours using a mulch machine. Next, quartz powder or EMC powder was added to 100 g of the obtained resin composition (specific gravity 1.0).
-Add 242g of Y40 (Tatsumorisha, specific gravity 2.2), 0.5~
Knead for about 1.5 hours. And finally 5-20
The coating material composition was completed by kneading it under reduced pressure for 1 minute to deaerate the air mixed in the coating material composition [Resin composition: quartz powder=
100:110 (volume parts) = 47.6:52.4 (volume %)]. (2) Application method As shown in Figure 3, the above coating material composition was applied only to one side of the Si chip of a test piece in which Si chips were CCB bonded to a glass substrate, and at a height comparable to the height of the chip. Coating 3 and heating at 120°C for 5 minutes. As a result, the coating material composition decreases in viscosity and flows between the chip and the substrate.
The air space between the chip and the board does not create bubbles,
Completely filled with coating material. Next, a predetermined amount of the coating material composition was applied in a predetermined shape so as to cover the entire chip, and kept at 120° C. for 2 hours to complete the curing reaction, thereby obtaining a resin-coated mounted product. Example 2 Using the coating material composition of Example 1 and the CCB connection test piece of Example 1, coating was applied to two sides of a Si chip at a height comparable to the height of the chip, as shown in Fig. 4. 3 and heated at 120°C for 5 minutes.
As a result, the coating material flowed between the chip and the substrate, and the space between the chip and the substrate was completely filled with the coating material without creating any air bubbles. The subsequent operations were performed in the same manner as in Example 1. Example 3 Using the coating material composition of Example 1 and the CCB connection test piece, coating 3 was applied to three sides of a Si chip at a height comparable to that of the chip as shown in Fig. 5, and the coating was heated at 120°C. Heated for a minute. As a result, the void was completely replaced by the coating material. The subsequent operations were performed in the same manner as in Example 1. Example 4 In Example 1, 308 g of the same quartz powder was used for 100 g of the same resin composition [i.e., resin composition: quartz powder = 100:140 (parts by volume) = 42:58
(Volume %)] The same operation as in Example 1 was performed except for the following. As a result, the coating material flowed between the chip and the substrate, and the space between the chip and the substrate was completely filled with the coating material without creating any air bubbles. Example 5 In Example 1, 66 g of the same quartz powder was used for 100 g of the same resin composition [i.e., resin composition: quartz powder = 100:30 (volume parts) = 77:23 (volume %)]. The same operations as in Example 1 were performed. As a result, the coating material flowed between the chip and the substrate, and the space between the chip and the substrate was completely filled with the coating material without creating any air bubbles. Comparative Example 1 Same coating material composition as Example 1 and
Using a CCB connection test piece, the Si chip was coated to cover the entire surface and cured by heating. As a result, a void was created between the Si chip and the substrate. Next, using the coating method of the present invention, three conditions were tested: -30℃80℃ Disconnection of solder joints due to temperature cycle test at 70℃
Table 1 shows the results of a moisture resistance test using leakage current between electrodes due to humidity at 95% RH.
本発明によれば、チツプと基板の空〓を完全に
コーテイング材で満すことができるので、耐湿信
頼性を著しく向上できる効果がある。
According to the present invention, since the space between the chip and the substrate can be completely filled with the coating material, the moisture resistance reliability can be significantly improved.
第１図、第２図は従来のコーテイング法による
断面図、第３図〜第５図は本発明の実施例による
コーテイング法を示す図であり２段階塗布のう
ち、第１段階目の塗布状態を示し、それぞれａは
断面図、ｂは平面図である。
１……ガラス基板、２……Siチツプ、３……コ
ーテイング材、４……CCB、５……空気飛散の
痕、６……空気の通路。
Figures 1 and 2 are cross-sectional views according to the conventional coating method, and Figures 3 to 5 are diagrams showing the coating method according to an embodiment of the present invention, showing the coating state in the first stage of two-stage coating. , where a is a cross-sectional view and b is a plan view. 1... Glass substrate, 2... Si chip, 3... Coating material, 4... CCB, 5... Traces of air scattering, 6... Air passage.
Claims (1)
端子と、配線を形成した基板とをはんだ接合し
た、該基板とチツプとの間〓が50〜200μmである
半導体素子チツプの実装方法において、熱硬化性
エポキシ樹脂組成物100部と石英粉30〜140部（体
積）とから成るコーテイング材組成物を、チツプ
の少なくとも一辺を残して該チツプの周囲に塗布
し、次いで該コーテイング材組成物を加熱し粘度
を下げて、配線を形成した基板とチツプとの間〓
に流し込み、該コーテイング材で該50〜200μmの
間〓を充てんする工程を含むことを特徴とする半
導体素子チツプの実装方法。1. In a mounting method for a semiconductor element chip in which terminals on a semiconductor element chip and a substrate on which wiring is formed are soldered together via solder bumps, and the distance between the substrate and the chip is 50 to 200 μm, thermosetting A coating material composition consisting of 100 parts of an epoxy resin composition and 30 to 140 parts (by volume) of quartz powder is applied around the chip, leaving at least one side of the chip, and then the coating material composition is heated to reduce the viscosity. between the board and the chip on which wiring was formed.
1. A method for mounting a semiconductor chip, comprising the step of: pouring the coating material into the coating material and filling the area between 50 and 200 μm with the coating material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59001977A JPS60147140A (en) | 1984-01-11 | 1984-01-11 | Mounting process of semiconductor element chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59001977A JPS60147140A (en) | 1984-01-11 | 1984-01-11 | Mounting process of semiconductor element chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60147140A JPS60147140A (en) | 1985-08-03 |
| JPH0315337B2 true JPH0315337B2 (en) | 1991-02-28 |
Family
ID=11516597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59001977A Granted JPS60147140A (en) | 1984-01-11 | 1984-01-11 | Mounting process of semiconductor element chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60147140A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0340492A3 (en) * | 1988-05-02 | 1990-07-04 | International Business Machines Corporation | Conformal sealing and interplanar encapsulation of electronic device structures |
| US6316528B1 (en) | 1997-01-17 | 2001-11-13 | Loctite (R&D) Limited | Thermosetting resin compositions |
| JP3543902B2 (en) * | 1997-01-17 | 2004-07-21 | ヘンケル ロックタイト コーポレイション | Semiconductor device mounting structure and mounting method |
| US6274389B1 (en) | 1997-01-17 | 2001-08-14 | Loctite (R&D) Ltd. | Mounting structure and mounting process from semiconductor devices |
| JP3982082B2 (en) * | 1998-09-28 | 2007-09-26 | ソニー株式会社 | Manufacturing method of semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4870479A (en) * | 1971-12-23 | 1973-09-25 | ||
| JPS5249643Y2 (en) * | 1973-06-06 | 1977-11-11 | ||
| JPS58127338A (en) * | 1982-01-25 | 1983-07-29 | Sharp Corp | Structure of electronic part |
-
1984
- 1984-01-11 JP JP59001977A patent/JPS60147140A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60147140A (en) | 1985-08-03 |
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