JPH0315365B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Industrial Application Field The present invention relates to a variable reactance circuit that can generate an equivalent reactance that changes from a predetermined negative value to a predetermined positive value, and particularly relates to a variable reactance circuit that can generate an equivalent reactance that changes from a predetermined negative value to a predetermined positive value. The purpose is to prevent abnormal oscillation of the circuit.

(b) Prior Art Japanese Unexamined Patent Publication No. 59-57515 describes a variable reactance circuit that can generate an equivalent reactance that varies from a predetermined negative value to a predetermined positive value. As shown in FIG. 2, the variable reactance circuit includes first and second transistors 1 and 2 whose emitters are commonly connected, third and fourth transistors 3 and 4 whose emitters are also commonly connected, and a first transistor. and a feedback capacitor 5 connected between the common base of the fourth transistors 1 and 4 and the common collector of the second and fourth transistors 2 and 4, and the common base of the first and fourth transistors 1 and 4. A resistor 6 connected between the common base of the second and third transistors 2 and 3 and a common base of the second and fourth transistors 2 and 4 by inverting the collector currents of the first and third transistors 1 and 3. a current inversion circuit 7 that supplies the collector; a first variable current source 8 connected to the common emitters of the first and second transistors 1 and 2; and a first variable current source 8 connected to the common emitters of the third and fourth transistors 3 and 4. Second
It is composed of a variable current source 9 and a constant voltage source 10 connected to the common base of the second and third transistors 2 and 3.

When a predetermined current is applied to the first variable current source 8 and the operation of the second variable current source 9 is stopped, the variable reactance circuit of FIG. It operates as a reactance circuit, and the equivalent admittance Y1 seen from the output terminal ₁₁ is _Y1 = 1-gmR/R+1/jωC...(1) [However, gm is the mutual conductance, R is the resistance value of the resistor 6, and C is the capacitance of the capacitor 5, and ω is the angular frequency]. In the above formula (1), gmR≫1, R≪
If 1/ωC, then Y ₁ =−jωgmRC (2), and the circuit of FIG. 2 exhibits negative reactance, the value of which is −gmRC. In that case, depending on the current flowing through the first variable current source 8, the first and second
Mutual conductance gm of transistors 1 and 2
changes, so the reactance also changes, and eventually the second
The circuit shown in the figure is equivalent to a capacitor having a reactance ranging from a predetermined negative value to zero.

On the other hand, a predetermined current is applied to the second variable current source 9,
When the operation of the first variable current source 8 is stopped, the variable reactance circuit shown in FIG. 2 operates as a positive reactance circuit mainly composed of the third and fourth transistors 3 and 4, and the equivalent The admittance Y ₂ is as follows: Y ₂ =1+gmR/R+1/jωC (3). In the above formula (3), gmR≫1, R≪
If 1/ωC, then Y ₁ =jωgmRC (4), and the circuit shown in FIG. 2 exhibits a positive reactance, the value of which is gmRC. Since the mutual conductance gm of the third and fourth transistors 1 and 2 changes according to the current flowing through the second variable current source 9, the reactance also changes, and the circuit of FIG. It becomes equivalent to a capacitor with reactance up to the value. Therefore, by using the circuit shown in FIG. 2, it is possible to obtain an equivalent capacitor having a reactance that varies from a predetermined negative value to a predetermined positive value.

(c) Problems to be solved by the invention However, the reactance circuit in FIG.
There was a risk of parasitic oscillation occurring at high frequencies. In other words, as the frequency increases, 1/ωC becomes smaller, and the condition R = 1/ωC breaks down, so the real part of equation (1) cannot be ignored with respect to the imaginary part, and the feedback capacitor 5 acts as a positive feedback capacitor, potentially causing parasitic oscillation.
If parasitic oscillation occurs, the reactance circuit shown in FIG. 2 will not operate normally as a negative reactance circuit, so when using the reactance circuit shown in FIG. 2, it is necessary to limit the frequency band.

In order to prevent parasitic oscillation in the negative reactance circuit mainly composed of the first and second transistors 1 and 2, an oscillation prevention capacitor may be connected between the base and collector of the first transistor 1. The technique of connecting a capacitor between the base and collector of a transistor to prevent oscillation is a common technical means in this field, but when applied to a variable reactance circuit like the one shown in Figure 2, it causes another disadvantage and is undesirable. . When an oscillation prevention capacitor is inserted between the base and collector of the first transistor 1, the capacitor is also inserted between the collector of the third transistor 3 and the base of the fourth transistor 4. The positive reactance circuit consisting of four transistors 3 and 4 is adversely affected. That is, when the capacitor is inserted, the voltage from the collector of the third transistor 3 to the fourth transistor
Since an unnecessary positive feedback path to the base of the transistor 4 is formed, parasitic oscillation occurs, causing a problem that the positive reactance circuit mainly composed of the third and fourth transistors 3 and 4 does not operate normally. Furthermore, when the capacitor is inserted, the second
If the reactance circuit shown in the figure is used to control the oscillation frequency of an oscillation circuit and a positive reactance circuit is operated, spurious oscillation will occur at the frequency of the parasitic oscillation, resulting in a significant change in the oscillation frequency and making it unusable. There was a problem.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes connecting a capacitor between the base and collector of the first transistor constituting the negative reactance circuit, and The present invention is characterized in that means is provided between the collector of one transistor and the collector of a third transistor constituting the positive reactance circuit, for making the impedance high when the negative reactance circuit is inactive.

(E) Effect According to the present invention, parasitic oscillation of the negative reactance circuit can be prevented by inserting a capacitor. Further, since a means is provided for making the negative reactance circuit high impedance when it is not in operation, parasitic oscillation in the positive reactance circuit can be prevented by inserting the capacitor.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention.
12 is an oscillation prevention capacitor connected between the base and collector of the first transistor 1, and 13
is a diode-connected fifth transistor connected between the collector of the first transistor 1 and the collector of the third transistor 3. Furthermore, the first
In the figure, circuit elements that are the same as those in FIG. 2 are given the same reference numerals, and their explanations will be omitted.

The negative reactance circuit mainly composed of the first and second transistors 1 and 2 exhibits a negative reactance depending on the current flowing through the first variable current source 8, and its admittance is as shown in equation (1). and,
Since the capacitor 12 for preventing oscillation is connected between the base and collector of the first transistor 1,
The negative reactance circuit does not cause parasitic oscillation. The current flowing through the first variable current source 8 is divided by the first and second transistors 1 and 2, and the collector current of the first transistor 1 is supplied from the current inverting circuit 7 via the diode-connected fifth transistor 13. be done. At this time, since the collector-emitter impedance of the fifth transistor 13 is very small, the fifth transistor 13 does not interfere with the normal operation of the negative reactance circuit.

The positive reactance circuit mainly composed of the third and fourth transistors 3 and 4 exhibits a positive reactance in accordance with the current flowing through the second variable current source 9, and its admittance is as shown in equation (3). that time,
Since no current flows through the first variable current source 8, no current flows through the diode-connected fifth transistor 13, and the collector of the fifth transistor 13
The impedance between the emitters becomes high. Therefore, the positive feedback path between the collector of the third transistor 3 and the base of the fourth transistor 4 due to the insertion of the capacitor 12 is cut off, and the normal operation of the positive reactance circuit is no longer disturbed.

In the embodiment of FIG. 1, the means for achieving high impedance when the first current source 8 is inoperable is as follows:
Since the diode-connected fifth transistor 13 is used, the voltage drop in the fifth transistor 13 is as small as V _BE (=0.7V), making it possible to provide a variable reactance circuit that can be used with a power supply voltage as low as 5V. . However, if there is no limit to the power supply voltage, as a means for achieving the high impedance,
A high resistance of about 10KΩ can also be used. Further, as the means for achieving high impedance,
It is also possible to use a switch that opens and closes depending on the output of a detection circuit that detects the current flowing through the first current source 8. In that case, the switch may be closed when the detection circuit detects the current, and the switch may be opened when the detection circuit does not detect the current.

(G) Effects of the Invention As described above, according to the present invention, it is possible to reliably prevent parasitic oscillation in a variable reactance circuit exhibiting positive and negative equivalent reactances. For that reason,
The normal operating frequency range of the variable reactance circuit can be expanded, and the range of use can be expanded. In particular, when the variable reactance circuit is used for controlling the oscillation frequency of an oscillation circuit,
It can also prevent spurious oscillations. Furthermore, if diode-connected transistors are used as in the embodiment shown in FIG. 1, a variable reactance circuit that operates at a low power supply voltage can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional variable reactance circuit. 1, 2, 3, 4...first, second, third, fourth transistor, 5...capacitor, 6...resistor, 7
...Current inversion circuit, 8, 9...First and second variable current sources, 12...Capacitor, 13...Fifth transistor.

Claims (1)

[Claims] 1. First and second transistors whose emitters are commonly connected, third and fourth transistors whose emitters are commonly connected, and a common base of the first and fourth transistors and a common collector of the second and fourth transistors. a capacitor connected between the first
and a resistor connected between the common base of the fourth transistor and the bias source, and a current inversion circuit connected between the common collectors of the first and third transistors and the common collectors of the second and fourth transistors. , a first variable current source connected to the common emitters of the first and second transistors, and a second variable current source connected to the common emitters of the third and fourth transistors; A variable reactance circuit that generates a negative equivalent reactance at the output terminal connected to the common collector of the second and fourth transistors depending on the current, and a positive equivalent reactance at the output terminal depending on the current flowing through the second variable current source. In this method, a capacitor for preventing oscillation is inserted between the base and collector of the first transistor, and a high impedance is formed between the collector of the first transistor and the collector of the third transistor when no current flows in the first variable current source. A variable reactance circuit characterized by having a means arranged therein.