JPH0315378B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a MOS that transmits analog signals.
Regarding MOS FET switch circuit using FET. [Technical background of the invention and its problems] With the development of analog ICs such as integrated analog-to-digital conversion circuits, high performance voltage comparison circuits are required to be built into these ICs. There are three characteristics particularly required of this voltage comparator circuit: high-speed response, offset resistance, and high resolution, and these characteristics are interrelated. FIG. 1 is a configuration diagram of a conventional amplifier circuit used in a chopper-type or auto-zero sampled data-type voltage comparator circuit configured with MOS FETs. This amplifier circuit is a P channel MOS FET
C consisting of 11 and N channel MOS FET12
- A MOS using an N-channel MOS FET 14 is connected between the input terminal and output terminal of the MOS inverter 13 .
Connect with FET switch circuit 15 , and further connect with C-
A coupling capacitor 1 is provided on the input end side of the MOS inverter 13 .
6 is provided. An input signal IN is supplied to the input terminal of the capacitor 16, and an output signal OUT is output from the C-MOS inverter 13. Further, a signal S for controlling the switch of this MOS FET 14 is supplied to the gate electrode of the N-channel MOS FET 14 constituting the MOS FET switch circuit 15, and furthermore, a signal S for controlling the switch of this MOS FET 14 is supplied to the back gate electrode of this MOS FET 14. is the power supply voltage supplied to this amplifier circuit
One of the voltages V _DD (positive polarity voltage ₎ and the ground voltage V _SS (reference voltage) is supplied.
In an amplifier circuit with such a configuration, first,
This MOS FET 14 is turned on by setting the control signal S supplied to the gate electrode of the MOS FET 14 to the V _DD level. MOS FET 1
4 is turned on, the input terminal voltage of the C-MOS inverter 13 is set to the circuit threshold voltage, and thereby the C-MOS inverter 13
The operating point of is set. Next, the signal S is set to the V _SS level to turn off the MOS FET 14, and in this state the input signal IN is amplified by the C-MOS inverter 13 . Since such an amplifier circuit has a simple circuit configuration and is suitable for integration, it has a wide range of applications as a basic amplifier circuit unit. In addition, as an example of applying a voltage comparison circuit based on this principle to an analog-to-digital conversion circuit, for example, “Monolithic Expandable 6 Bit 20MHz
CMOS/SOS A/D Converter”
ANDREW GFDINGALL, IEEE J.Solid−
State Circuit, vol SC-14, pp. 926-932,
Please refer to ``Dec.1979''. The analog-to-digital conversion circuit described in the above document requires high-speed conversion characteristics, and therefore the operating speed of the amplifier circuit shown in FIG. 1, which is one of the circuit parts with the slowest operating speed, is a problem. It's coming. That is, if the analog-to-digital conversion circuit is to have high-speed conversion characteristics, the C-MOS inverter 13 is turned on by turning on the MOS FET switch circuit 15 in the amplifier circuit.
It is necessary to shorten the time it takes for the operating point to stabilize. However, in the conventional technology, the MOS
Since the FET switch circuit 15 simply uses the MOS FET 14 as a transfer gate, the ground voltage V _SS is supplied to its back gate electrode. Therefore, when the voltage of the input signal IN increases, the on-resistance of the MOS FET 14 increases due to the influence of the so-called back gate bias effect, and therefore the C-MOS inverter 1
The disadvantage is that it takes a long time to set the operating point. In addition, the threshold voltage of MOS FETs varies due to the manufacturing process, so
In the prior art, when the threshold voltage varies toward a higher absolute value, the on-resistance of the MOS FET 14 also increases, and therefore, in this case as well, C-
There is a drawback that it takes a long time until the MOS inverter 13 is set to the operating point. By the way, in another conventional technique for eliminating the above-mentioned drawbacks, the channel width of the MOS FET 14 constituting the MOS FET switch circuit 15 is increased in order to lower its on-resistance.
However, the MOS FET switch circuit 1
In the MOS FET 14 constituting the MOS FET 5, leakage of the control signal S occurs on the source and drain sides due to the feedthrough phenomenon through the parasitic capacitance generated between the gate electrode and the source and drain electrodes. - An offset voltage is generated on both sides of the input and output terminals of the -MOS inverter 13 , and as the channel width of the MOS FET 14 is increased, the value of the parasitic capacitance is also increased, and as a result, the offset voltage is also increased. Therefore, in the conventional technique of increasing the channel width of the MOS FET 14, the offset stress characteristic, which is one of the most important characteristics of a chopper type or auto-zero sampled data type voltage comparison circuit, is impaired. Therefore, it is preferable that the channel axis, that is, the element size, of the MOS FET 14 used for this type of application be made as small as possible. On the other hand, when the MOS FET 14 is actually manufactured with the element dimensions minimized, the on-resistance typically reaches 10KΩ to 100KΩ when the _VDD level of the control signal S supplied to the gate electrode is 5V. In particular, when the operating point voltage of the C-MOS inverter 13 is about 2.5V, the on-resistance becomes high.
It is not uncommon for the resistance to reach around 100KΩ.
Therefore, if the element dimensions of the MOS FET 14 are minimized, it will take a long time to set the operating point, making it impossible to achieve high-speed operation. Furthermore, as mentioned above, the threshold voltage of MOS FETs varies by about ±0.3V due to the manufacturing process, and especially in the case of N-channel MOS FETs, if the threshold voltage varies in the higher direction, the above-mentioned on-resistance will further increase. become. For example, in Figure 2, the gate electrode of an N-channel MOS FET with a ratio W/L of channel width W to channel length L of 6/7 is shown on the mask.
It is a characteristic diagram of input voltage (supply voltage to a source electrode or drain electrode) versus on-resistance when a voltage of 5.0V is supplied. In Figure 2, when the threshold voltage Vth = 1.0V and the input voltage is 2.5V, the on-resistance is approximately 28KΩ, and when the input voltage is 2.5V, the threshold voltage shifts by 0.3V toward the lower Vth. The on-resistance is 19KΩ, and if it is shifted by 0.3V to the higher side, it becomes 65KΩ.
That is, it can be seen that when the threshold electrode pressure varies by the same amount, the on-resistance increases at a higher rate when it varies higher than when it varies lower. [Object of the Invention] Therefore, an object of the present invention is to provide a MOS that has a low on-resistance and can always keep the on-resistance close to a constant value even if the threshold voltage of the MOS FET varies due to the manufacturing process. Our goal is to provide FET switch circuits. [Summary of the invention] In the MOS FET switch circuit according to the present invention,
A bias generation circuit that generates a bias voltage having a value between the supplied power supply voltage and the ground voltage and a value corresponding to the threshold voltage of the MOS FET in the MOS switch is provided, and this bias voltage is applied to the MOS switch.
It is designed to be supplied to the back gate electrode of the switch's MOS FET. [Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. FIG. 3 is a block diagram of a circuit according to an embodiment of the present invention, and parts corresponding to those of the conventional circuit shown in FIG. 1 are given the same reference numerals. In the figure, P channel
MOS FET 11 and N-channel MOS FET 12 constitute a C-MOS inverter (inverting amplification means) 13 , and an N-channel MOS FET (MOS switch) 1 is connected between the input terminal and output terminal of this inverter 13 .
4, and a coupling capacitor 16 is further provided on the input end side of the C-MOS inverter 13 . An input signal IN is supplied to the input terminal of the capacitor 16, and an output signal OUT is output from the C-MOS inverter 13 . In addition, the above N-channel MOS FET
A signal S for controlling the switch of this MOS FET 14 is supplied to the gate electrode of the MOS FET 14. Furthermore, the above C-MOS inverter 1
The sources and drains of P-channel MOS FET 21 and N-channel MOS FET 22 are connected in series between the application points of power supply voltage V _DD and ground voltage V _SS applied to 3, and the common drain connection point of both FETs is connected to the bias voltage output terminal. As 23, a P channel MOS FET 2 is further connected to this bias voltage output terminal 23.
A bias generation circuit 24 is configured by connecting the gate electrodes of the MOS FET 1 and the N-channel MOS FET 22. Further, the bias voltage output terminal 23 of the bias generation circuit 24 is connected to the back gate electrode of the N-channel MOS FET 14. That is, the embodiment circuit shown in FIG.
Connect the input and output terminals of the MOS inverter 13 with an N-channel MOS FET 14 as a MOS switch,
A bias voltage higher than the ground voltage V _SS is always supplied from the bias generation circuit 24 to the back gate electrode of the MOS FET 14. In the embodiment circuit having the above configuration, the bias generation circuit 24 has a circuit configuration in which the input and output terminals of a C-MOS inverter are short-circuited, so that the voltage at the bias voltage output terminal 23 is as follows.
It is equal to the circuit threshold voltage Vthc as a C-MOS inverter expressed by equation (1). Here, Vthp: Threshold voltage of P-channel MOS FET21 Vthp: Threshold voltage of N-channel MOS FET22, and Kp and _KN are P-channel MOS FET21 threshold voltages.
Kp = 1/2・Wp/Lp・ε _px /t _px・μp ……(2) K _N = 1/2・W _{N /} L _N・ε _px /t _px・μ _N ...(3). Here, Wp, W _N :Each channel MOS of P channel MOS FET21 and N channel MOS FET22
Each channel width of FET22 Lp, L _N : P channel MOS FET21 and N
Each channel length of the channel MOS FET 22 t _px : Thickness of gate insulating film ε _px : Dielectric constant μp of gate insulating film, μ _N : Effective mobilities of holes and electrons. As is clear from the above equations (1) to (3), C-MOS
As the circuit threshold voltage Vthc as an inverter, that is, the voltage at the bias voltage output terminal 23 of the bias generation circuit 24 , the P channel MOS FET 2
By setting the channel width and channel length of the 1- and N-channel MOS FETs 22, a voltage having a value between V _DD and V _SS can be obtained. That is,
N-channel MOS FET1 as a MOS switch
A bias voltage higher than V _SS is supplied to the back gate electrode of MOS FET 1.
The apparent threshold voltage of MOS FET 1 is lower than that of the conventional one.
The on-resistance of No. 4 can be set to a sufficiently lower value than the conventional one. Incidentally, considering only the on-resistance, the voltage supplied to the back gate electrode of the MOS FET 14 is preferably higher, and may be set to the value of V _DD itself, but on the other hand, a problem arises in terms of current consumption. This means that between the back gate electrode and each of the source and drain electrodes of the N-channel MOS FET 14 used as a MOS switch, there is a PN layer with a P conductivity type layer on the back gate electrode side.
A junction occurs due to the structure, and if V _DD itself is supplied to the back gate electrode of the MOS FET 14, a current will always flow from the back gate electrode to the source or drain electrode, resulting in extremely large current consumption. Therefore, the bias voltage supplied to the back gate electrode of the N-channel MOS FET 14 needs to be set to a voltage between V _DD and V _DD in consideration of current consumption. Furthermore, when integrating the circuit shown in Figure 3,
N-channel MOS FET14 which is a MOS switch
and N-channel MOS in the bias generation circuit 24
Since the FETs 22 are manufactured using the same process, their respective threshold voltages vary in the same direction with respect to a predetermined threshold voltage. So now, for example
If the threshold voltage of MOS FET 14 fluctuates toward the higher side, and as a result, its on-resistance becomes higher than a predetermined value, the threshold voltage of MOSFET 22 also fluctuates toward the higher side, and the bias expressed by equation (1) above increases. The bias voltage from generation circuit 24 becomes high. Then, since the actual threshold voltage of the MOS FET 14 is lowered, the on-resistance of the MOS FET 14 is lowered. On the other hand, contrary to the above, if the threshold voltage of the MOS FET 14 varies towards the lower side and its on-resistance becomes lower than a predetermined value (lower on-resistance is a good thing for an amplifier circuit) However, the threshold voltage of the MOS FET 22 also varies in the lower direction, and the bias voltage from the bias generation circuit 24 expressed by the above equation (1) becomes lower. Therefore, in this case, the effective threshold voltage of MOS FET 14 is increased, so this MOS FET
The on-resistance of 14 is increased. That is, the bias voltage from the bias generation circuit 24 is
By supplying it to the back gate electrode of the FET 14, the on-resistance of the MOS FET 14 can almost always be kept close to a constant value, and an increase in the on-resistance of the MOS FET 14 can be prevented especially when the threshold voltage becomes high. Can be done. Figure 4 shows the MOS in the above embodiment circuit.
2 is a cross-sectional view showing a specific element structure of a portion of the FET 14 and the bias generation circuit 24. FIG. In the figure, N
Two P- well regions 10 are formed on a type semiconductor substrate 101.
2 and 103 are formed, and in one of the P well regions 102, a pair of N ⁺ type regions 104 and 105 which become the source and drain of the MOS FET 14 are formed.
This P well region 102, that is, MOS FET1
A P ⁺ type region 106 is provided for making contact with the back gate electrode of No. 4. Furthermore, in the other P well region 103, a pair of N ⁺ type regions 107, 1 which become the source and drain of one MOS FET 22 constituting the bias generation circuit 24 are provided.
08 and a P ⁺ type region 109 for making contact with this P well region 103,
A pair of P ⁺ -type regions 110 and 111 are provided on the substrate 101 to serve as the source and drain of the other MOS FET 21 constituting the bias generation circuit 24 .
Then, the gate electrode 11 of the MOS FET 14 is placed over the pair of N ⁺ type regions 104 and 105.
2 is provided, and this gate electrode 112 is provided with a signal S
is supplied. In addition, the pair of N ⁺ type regions 10
The gate electrode 113 of the MOS FET 22 extends over the pair of P ⁺ type regions 110,1
A gate electrode 114 of the MOS FET 21 is provided over the MOS FET 11 , and both gate electrodes 113 and 114 are connected to the bias voltage output terminal 23 . Furthermore, this output terminal 23 has the above-mentioned N ⁺
The type region 107 and the P ⁺ type region 110 are connected,
The output end 23 is connected to the P ⁺ type region 106 .
The P ⁺ type region 111 is connected to a power supply voltage V _DD application point, and the N ⁺ type region 108 and the P ⁺ type region 109 are connected to a ground voltage V _SS application point. Figure 5 shows an N-channel MOS FET that becomes a MOS switch, similar to the characteristic diagram shown in Figure 2 above.
Ratio W/L of channel width W and channel length L of 14
Set it to 6/7 on the mask and connect it to the gate electrode.
Supplying 5.0V voltage and bias generation circuit 2
Set the W/L of P-channel MOS FET21 in 4 to 6/42 on the mask, and the W/L of N-channel MOS FET22 to 35/7 on the mask.
FIG. 3 is a characteristic diagram of input voltage versus on-resistance when the bias voltage supplied to the back gate electrode of MOS FET 14 is set to be approximately 1.2V to 1.5V.
As is clear from Figure 5, the input voltage is 2.5V
And the threshold voltage Vth of MOS FET14 is
15KΩ and 18K at 0.7V, 1.0V, and 1.3V, respectively
The on-resistance value is 25KΩ. These values are 19KΩ, 28KΩ, and 65K in the case of Figure 2 above.
It is obvious that the resistance is significantly reduced compared to Ω. Further, even when the threshold voltage of the MOS FET 14 varies during the manufacturing process, the variation in on-resistance is significantly improved compared to the conventional method. Also, the on-resistance value in FIG. 5 is when the bias voltage is 1.2V to 1.5V, but
By changing the element dimensions of the P and N channel MOS FETs 21 and 22 in the bias generation circuit 24, the voltage can be increased to, for example, 2.0V to 2.5V. By increasing this bias voltage, the MOS FET 14
In addition to further lowering the on-resistance of the bias voltage, it is also possible to further reduce its influence on variations in the threshold voltage, but as mentioned above, the value of this bias voltage is determined by taking into account the current consumption. It should be. 6 to 8 show other embodiments of the present invention, and are configuration diagrams of other examples of the bias generating circuit 24. In FIG. In the circuit shown in FIG. 6, a constant current source circuit 31 is connected between the V _DD application point and the bias voltage output terminal 23, and a resistor 32 and the above-mentioned resistor are connected between the bias voltage output terminal 23 and the V _SS application point.
The drain and source of a MOS FET 33 of the same channel as the MOS FET 14, that is, an N channel, are connected in series, and the gate electrode of this MOS FET 33 is further connected to the bias voltage output terminal 23. In the bias generation circuit having such a configuration, the output current I of the constant current circuit 31,
A bias voltage having a value between V _DD and V _SS is output depending on the resistance value R of the resistor 32 and the element dimensions of the MOS FET. Also, assuming that the resistor 32 does not exist in this circuit, the MOS FET
The threshold voltage of 33 is Vth _N33 , and the bias voltage is
Assuming Vo, the following proportional equation holds between I, Vth ₃₃ and Vo. I∝K (Vo−Vth ₃₃ ) ² ...(4) K: proportionality constant The above formula (4) is the threshold voltage of MOS FET33.
As Vth ₃₃ increases, the bias voltage Vo also increases,
This shows that, on the contrary, when Vth ₃₃ decreases, Vo also decreases. Therefore, even if the bias voltage from this bias generation circuit is used, it will not be affected by variations in threshold voltage due to the manufacturing process, as in the case of the bias generation circuit 24 in the circuit shown in FIG.
The on-resistance of the MOS FET 14 can be kept close to a constant value. Note that the resistor 32 is a MOS
It is provided to obtain a bias voltage Vo, which is a constant voltage added to the voltage between the drain and source of the FET 33. In the circuit shown in FIG. 7, a load resistor 41 is connected between the V _DD application point and the bias voltage output terminal 23, and a load resistor 41 on the same channel as the MOS FET 14 is connected between the bias voltage output terminal 23 and the V _SS application point. That is, the drain and source of an N-channel MOS FET 42 are connected, and the gate electrode of this MOS FET 42 is connected to the bias voltage output terminal 23. In the bias generation circuit having such a configuration, the resistance value of the load resistor 41 and
V _DD and V _SS according to the element dimensions of MOS FET42
A bias voltage having a value between is output. In addition, in this circuit, the output bias voltage is Vo′, and the threshold voltage of MOS FET 42 is Vth ₄₂
Then, the following proportional equation holds between Vo′ and Vth ₄₂ . Vo'∝1/K'Vth _N42 ...(5) K': Constant of proportionality The above equation (5) is the threshold voltage of MOS FET42.
This shows that Vth ₄₂ and bias voltage Vo' are proportional. Therefore, even if this circuit is used, the on-resistance of MOS FET 14 can be adjusted against variations in threshold voltage due to the manufacturing process. It is possible to approach a nearly constant value. Incidentally, in either case in the bias generation circuit shown in FIGS. 6 and 7, the output bias voltage varies depending on the threshold voltage of the N-channel MOS FET 33 or 42. If the on-resistance of the MOS FET 14 simply needs to be lowered without considering variations in the threshold voltage of the MOS FET 14, a bias generation circuit as shown in FIG. 8 can also be used. That is, the eighth
The circuit shown in the figure connects two resistors 51 and 52 in series between a V _DD application point and a V _SS application point, and connects the two resistors 51 and 52 from the bias voltage output terminal 23, which is the series connection point. , 52 to obtain a constant bias voltage divided according to the resistance ratio. Therefore, by supplying the bias voltage obtained by this circuit to the back gate electrode of the MOS FET 14, the on-resistance of the MOS FET 14 can be made sufficiently lower than that of the conventional one. FIG. 9 is a configuration diagram of an applied example circuit of the present invention. This circuit consists of C-MOS inverters 61, 62, and 63 for signal inversion and amplification, and N-channel MOS FETs 64, 65, and 66 for shorting the input and output terminals of each of these inverters to set the operating point.
Amplifying circuits 71 , 72 , and 73 each having coupling capacitances 67, 68, and 69 are connected in cascade to form an amplifying circuit having a high gain as a whole. Furthermore, among the above amplifier circuits, the MOS in the first stage amplifier circuit 77
The back gate electrode of the FET 64 is supplied with a bias voltage Vo ₁ from a bias generation circuit 74 configured by shorting the input and output terminals of a C-MOS inverter, and the bias voltage Vo 1 in the intermediate stage amplifier circuit 72 is supplied to the back gate electrode of the FET 64.
A bias voltage Vo ₂ from a bias generation circuit 75, which is also configured by shorting the input and output terminals of a C-MOS inverter, is supplied to the back gate electrode of No.
The back gate electrode of FET66 also has C-
Bias voltage from the bias generation circuit 76 configured by shorting the input and output terminals of the MOS inverter
Vo ₃ is supplied. When the power supply voltage V _DD supplied to each C-MOS inverter 61, 62, 63 and each bias generation circuit 74, 75, 76 is, for example, 5.0V, the bias voltage Vo ₁ ,
2.0V~2.5V, 1.5V~2.0V, 1.2V as Vo ₂ , Vo ₃
The element size ratio in each bias generation circuit 74, 75, 76 is set so that a voltage of 1.5V to 1.5V can be obtained. Note that a control signal S is supplied to the gate electrodes of the MOS FETs 64, 65, and 66. In a circuit configured like this, the amplifier circuit closer to the input signal IN handles a signal with a smaller voltage.
Accordingly, it is necessary to reduce the on-resistance value of the MOS FET for setting the operating point and increase the operating speed. Therefore, by supplying the highest bias voltage to the back gate electrode of the MOS FET 64 in the first-stage amplifier circuit 71 that is closest to the input signal IN, the amplifier can construct a voltage comparator circuit that is fast as a whole and has offset characteristics. It is a circuit. Note that the present invention is not limited to the above embodiment; for example, in FIG.
Although we have explained the case where the MOS switch connecting between the input and output terminals of the inverter 13 is an N-channel MOS FET 14, this is a P-channel MOS
FET may be used, and if a P-channel one is used, the power supply voltage of each bias generation circuit is
The relationship between V _DD and ground voltage V _SS must be reversed. Furthermore, if the SOS CMOS process is used, as shown in Figure 10, an N-channel MOS FET81 and a P-channel MOS FET81 are used as MOS switches.
It is also possible to use a MOS switch in which MOS FETs 82 are connected in parallel, and in this case, the bias generation circuit is, for example, a C-
If a MOS inverter is used, the configuration will be as shown in the figure. In other words, N-channel MOS FET81
The bias generation circuit 83 for applying a bias voltage to the back gate electrode of the transistor has a P channel MOS FET 84 and an N channel MOS FET 85 connected in series between a V _DD application point and a V _SS application point, and both gate electrodes are connected to their drains. The structure is such that it is connected to a common connection point. On the other hand, P channel MOS
A bias generation circuit 86 for applying a bias voltage to the back gate electrode of the FET 82 connects the P channel MOS FET 8 between the V _SS application point and the V _DD application point.
7 and N channel MOS FET88 are connected in series,
The structure is such that both gate electrodes are connected to the common drain connection point. In each of the embodiments or application examples described above, the present invention was applied to a voltage comparator circuit of an analog-to-digital converter circuit.Next, an example will be described in which the present invention is applied to a switched capacitor integrating circuit. do. FIG. 11 is a circuit diagram of a switched capacitor integration circuit according to the prior art. That is,
This circuit uses MOS FET201 at the timing of _φ1 .
is turned on, the capacitor 202 is charged with the input signal IN, and then the MOS is turned on at the timing of _φ2 .
The FET 203 is turned on to discharge the capacitor 202. In other words, two MOS FET201, 20
3 acts as a resistive element, and the signal passing through this resistive element is integrated by a circuit consisting of a capacitor 204 and an operational amplifier 205. Its detailed operation is described in "JTCaves et al; Sampled Analog
Filtering.Using Swithed Caoacitors as
Resistor Equiva lerts, IEEE J of Solid−
State-Circuits, Vol, SC-12, No. 6, Dec.
1977, P592-P599. The resistance of the two MOS FETs 201 and 203, which act as resistance elements in this integrating circuit, becomes a problem. That is, in general, when the on-resistance increases, it means a decrease in the capacitance ratio of the integrating circuit, and the characteristics deteriorate. So two MOS
Although it is desirable that the element dimensions of FETs 201 and 203 be larger, as in the case of the voltage comparison circuit described above, there is an adverse effect due to the feedthrough of the clock signal due to the parasitic capacitance between the gate and source and between the gate and drain, which is unique to MOS FETs. For,
The dimensions of MOS FETs 201 and 203 have to be reduced. Therefore, as shown in FIG. 12, by applying the present invention to the conventional switched capacitor integration circuit, a P channel MOS FET 206 and an N
A bias voltage Vg ₁ obtained by a bias generation circuit 208 consisting of a channel MOS FET 207 is supplied, and a bias voltage Vg 2 obtained by a bias generation circuit 211 consisting of a P channel MOS FET 209 and an N channel MOS FET 210 _is supplied to the back gate electrode of the MOS FET 205. The on-resistance of MOS FETs 201 and 205 is reduced by supplying φ ₁ ,
Charging and discharging of the charge is completed within the switching period of _φ2 .
Furthermore, the element dimensions of the MOS FETs 201 and 205 can be minimized, and as a result, the influence of feedthrough can be minimized, and high integration can be achieved. [Effects of the Invention] As explained above, according to the present invention, the on-resistance is low, and even if the threshold voltage of the MOS FET varies due to the manufacturing process, the on-resistance can always be kept close to a constant value. We can provide MOS FET switch circuits.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional amplifier circuit, and Figure 2 is a diagram of a conventional amplifier circuit.
A characteristic diagram when a MOS FET is used as a MOS switch. Figure 3 is a configuration diagram of an embodiment of the present invention. Figure 4 is a cross-sectional view specifically showing the element structure of a part of it. Figure 5 is the above-mentioned diagram. 6 to 8 are respectively diagrams showing the configuration of bias generation circuits according to other embodiments of the present invention. FIG. 9 is a diagram showing the configuration of an application example of the present invention. FIG. 10 is a block diagram of a modified example of the present invention, FIG. 11 is a block diagram of a conventional switched capacitor integrating circuit, and FIG. 12 is a block diagram of an application example in which the present invention is applied to a switched capacitor integrating circuit. 11, 21, 82, 84, 87...P channel
MOS FET, 12, 14, 22, 33, 42,
64, 65, 66, 81, 85, 88...N channel MOS FET, 13, 61, 62, 63...
C-MOS inverter, 16, 67, 68, 69
...coupling capacitance, 24,74,75,76,83,
86... Bias generation circuit, 31... Constant current source circuit, 32, 51, 52... Resistor, 41... Load resistance.

Claims (1)

[Scope of Claims] 1. A MOS switch consisting of at least one MOS FET having a gate electrode and a back gate electrode, and a MOS switch formed in the same substrate as the MOS FET in the MOS switch, and a MOS switch in the MOS switch.
It is constructed by short-circuiting the input and output terminals of a complementary MOS inverter consisting of a MOS FET on the same channel as the FET and a MOS FET on the opposite channel. a bias generating means for generating a bias voltage of a value corresponding to the threshold voltage of the MOS FET;
1. A MOS FET switch circuit comprising means for supplying a signal to a back gate electrode of a MOS FET. 2. A MOS switch consisting of at least one MOS FET having a gate electrode and a back gate electrode, a load means inserted between a power supply voltage application point or a reference voltage application point and a bias voltage output terminal, and a MOS FET in the MOS switch. The MOS switch is formed in the same substrate as the MOS switch, and has a gate electrode connected to the bias voltage output terminal and inserted between the bias voltage output terminal and the reference voltage application point or the power supply voltage application point. It consists of a FET and a MOS FET on the same channel, and has a value between the power supply voltage and the reference voltage and is above
A bias generating means for generating a bias voltage having a value corresponding to the threshold voltage of the MOS FET in the MOS switch;
1. A MOS FET switch circuit comprising means for supplying a signal to a back gate electrode of a MOS FET. 3. The MOS FET switch circuit according to claim 2, wherein the load means is constant current generating means. 4. The MOS FET switch circuit according to claim 2, wherein the load means is a resistor.