JPH0315843B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential amplifier circuit, and more particularly to an offset voltage control circuit for a differential amplifier circuit.

Traditionally, complex differential circuits were constructed with individual components,
In many cases, they were constructed using hybrid integrated circuits, and even when they were realized as integrated circuits, they were only small-scale.
For this reason, an AC coupling method (coupling using inductance or capacitance) was often used for coupling between amplifier circuits. With advances in integrated circuit technology, it has become possible to integrate large-scale analog circuits, but as is well known, methods that use inductance or capacitance for interstage coupling are not suitable for integration, so DC coupling methods have been adopted. Ru. In this case, correction of the DC offset voltage becomes a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a differential offset voltage control circuit suitable for a DC-coupled differential amplifier circuit integrated in one stage or in multiple stages. In particular, the present invention provides a differential amplifier circuit equipped with a differential offset voltage control circuit for amplifying a single polarity pulse signal.

According to the present invention, there is provided a differential amplifier having a positive-phase input terminal that receives an input signal, a negative-phase input terminal to which a reference voltage is applied, and a positive-phase and negative-phase output terminal; First and second amplitude detectors are respectively connected to the phase output terminals, and a signal corresponding to the difference between these outputs is sent to the negative phase input of the differential amplifier. A differential amplifier circuit including a difference detection circuit added at both ends is obtained.

Generally, in a DC-coupled differential amplifier circuit, the DC levels of the positive-phase output voltage and the negative-phase output voltage are not the same, and a differential offset voltage is generated due to fluctuation factors inside or outside the amplifier circuit. Particularly in the case of an unbalanced input, a differential offset voltage is generated on the output side due to fluctuations in the DC level of the input signal. Such relationships are shown in FIGS. 1a and 1b. FIG. 1 shows a basic differential circuit, with terminals 101 and 10
2 are positive phase and negative phase input terminals, and terminals 103 and 104 are positive phase and negative phase output ends. Give a voltage V ₁ on which the signal voltage of the positive phase input terminal 101 is superimposed,
FIG. 1b shows the relationship between the input waveform and the output waveform when a DC voltage V _R is applied to the negative phase input terminal 102. Curve 105 and curve 106 show the transfer characteristics of the differential amplifier for positive phase output and negative phase output. Waveform 107 is the waveform of input signal V _I , and waveform 109
and 120 indicate a positive phase output waveform V _P and a negative phase output waveform V _N for this. DC level 108
is the reference voltage level applied to the negative phase input terminal 102
Indicates _VR .

The input and output voltage is now divided into DC and AC components and is expressed by the following equation.

V _I = V _IO + Vi V _R = V _RO V _P + V _PO + vp V _N = V _NO + vn …(1) However, V _IO , V _RO , V _PO and V _NO are positive phase input, negative phase input, and positive phase output. and shows the DC component of the negative phase output.
vi, vp, and vn indicate signal components of positive phase input, positive phase output, and negative phase output. In this case, the DC offset voltage V _IS on the input side and the DC offset voltage V _OS on the output side are expressed by the following equations.

V _IS =V _IO −V _RO V _OS =V _PO −V _NO (2) FIG. 2 is a diagram showing an embodiment of the amplitude detection circuit used in the present invention. Transistors 201, 202,
Resistors 204 and 205 constitute a differential amplifier circuit, including a transistor 203, a resistor 206, and a capacitor 20.
7 constitutes a voltage holding circuit. Only when the signal voltage input to the input terminal 208 is higher than the voltage held by the capacitor 207, the emitter follower 203 is activated, a new voltage is charged to the capacitor 207 through the resistor 206, and the voltage amplitude is maintained. Therefore, the positive phase output of the differential circuit shown in FIG.
When V _P or negative phase output V _N is given, the output terminal 20
9, a voltage given by the following equation appears.

V^ _P = V _PO + v^p or V^ _N = V _NO ……(3) However, V^ _P is the maximum value of the positive phase output voltage V^ _N is the maximum value of the negative phase output voltage, and v^p is the positive phase output voltage. Indicates the maximum value of the phase output signal voltage.

FIG. 3 is a block diagram of an embodiment of the present invention. 30
1 is a single-stage or multi-stage differential amplifier circuit,
305 and 306 are positive phase and negative phase input terminals, 3
07 and 308 are a positive phase output terminal and a negative phase output terminal. 302 and 303 are amplitude detection circuits as shown in FIG. 304 is a difference circuit,
The difference between the outputs of the two amplitude detection circuits 302 and 303 is taken, appropriately amplified, and the output ΔV _F is supplied to the anti-phase input terminal 306 of the differential amplifier circuit 301. In this connection state, if the differential gain of the differential amplifier circuit 301 is A and the gain of the difference circuit 304 is β, the following relational expression is derived.

ΔV _F = β(V^ _P −V^ _N ) = β(V _PO −V _NO +v^p) ……(4) V _PO V _NO = A(V _IO −V _R −ΔV _F ) ……(5 ) From equations (4) and (5), the differential offset voltage V _OS on the output side is V _OS = V^ _PO - V^ _NO = A/1 + βA (V _IO - V _R ) - v^p ……(6 ) v^p = 1/2Av^i, so V _OS = A/1 + βA (V _IO - V _R ) - 1/2Aβv^i ... (7) If Aβ >> 1, then V _OS = V _IO - V _R ／β−1/2Av^i ……(8) Furthermore, if β is sufficiently large, V _OS =−1/2Av^i ……(9) V _IS ＝V _PO −V _NO ／A−1/2v^ i...(9) Equation (9) becomes -1/ on the output side by implementing the present invention.
2Av^i = -v^p This shows that there is a DC offset of -1/2v^i on the input side. Since v^i is the maximum value of the input signal, this offset voltage is equal to 1/2 of the maximum value of the input signal. To illustrate this relationship, the fourth
It will look like the figure. Transfer characteristics of differential amplifier circuit 401
and 402, the positive-sequence input voltage V _I is given a DC offset in the direction of 1/2v^i with respect to the negative-sequence input voltage V _R +ΔV _F , and the positive-sequence output voltage 405
V _P and the negative phase output voltage 406V _N are given a DC offset equal to the maximum value v^p of the positive phase output signal.

As is clear from FIG. 4, the differential amplifier circuit according to the present invention can make the most effective use of the linear portion of the transfer characteristic of the differential amplifier circuit when amplifying a single-polarity signal, resulting in a signal with less distortion. It becomes possible to perform amplification.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the differential offset voltage of the differential amplifier circuit, FIG. 2 is a diagram showing an embodiment of the maximum value detection circuit, and FIG. 3 is a diagram showing the configuration of the differential amplifier circuit according to the present invention. FIG. 4 is a diagram illustrating the differential offset voltage of the differential amplifier circuit according to the present invention. In the figure, 201-203...transistor, 204-206...resistor, 207...capacitor, 301...direct-coupled differential amplifier circuit, 30
2,303...detection circuit, 304...difference circuit.

Claims (1)

[Claims] 1 a differential amplifier comprising a positive phase input terminal that receives an input signal, a negative phase input terminal to which a reference voltage is applied, a positive phase output terminal, and a negative phase output terminal; a first differential amplifier connected to the positive phase output terminal; an amplitude detector, a second amplitude detector connected to the negative phase output terminal, and a first input terminal receiving the output of the first amplitude detector, and an output of the second amplitude detector. a difference detection circuit which receives at a second input terminal and obtains an output corresponding to the difference between the outputs of the first and second amplitude detectors at an output terminal; and the output terminal of the difference detection circuit is connected to the negative phase input terminal. and means for controlling an offset voltage of the differential amplifier.