JPH0315865B2 - - Google Patents

Description

Detailed Description of the Invention Technical Field The present invention is a memory switch type that performs parallel switching after storing data over multiple frames on a time division multiplex line that multiplexes data from terminals having various communication speeds. This paper relates to a parallel memory switch system for a time division converter.

Prior Art A conventional memory switch type data exchange system has a buffer memory for storing one frame of subscriber data between an input highway and an output highway, and has a clock synchronized with the highway data, a counter for counting this data, and a buffer memory for storing subscriber data for one frame. The data on the ingress/egress highway is converted by replacing the subscriber data stored in the buffer memory with an operation from the memory that holds the address. FIG. 1 is a block diagram showing an example of a conventional memory switch system. The channels transmitted on multiplex transmission paths 100 and 101 are typically in the form of octets, each consisting of a set of 8 consecutive bits. First, 8-bit data from the input multiplex transmission line 100 is written to an address of the buffer memory 105 determined by the instruction content of the time slot counter 102, which is synchronized with the phase of the time-division multiplexed data on the transmission line. The written data is read out according to the address pointed to by the holding memory 104 accessed by the time slot counter 103 which operates in synchronization with the local clock, thereby realizing a conversion operation. In this basic memory switch type communication path, holding memory 10
Regarding No. 4, the operating speed can be reduced by using the bank division method, but in the case of the buffer memory 105, even if the bank division method is used, the operating speed can only be reduced by 1/2 at most. In general, the operating speed is required to be high-speed operation proportional to the speed of the multiplex transmission line 100, and the operating cycle time must be increased in proportion to the increase in the number of accommodated terminals and the number of accommodated high-speed terminals. Shortcomings have long been pointed out.
On the other hand, as a method of reducing the operating speed of the buffer memory, FIG. 2 shows a method that has been tried in the past in the general case of accommodating a plurality of multiple highways. In Fig. 2, multiplex transmission line 2
Each time slot multiplexed into 00 and 201 is in the form of an octet consisting of a set of 8 consecutive bits. First, the 8-bit signal from the input multiplex transmission line 200 is converted from serial format to parallel format by the serial/parallel conversion circuit 202 in order to reduce the operating speed of the switch, and then the parallel signals from each transmission line are converted by the multiplexer 204. , are multiplexed into an 8-bit wide input highway 205, and then converted into an 8-bit width in a buffer memory 207.
The converted signal is periodically distributed to each output multiplex transmission path by the demultiplexer 210, and further converted from parallel format to serial format by the parallel/serial conversion section 203.
After being converted, it is sent out to the outgoing multiplex transmission path 201. In the exchange operation, as in the case of FIG. 1, data is written to the address of the buffer memory 207 determined by the instruction content of the time slot counter 206 synchronized with the phase of the data on the transmission path, and the written data is This can be achieved by reading out according to the address specified by the holding memory 208, which is accessed in synchronization with the local clock. By the way, even in the memory switch method shown in FIG. 2, when a large number of high-speed terminals are accommodated in the converter, or when the converter accommodation scale becomes large, the data signal speed of the input/output multiplex highways 205 and 209 becomes large. In this case, it becomes necessary to increase the speed of the buffer memory 207 in proportion to its operating speed. In recent years, the demand for high-speed data communication terminals has increased, and the operating speed of memory cannot keep up with the demand trend.In view of this situation, technology has been developed to reduce the operating speed of buffer memory. There has been a desire for an exchange system that can convert data from a large number of medium-speed to high-speed terminals by providing a means for converting data from a large number of medium-speed to high-speed terminals.

Purpose of the Invention The present invention provides a system that can reduce the operating speed of a buffer memory in a memory switch communication path section, and enables data exchange on a multiplexed transmission path assuming the coexistence of a plurality of multiplexed speed series. be.

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a two-sided buffer memory for storing data on a multiplex transmission path over a plurality of frames and access to the buffer memory at the front stage of a conventional memory switch communication path. By reading terminal data over a plurality of frames in parallel from the buffer memory, parallel memory switching is performed, and the operating speed of the buffer memory in the memory switch channel section is eased.

Structure and operation of the invention The present invention will be described in detail below along with examples.

FIG. 3 shows the configuration of an embodiment for realizing the parallel memory switching method of the present invention. 300 is an incoming super multiplex highway, 300' is an outgoing super multiplex highway, 301 is a serial/parallel conversion circuit for octet data on the incoming multiplex transmission path, 302
is a parallel-to-serial conversion circuit for 8-bit parallel octet data; 303 is a buffer memory in the input direction (two-sided configuration); 304 is a buffer memory in the output direction (two-sided configuration); 305 is a holding memory for controlling the writing of the buffer memory 303; 306 is a holding memory 305
Arithmetic circuit for updating read information of 307
308 is a holding memory for controlling reading of the buffer memory 304 in the outgoing direction; 309 is an arithmetic circuit for updating read information of the holding memory 308; 310 is a buffer memory 304; 311 is a selector circuit for selecting the output of the buffer memory 303 in the input direction, 312 is a selector circuit for selecting the output of the buffer memory 304 in the output direction, and 313 is a replacement circuit. A time slot counter 314 designates a write address of the buffer memory 315, a holding memory 314 designates a read address of the buffer memory 315, and constitutes an n-bit parallel memory switch A. In Figure 3,
The octet data on the input multiplex transmission path is converted into 8-bit parallel data by a serial/parallel conversion circuit 301, and then transferred to a buffer memory 303 indicated by a holding memory 305.
A write is performed to the address. On the other hand, the buffer memory 303 has a two-sided configuration, and sequential reading from the buffer memory on the other side, where the above-mentioned 8-bit parallel data is not written, is performed based on the address indicated by the time slot counter 307. It will be done. For example, when 64-bit parallel switching is performed in the buffer memory 315, the planes of the buffer memory are switched every 8 frames. Arithmetic circuit 3
06 performs an operation to update the address value for writing 8-bit parallel data to the buffer memory 303. In a procedure completely opposite to these operations, multi-bit (for example, 64-bit parallel) data read from the buffer memory 315 by the switching operation is written to the address indicated by the time slot counter 310 in the buffer memory 304, and is also transferred to the output line. In the read operation, the data at the address specified by the holding memory 308 is transferred to the buffer memory 30.
This is realized by reading from 4. The incoming super-multiplex highway 300 shows the 64-bit parallel bus before conversion, and the outgoing super-multiplex highway 300' shows the 64-bit parallel bus after the conversion. The buffer memory 304 on the output side also has a two-sided structure, and the switching between the planes is performed in units of eight data frames, similar to the buffer memory on the input side.

FIG. 4 shows data multiplexing in which octet data serially bit-multiplexed on the input multiplex transmission line 100 is channel-converted in the buffer memory 315 for parallel switching, and is read out to the output multiplex transmission line 101. This shows the process of change in format. The data bit string on the input multiplex transmission path is stored in the input buffer memory 303 over eight data frames and read out in 64-bit parallel units. Therefore,
The interval between bit sequences on the ingress super multiplex highway 300 has a time width 64 times as long as the interval between bit sequences on the ingress multiplex highway 100.

Exit super multiplex highway 30 in Figure 4
The data above 0' indicates the state after being exchanged in the buffer memory 315 in 64-bit parallel units. FIG. 5 shows an implementation means for controlling the writing of data into the buffer memory on the input side through the operations of the holding memory 305 and the arithmetic circuit 306. In Figure 5, the multiplex transmission path is assumed to be, for example, 128 channel multiplex,
High-speed terminal data is transmitted through the sixth transmission line on the multiplex transmission path.
As shown in the figure, the assumption is that time slots are secured periodically. In Figure 6, a total of 128 time slots from #0 to #127 are divided into one time slot.
The time slots #0 and #64 are used as channels for double calls (equally spaced), and the time slots #1, #33, #65, and #97 are used as channels for quadruple calls. An example of a multiplexing format is shown in which one time slot is used as a channel (equally spaced) and the other time slots are used for basic calls (one time slot corresponds to one channel). basic call
If it is a 64Kb/s channel, the 2x call and 4x call will be 128Kb/s and 256Kb/s, respectively.

The operation in Figure 5 is shown in Figures 3, 6, 7, and 8.
This will be explained in detail using figures. Holding memory 30
5, if one frame consists of 128 time slots, it consists of 128 words, and each word is
It is divided into three types of fields 1F to 3F. The first field 1F indicates the address when accessing the buffer memory 303, and the second field 2F indicates each block number when the buffer memory 303 is composed of 8 blocks #0 to #7, for example. Instruct, 3rd field
3F indicates the speed type of the data signal to be multiplexed within one frame ('m' is displayed in the case of an m-times speed call). The write address of the transmission line data in the buffer memory 303 (horizontal address number and vertical block type number of the buffer memory 303 shown in FIG. 8) is read from the holding memory 305 which operates in synchronization with the transmission line clock. Determined based on address. The third field 3F in the holding memory 305 indicates the speed of each channel on the multiplex transmission path, and is initialized by soft order.

Further, regarding the first and second fields 1F and 2F, the information is updated by the arithmetic circuit 306 immediately after the read cycle of the holding memory 305,
The updated information is written to the same address of the holding memory 305 as the read address.
The seventh example shows how the operation cycle of the holding memory 305 is used.
As shown in the figure. The A cycle and the C cycle are read and write cycles for the above-mentioned holding memory 305, respectively, and the B cycle is a soft access cycle. In the B cycle, the holding memory 30
Maintenance readout of 5 and retention memory 3 based on call processing
It is normally used for initial setting of 05 or for writing at the time of call setup. Also in the figure, t indicates the execution processing time by the arithmetic circuit 306.

FIG. 8 shows that using the arithmetic circuit shown in FIG.
The data on the incoming multiplex transmission path carried in each time slot shown in FIG. 6 is transferred to the incoming buffer memory 3.
This figure shows how data is written to each address of 03 in 8-bit units.

In each stage of () to () in Figure 8,
() to () indicate writing of the first frame, the first stage of () indicates writing from channel 0 to channel 63, and the second stage of () indicates writing from channel 64 to channel 96. ()
The third stage shows writing from 97 channels to 127 channels. The 4th stage in () indicates writing from channel 0 to frame 127 of the 1st and 2nd frames, and the 5th stage in () indicates writing from channel 0 to 127 of the 1st frame to channel 0 → 127 of the 8th frame. Indicates writing.

Input buffer memory 3 shown at each stage in Figure 8
The numbers in 03 correspond to each time slot number on the input multiplex transmission line 100.

As shown in the figure, for high speed calls such as double speed calls and quadruple speed calls, a buffer area proportional to the speed increase is secured on the ingress buffer memory 303. Furthermore, when data on the transmission path stored in the input buffer memory 303 is written to the buffer memory 315, the parallel reading of 64-bit data from the buffer memory 303 is controlled so that the data from the same terminal are aligned in the same phase. (This can be realized by the order in which the transmission path data is written to 303 in the first to fifth stages () to ()). buffer memory 30
3 has finished storing all the data on the transmission line for 8 data frames (step 5), 303
Writing of transmission line data to the other side of the buffer memory 303 is started, and at the same time, the time slot counter 307 sequentially reads data from the side of the buffer memory 303 on which the transmission line data has already been stored. This is done in bit parallel units. FIG. 9 shows a method of transitioning the contents of the holding memory 305 when writing transmission line data to each address of the buffer memory 303 shown in FIG. 8.

In FIGS. 8 and 9, in time slots #0 to #127 in one data frame,
#0 time slot is double speed call (therefore, if periodic arrangement is assumed, #64 time slot is also
Used for the call. ), time slot #1 is allocated for a quadruple speed call (therefore, if periodic allocation is assumed, time slots #33, #65, and #97 are also used for this call). This shows the case where

The holding memory for inlet buffer control in FIG. 9 is 3
The first field 1F shows the content corresponding to the horizontal address (0 to 127) of the input buffer in FIG.
The second field 2F is the vertical address of the input buffer in Figure 8 (block types #0 to #7).
Indicates the content corresponding to. Further, 3F indicates the content corresponding to the type of double speed call. In FIG. 9, (a) is the initial state, (b) is after one frame (after the time slot counter moves from 0 to 127), (c) is after two frames, (d) is after four frames, (e) shows the state after 6 frames. Taking the case of a double-speed call as an example, the 0 address of the ingress buffer control holding memory 305 in the initial state shown in FIG. 9 contains '0' in the first field 1F, '0' in the second field 2F, 3rd field
'2' is stored in the 3F, and the data carried in the #0 time slot is stored in the input buffer memory 303 at (horizontal address, vertical block type) = (0,
0) indicates that it is a double speed call stored in the buffer address. The contents of the 0 address of 305 are:
Once read, the input buffer control arithmetic circuit 306 in FIG. 3 sets the contents to (horizontal address, vertical block type) = (0, 2), and adds +2 to the vertical block type number. Ru. As a result, preparations for storing the data carried in the #0 time slot of the next data frame into the buffer memory 303 are completed. On the other hand, the address 64 of the ingress buffer control holding memory 305 contains the first field.
0 is stored in 1F, 1 is stored in 2nd field 2F, and 2 is stored in 3rd field 3F, and the data carried by time slot #64 is 303 (horizontal address, vertical block type) = (0, 1). This indicates that the call is a double speed call stored in the buffer address. The data in the first and second fields 1F and 2F stored at this address 64 are changed into (horizontal address, vertical block type) = (0, 3) by the input side buffer control arithmetic circuit 306. Updated. That is, the vertical block type number is incremented by +2, and preparations are made for storing the data carried in time slot #64 of the next data frame. 2
Holding memory 3 for incoming buffer control in case of double speed call
The transition from the initial state of 05 and the method of writing data from the first to third frames are as described above. The method of updating the contents of the address in the ingress buffer control holding memory 305 is as shown in FIG.
'64' in 1st field 1F, 2nd field 2F
It is necessary to operate the incoming buffer control arithmetic circuit 306 so that '0' is stored in the input buffer. After this, the content of the second field 2F is added by +2 until the data of the eighth data frame is received. . After receiving the data of the eighth data frame, the contents of the first and second fields 1F and 2F are returned to their initial states. The same method as for double speed calls can be applied to quadruple speed calls as well.

In the initial state as shown in FIG. 3F) values are (1, 0, 4), (1, 1, 4), (1, 2, 4), respectively.
(1, 3, 4) are stored, and as shown in FIG. 9, in order to control writing to the incoming buffer memory 303, the contents of each address are stored in 8 data frames after receiving 1 data frame. The transition is as follows until after reception.

Content transition of #1 address of 303 (1, 0, 4) → (1, 4, 4) → (33, 0,
4) → (33, 4, 4) → (65, 0, 4) → (65,
4,4) (97,0,4) → (97,4,4) → (1,
0, 4) = initial state Content transition of #33 address of 303 (1, 1, 4) → (1, 5, 4) → (33, 1,
4) → (33, 5, 4) → (65, 1, 4) → (65,
5, 4) → (97, 1, 4) → (97, 5, 4) →
(1, 1, 4) = initial state 303 #65 address content transition (1, 2, 4) → (1, 6, 4) → (33, 2,
4) → (33, 6, 4) → (65, 2, 4) → (65,
6, 4) → (97, 2, 4) → (97, 6, 4) →
(1, 2, 4) = initial state 303 #97 address content transition (1, 3, 4) → (1, 7, 4) → (33, 3,
4) → (33, 7, 4) → (65, 3, 4) → (65,
7, 4) → (97, 3, 4) → (97, 7, 4) →
(1, 3, 4) = initial state Generally, in the case of n times speed calls, parallel switching can be realized using the same method. Next, the specific operation of the incoming buffer control arithmetic circuit 306 for updating the read contents of the incoming buffer control holding memory 305 described above will be described with reference to FIG.

In Figure 5, 5051, 5052, 505
3 is +4 addition, +2 addition, + of mod8, respectively.
This is a 1 addition circuit. The decoder 504 selects the +4 adder circuit (mod8) 5051 in the case of a quadruple speed call, selects the +2 adder circuit (mod8) 5052 in the case of a double speed call, and selects the +2 adder circuit (mod8) 5052 in the case of a basic call. +1 adder circuit is selected. Each of these adder circuits performs a mod8 operation when the buffer memory 303 consists of 8 blocks, and generally performs a modn operation when the incoming buffer memory 303 consists of n blocks.

In the case of a double speed call, the number 64 indication circuit (2
When the number 32 (binary) 503 is a quadruple speed call, the decoder 504 selects an indicator circuit (binary) 502 with a numerical value of 32. For mx speed calls where one data frame consists of 128 time slots, the value is
A 128/m indicator circuit is required. (Generally, in the case of a multiplexed transmission path where one frame consists of N time slots, an instruction circuit with the numerical value 'N'/m is required.) Except for basic calls, double calls, quadruple calls, In the case of a high-speed call such as a call, when an added value of 8 or more is obtained from the adder circuits 5051 and 5052, the overflow detection circuit 508 detects it, and the AND logic circuit 507 Accordingly, the value of the instruction circuit 502 or 503 is
It is selected and input to adder circuit 506. The addition circuit 506 receives the above instruction value and the holding memory 30.
5 and the address value of the first field using mod128, and the addition result is written to the corresponding address in the holding memory 305. As a result, as shown in FIG.
The first and second fields of No. 5 are updated.

Further, an output side buffer control holding memory 308 for controlling the output side buffer memory 304;
The output side buffer control arithmetic circuit 309 also needs to be configured to perform the same operation as the input side control circuits 305 and 306.

In the examples shown in Figures 5 to 9 described above, it is assumed that one data frame is composed of 128 time slots, 8 data frames are accumulated, and a readout output with a parallel width of 64 bits is obtained. However, these values are not limited to the values mentioned above. In addition, in the above example, double call,
Although we have dealt with the example of a double-speed call with a quadruple-speed call, this value can also be easily expanded, and can generally be handled in the same way even when M-times speed calls are mixed.

On the other hand, in the configuration of FIG. 3, the buffer memory 303 on the input side and the buffer memory 30 on the output side
Holding memories 305, 30 for controlling 4
8. Although a configuration example in which the arithmetic circuits 306 and 309 are provided independently has been shown, these can be integrated as shown in FIG.

Reference numerals 400, 401, and 402 indicate an arithmetic circuit for input/output control, a time slot counter, and a holding memory, respectively. These circuits are controlled to operate in synchronization with the phases on the input and output transmission paths.

In addition, in the explanation so far, for double-speed calls with high-speed channels, as shown in FIG.
Although a case has been described in which a plurality of time slots are occupied at equal intervals within a data frame, this assumption does not limit the method of application of the present invention.
For example, as shown in Fig. 11, when the multiplexing method on the transmission path is a double-speed call (2x, 4x, etc.), multiple time slots are consecutively secured within one data frame. There are possible ways. For example, in the case of a basic call, among channels 0 to 127,
If only one channel is used, and if it is a double call, two channels will be used consecutively, for example, channels 0, 1, and if it is a quadruple call, for example, channels 2, 3, etc.
Four channels are used consecutively, such as channels 4 and 5. In the case of this multiplexed configuration, as shown in FIG. 12, addresses corresponding to each time slot of the incoming buffer control holding memory are used to control writing of transmission line data to the incoming buffer memory 303. It is necessary to update the contents of . FIG. 13 shows the process of transition of the contents of the incoming buffer control holding memory 305' in this multiplexed configuration. 1st field ~ 3rd field 1F
The meaning of the contents of ~3F is the same as that shown in FIG. The fourth field 4F is a newly added field, and this field is a field in which double-speed call data is stored in the incoming buffer memory 30.
This field is used to count how many columns are stored at different addresses in the horizontal direction in the buffer area above 3, and is used for various controls (see FIG. 14 for details).

In FIG. 12, the input buffer memory () indicates the writing of the first data frame, and
The No. 1 shows the writing of the 1st and 22nd data frames,
() indicates the write operation of the first to fourth data frames, and () indicates the write operation of the first to eighth data frames. In addition, in FIG. 13, (a) of the ingress buffer control holding memory 305' is in the initial state, (b) is after one frame, (c) is after two frames, (d) is after four frames,
(e) shows each state after 6 frames.

An input side buffer control arithmetic circuit 30 for controlling the input side buffer memory and the input side buffer control holding memory as shown in FIGS. 12 and 13.
The configuration and operation of 6' will be explained below using FIG.

In the holding memory 305', the first to third fields 1F to 3F are similar to the above, with the first field 1F indicating the content corresponding to the horizontal address of the input buffer, and the second field 2F indicating the content corresponding to the horizontal address of the input buffer. It shows the contents corresponding to the vertical address (block type), and 3F shows the contents corresponding to the double speed call type. The fourth field 4F added to the holding memory 305' is stored in the overflow at 508 (addition circuit at 5051, addition circuit at 5052).
(If the addition result of the addition circuit is 8 or more), it is used to store the counting result of the number of detections.

If overflow detection is not performed in 508, +1 addition circuit 5060 and subtraction circuit 5061
does not perform subtraction, the input value is passed through, and 30
The same content as the read content is written to the addresses of the first and fourth fields of 5' (the second field is updated every time it is accessed).

On the other hand, if overflow detection is performed in step 508, +1 is added to the value of the fourth field 305' in step 5072. The coincidence detection circuit of 5071 detects that the result of this +1 addition is 2 in the case of a double call, and 4 in the case of a 4 times call. The content of the address is limited to 0. In addition, when the above-mentioned coincidence detection occurs, '2', '2',
Specify '4' and input it to the 5061 subtraction circuit. The subtraction circuit of 5061 is (number of 5064) -
(Number of 5063)+1 is subtracted. If the +1 addition result of 5072 does not become a value of 2 or 4 in the case of a double call or a quadruple call, respectively,
The calculation result of 5072 is written to the corresponding address of the fourth field of 305'. Although the operation has been described above in the case where double calls and quadruple calls coexist, the same circuit can generally handle the case where P multiple calls are included.

Effects of the Invention As explained above, in order to perform parallel switching on the communication path of an exchange, a buffer memory for storing a plurality of frames, a holding memory for controlling the buffer memory, an arithmetic circuit, etc. are used to perform switching operations. By providing the switch before and after the communication path section, the operating speed of the switch can be significantly reduced, and data on the multiplex transmission path can be exchanged on the assumption that a plurality of multiplex speed sequences coexist.

As described in Japanese Patent Application No. 58-140764 "Time-division line channel selection system", the present invention combines a plurality of empty channels from among the channels arranged periodically for each speed class on a multiplex line. Accordingly, the present invention is similarly applicable to a case where a multiplexing configuration is adopted that allows arbitrary band allocation on a transmission path, and the present invention is not limited to the above embodiments, but also includes the claims. Various changes can be made within the range described in the range.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional memory switch method, FIG. 2 is a block diagram showing a method for reducing the operating speed of a conventional buffer memory, and FIG. 3 is an embodiment of the parallel memory switch method of the present invention. 4 is a diagram showing an example of the transition process of the data multiplexing format in the present invention, and FIG. 5 is a diagram showing an example of the transition process of the data multiplexing format in the present invention. FIG. 6 is a configuration diagram of a data frame showing a case in which a time slot is periodically secured for high-speed terminal data, and FIG. FIG. 8 is a diagram showing an example of how the operation cycle is used. FIG. 8 is a diagram showing how data on the incoming multiplex transmission path is written in units of 8 bits to each address of the incoming buffer memory 303 in an embodiment of the present invention. Figure 9 shows the 8th
FIG. 10 is a diagram showing a method of transitioning the contents of the holding memory 305 when writing transmission line data to each address of the buffer memory 303 shown in the figure, and FIG. 10 shows another embodiment of the parallel memory switch system of the present invention. FIG. 11 is a data frame configuration diagram showing another multiplexing method to which the present invention is applied.
2 is a diagram showing the write control of transmission line data to the input side buffer memory 303 in the case of the multiplex configuration shown in FIG. 11, and FIG. 13 is a diagram showing the holding memory for input side buffer control in the case of the multiplex configuration shown in FIG. 11. FIG. 14 is a diagram showing the transition process of the contents of 305', and FIG. 14 is an arithmetic circuit for controlling the incoming buffer memory for controlling the incoming buffer memory and the holding memory for controlling the incoming buffer as shown in FIGS. 12 and 13. Diagram showing. 100... (in) multiplex transmission line, 101...
(Output) Multiplex transmission line, 102...Time slot counter, 103...Time slot counter, 1
04...Holding memory, 105...(data) buffer memory, 200...(input) multiplex transmission path, 20
1...(output) multiplex transmission line, 202...serial-parallel conversion circuit, 203...parallel-serial conversion circuit, 204...multiplexer (multiplexer), 205...(in)
Multiplexing highway, 206... Time slot counter, 207... (data) buffer memory (8-bit parallel), 208... Holding memory, 209
... (output) multiplex highway, 210 ... separation circuit (demultiplexer), 300 ... (input side) super multiplex highway, 300' ... (output side) super multiplex highway, 301 ... serial-parallel conversion circuit, 302... Parallel/serial conversion circuit, 303... (input side) buffer memory, 304... (output side) buffer memory, 305... (for input side buffer control) holding memory, 305'... (for input side buffer control)
Holding memory, 306... (for input buffer control)
Arithmetic circuit, 306'... (for input side buffer control)
Arithmetic circuit, 307...time slot counter,
308... (for output buffer control) holding memory,
309... (for output buffer control) arithmetic circuit, 3
10...Time slot counter, 311...Selector circuit, 312...Selector circuit, 313...
...Time slot counter, 314...Holding memory (for switching control), 315...Buffer (for parallel switching), 400...Arithmetic circuit,
401...Time slot counter, 402...
Holding memory, 501...decoder (for write block instruction), 502...'32' instruction circuit, 50
3...'64' instruction circuit, 504...decoder, 5
051...+4 addition circuit, 5052...+2 addition circuit, 5053...+1 addition circuit, 506...
Addition circuit of MOD128, 507...AND logic circuit, 508...Overflow detection circuit, 506
0...+1 addition circuit, 5061...subtraction circuit, 5
071...Coincidence detection circuit, 5072...+1 addition circuit, 5073...2 designation circuit, 5074...'
4' designated circuit, 5075...AND logic circuit.

Claims (1)

[Claims] 1. Equipped with a buffer memory for storing data and a holding memory for storing an access address to the buffer memory, and converts data carried in a time slot on an input multiplex transmission path into data carried in an arbitrary time slot on an output multiplex transmission line. In the memory switch method, the buffer memory for storing data for a plurality of frames further includes a second holding memory for controlling the buffer memory for storing data for a plurality of frames, and an arithmetic control unit for updating the contents of the second holding memory. , and accumulates basic speed data given one time slot in one frame and high speed data given multiple time slots in one frame over multiple frames on the input multiplex transmission path. , a parallel memory switch method characterized in that the accumulated data is switched in parallel at once.