JPH0316808B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL suitable for application to a jumping correction circuit used in a reproduction system of a VTR.

This jumping correction circuit is a circuit for correcting discontinuity of horizontal synchronizing pulses occurring between tracks during variable speed reproduction, and the one shown in FIG. 1 is a 0.5H jumping correction circuit.

In the figure, reference numeral 1 denotes a switching circuit, and this circuit 1 receives the reproduced video signal S _i supplied to the terminal 2 and the reproduced video signal S _i by delay element 3 for 0.5H.
A playback video signal S id delayed by S _id is provided,
When 0.5H jumping occurs, the discontinuity of the horizontal synchronizing pulse is corrected by switching as shown in the figure and outputting the reproduced video signal S _id .

Since a glass delay line or the like is used as the delay element 3, a signal converted into a high frequency signal is used as the reproduced video signal S _i . Therefore, an AM modulator 4 is provided as shown in the figure, and the carrier Po from the carrier generator 10 (the frequency of which is, for example, three times the subcarrier frequency sc is used) is modulated by the AM modulator 4 by the reproduced video signal S _i . Modulated. Therefore, a demodulation circuit 6 is provided after the delay element 3.

By the way, as the carrier generator (tripler) 10 for obtaining the AM carrier Po, a PLL configuration is used to form the AM carrier Po locked to the subcarrier of the reproduced video signal S _i . As shown in FIG. 2, the PLL used as the carrier generator 10 includes a variable oscillator 11 that oscillates at a frequency 3sc that is triple the subcarrier frequency sc, a 1/3 frequency divider 12, an input subcarrier S _B , and a phase It is composed of a phase comparator 13 for comparison and a low-pass filter 14 for smoothing the phase comparison output.

This is a well-known configuration, but since the circuit configuration of the frequency divider 12 in this PLL 10 is relatively complicated, even when converting it into an IC, the frequency divider 12
There is a demand to eliminate as much as possible. If the frequency divider 12 is omitted, the AM carrier Po, which is the oscillation output of the VCO 11, is directly supplied to the phase comparator 13 as shown in Figure 3.
Contains unnecessary ingredients. These unnecessary ingredients
In order to prevent the signal from being fed back to the VCO 11, it is necessary to make the value of the capacitor C that constitutes the low-pass filter 14 sufficiently large.

However, when doing this, the capture range L _P of PLL10 (see Figure 4) becomes extremely narrow.
It becomes impossible to absorb frequency fluctuations due to variations in the VCO 11 itself and temperature drift.

Therefore, in the present invention, even if a large capacitor C is used in order to omit the 1/3 frequency divider 12, the apparent capture range can be expanded. Furthermore, in this invention, by omitting the 1/3 frequency divider 12,
This is designed to reliably prevent PLL mislock.

Next, a case in which an example of the present invention is applied to the carrier generator of the above-mentioned jumping correction circuit will be described with reference to FIG. 5 and subsequent figures.

In this invention, as shown in FIG. 5, a current control circuit 20 for controlling charging and discharging of the capacitor C is provided between the phase comparator 13 and the VCC 11. The current control circuit 20 is composed of a pair of current sources 21 and 22 that are controlled in a switching manner and a Schmitt circuit 24 that controls these current sources 21 and 22. It operates by the control voltage Vc applied to the VCO 11.

FIG. 6 is a specific example of the main part, and the phase comparator 13 is composed of three differential amplifiers 25 to 27 as shown in the figure.
An input subcarrier S _B is supplied to a terminal 28, and an AM carrier Po, which is a VCO output, is supplied to a terminal 29. The phase comparison output is converted to a predetermined current by the current conversion circuit 30.
Converted to I _I and I _J.

Note that the phase comparator 13 includes a pair of resistors R _a ,
A low pass filter 31 composed of R _b and a capacitor C _a is connected.

The current conversion circuit 30 is composed of a pair of emitter-coupled transistors Q _a and Q _b as shown in the figure, and each collector is connected to a constant current source 32 . This current source 32 is configured as a current mirror, so that the converted current I I flows into the transistor Q _c and the corresponding current I _I flows into the other transistor Q _d , which in this example is the same current I _I
is made to flow.

The current that is the difference between the conversion currents I _J and I _I is supplied to the capacitor C as an output corresponding to the phase comparison output, but
The sum current (I _J +I _I ) is constant and its values are complementary. Therefore, I _J and I _I have the following relationship: I _I =xK (1) I _J = (1-x)K (2) {|x|<1 K: constant}.

The Schmitt circuit 24 has first and second threshold levels V _H , V _L (V _H >V _L ),
These levels V _H and V _L both correspond to the control voltage V _c outside the capture range.

Constant current sources 21 and 22 are connected in series, and
One current source 21 operates as a charging source for capacitor C, and the other current source 22 operates as a charging source for capacitor C.
connected to operate as a discharge source for the The respective current values I ⁺ _S and I ^- _S are equal, I ⁺ _S = I ^- _S ≒ 1/2
I _I = 1/2 I _J is selected.

Switching means 35 and 36 are connected in series to the current sources 21 and 22, respectively, and these are controlled by the output S _s of the Schmitt circuit 24.

That is, when charging the capacitor C, the upper switching means 35 is turned on and the lower switching means 36 is turned off, so that the control voltage _Vc is controlled by the Schmitt output _Ss to the first threshold level _VH. When the voltage exceeds the threshold level, the upper switching means 35 is turned off and the lower switching means 36 is turned on, and due to the discharge, the control voltage _Vc reaches the second threshold level.
When the voltage falls below V _L , switching control opposite to that described above will be performed.

Next, the retracting operation and the like in this invention will be explained with reference to FIGS. 7 and 8.

First, when the terminal voltage of the capacitor C, and thus the control voltage _Vc , is zero, as when the power is turned on, only the switching means 35 is on, so that a constant current is generated.
The capacitor _C is charged by I ⁺ _S (Fig. 7B), and the control voltage V _c rises accordingly (Fig. 7A).
oscillation frequency increases. On the other hand, in the phase comparator 13, since the input burst carrier S _B and the oscillation output Po are different, its output terminal 33a,
33b, phase comparison outputs are obtained alternately, and due to the presence of the low-pass filter 31, transistors Q _a and Q _b are both turned on, and currents I _I and I _J related to the phase comparison outputs are obtained.

The magnitudes of the currents I _I and I _J change alternately, so that the sixth
A charging/discharging control current (pull-in current) i _PD that charges the capacitor C through the signal line l in the figure or discharges it from the capacitor C to the current source 32 side,
That is, i _PD =I _J -I _I (3) Since charging and discharging are repeated alternately, the average value of this current i _PD becomes zero (Fig. 7C).

For this reason, the capacitor C is connected until the oscillation frequency of VCO11 enters the capture range.
is charged by a constant current I ⁺ _S. The charging/discharging current i _C (=I ⁺ _S + i _PD ) for the capacitor C is shown in FIG. 7D.

When the oscillation frequency approaches the center frequency 3sc, in this example, I _I of the converted current gradually becomes larger than I _J , and after changing to i _PD = I _J −I _I <0, further i _PD = −I ⁺ _S (4) When the charging/discharging current i _C of the capacitor C becomes zero, the control voltage V _c maintains the value when i _PD =−I ⁺ _S. In other words, it enters a locked-in state.

Contrary to the above, when the oscillation frequency changes from the higher side and locks in, only the lower switching means 36 is turned on and the charge in the capacitor C is transferred to the current source 2.
2, the control voltage V _c drops and the oscillation frequency decreases (FIGS. 8A and 8B). As in the previous case, the average value of the current i _PD until lock-in is zero (C in the same figure).

When the oscillation frequency approaches the center frequency 3sc, I _J of the converted current gradually becomes larger than I _I , and after changing to i _PD = I _J − I _I > 0, i _PD = +I ⁻ _S ...(5) When the charging/discharging current i _C of the capacitor C (=
i _PD +I ^- _S ) becomes zero (D in the same figure), and the control voltage V _c maintains the value when i _PD =+I ^- _S , as described above, and enters the lock-in state.

By the way, when the PLL 10 is configured by omitting the 1/3 frequency divider as described above, the VCO 11 locks in at each frequency of N/M·sc (M and N are integers). When applied to the jumping correction circuit shown in FIG. 1, all cases other than M=3 and N=9 result in mislock. Figures 9 and below are designed to prevent this mislock.

Figure 9 is an example of this, in which a ceramic filter 4 with a passband of 3sc is used at the output stage of the VCO 11.
0 is provided, and its output P _CF is used as an AM carrier, and this filter output P _CF is supplied to a peak hold circuit 42 via an amplifier 41, and the level of the hold output is determined by a level comparison circuit 43. Ru. The reference level is selected to be such that when the filter output _PCF of 3sc is obtained, the discrimination output _PD is obtained. When the discrimination output P _D is obtained, a switch 44 provided after the Schmitt circuit 24 is turned off.

When switch 44 is turned off, current sources 21 and 22 are both controlled to be floating relative to capacitor C.
For this purpose, switching means 35 and 36 may be provided as shown in FIG. 6, and both of them may be opened (off).

Therefore, if the current values I ⁺ _S and I ^- _S of the current sources 21 and 22 are selected to be relatively large, the frequency will be swept as it is even at the frequency at which a mislock occurs, so that N/M can be changed as before. There is no possibility of mislock occurring at each point of the double.

When the oscillation frequency is swept to the desired frequency, the switch 44 is switched by the discrimination output P _D from the filter output P _CF at that time.
Since both current sources 21 and 22 are in a floating state, the charging and discharging of the capacitor C is performed by the converted current I _I ,
Performed only by _IJ . When the lock is released, the switch 44 is turned on again, so there is no problem with PLL operation.

FIG. 10 shows another example of preventing mislock. In the case of FIG. 9, if the capture range of the PLL is narrower than the passband of the ceramic filter 40, lock-in may not occur even if the filter output _PCF is obtained. The PLL's capture range must be wider than the passband of the PLL.

FIG. 10 omits this restriction. In this embodiment, in addition to the first and second current sources 21 and 22, third and fourth current sources 46 and 4 are connected in parallel with these.
7 is connected, and the first and third current sources 21 and 46 and the second and fourth current sources 22 and 47 are connected to the switch 49.
and the third and fourth current sources 46,
Switches 51 and 52 are connected in series to 47, respectively, and these are controlled simultaneously by the discrimination output P _D.

Here, when the charge/discharge control current i _PD is set to ±1.0 mA, the first and second currents I ⁺ ₁ and I ^- ₁ are selected to be 0.5 mA, and the third and fourth currents I ⁺ ₂ , I ^- ₂ is 3.0mA
selected according to degree.

When the discrimination output P _D cannot be obtained, the first and third
The current I ⁺ ₁ , the combined current of I ⁺ ₂ , and the second and fourth currents
Since the control voltage V _c is changed by the combined current of I ^- ₁ and I ^- ₂ , the charge/discharge control current at lock-in
i Controlled by a much higher current than _{the PD} .
Therefore, due to voltage control using these combined currents, the control voltage V _c changes beyond the mislock point. When N/M approaches 3, the discrimination output P _D is obtained and the third and fourth currents I ⁺ ₂ and I ^- ₂ are opened. i _PD > I ⁺ ₁ , I ^- ₁
Therefore, the lock-in operation is performed by these currents I ⁺ ₁ and I ^- ₁ .

If you do this, the ceramic filter 40
Even if the capture range is narrower than the pass band of , the lock-in operation is performed by the first and second currents I ⁺ ₁ and I ^- ₁ , so the conditions shown in FIG. 9 are not necessary.

As explained above, according to the present invention, the 1/3 frequency divider 12 can be omitted. Even if the current control circuit 20 and other circuits are added in place of the frequency divider 12, the configuration can still be simplified. Even if the frequency divider 12 is omitted and the capacitor C is increased, the current control circuit 20 can perform the pull-in operation, so that the capture range can be increased in appearance. Of course, if the capacitor C is increased, the hold range L _D (see Figure 4) will be expanded, so the PLL
10 works very stably.

Furthermore, according to the present invention, mislocks can be easily removed.

Note that the sc mentioned above may be a subcarrier of either the NTSC system or another television system.
In addition, this invention provides a PLL for a jumping correction circuit.
It can also be applied other than. In the jumping correction circuit
If there are unnecessary components such as 2sc and 4sc in addition to 3sc, the beat components with 3sc will be mixed into the playback video signal, which may cause color killers to malfunction, but when using the PLL according to this invention, 2sc or 4sc component for 3sc component
Since it is possible to attenuate up to 60 dB, the PLL according to the present invention is extremely suitable for use in the carrier generator of the above-mentioned jumping correction circuit.

[Brief explanation of the drawing]

Figure 1 is a system diagram of the jumping correction circuit, Figure 2 is a system diagram of the jumping correction circuit.
Figure 3 is a system diagram of the PLL, Figure 3 is a system diagram of the improved PLL, Figure 4 is an explanatory diagram of its operation, Figure 5 is a system diagram showing an example of the PLL according to the present invention, and Figure 6 is its outline. System diagram showing specific examples of the division, Figures 7 and 8
The figure is a waveform diagram for explaining the operation, and FIGS. 9 and 10 are system diagrams showing other examples of the present invention. 10 is PLL, 11 is VCO, 13 is phase comparator,
14 is a low-pass filter, 20 is a current control circuit, 21, 22, 46, 47 are current sources, and 24 is a Schmitt circuit.

Claims (1)

[Claims] 1. A variable oscillator, a phase comparator that is directly connected to the variable oscillator without using a frequency divider and that compares the frequency of its oscillation output with the frequency of an input signal, and smoothes the phase comparison output. A PLL loop is formed with a low-pass capacitor of relatively large capacity, and a current control circuit having first and second current sources is provided after the phase comparator, and the output voltage of the phase comparator is is input to the Schmitt circuit, and based on this output, either the first or second current source is controlled to operate selectively, and until the pull-in operation occurs, the first and second current sources are A PLL that charges and discharges the capacitor with a current generated by the PLL to form a control voltage for the variable oscillator. 2. A variable oscillator, a phase comparator that is directly connected to this without going through a frequency divider and compares the frequency of its oscillation output with the frequency of the input signal, and a low-pass with a relatively large capacity that smoothes the phase comparison output. A PLL loop is formed with the capacitor for
Furthermore, a current control circuit having first and second current sources is provided after the phase comparator, and the output voltage of the phase comparator is input to the Schmitt circuit;
Based on this output, either the first or second current source is controlled to operate selectively,
Until the pull-in operation occurs, the capacitor is charged and discharged by the current from the first and second current sources to form a control voltage for the variable oscillator,
A PLL that detects a specific oscillation frequency among the oscillation frequencies of the variable oscillator and controls the current control circuit to cut off both the first and second current sources when this detection output is obtained. . 3 When the third current source is connected to the first current source provided in the current control circuit, and the fourth current source is connected to the second current source, and the detection output is obtained, the 3. The PLL according to claim 2, wherein the third and fourth current sources are disconnected from the first and second current sources.