JPH0317171B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for driving a so-called latching relay that self-maintains the switching state of a relay switch even if the relay coil is once energized and then the energized state is released.

A known example of a drive circuit for this type of latching relay is Utility Model Publication No. 48702/1983. In the circuit of this invention, current is passed in one direction and the opposite direction to the relay coil by charging and discharging the capacitor to operate it alternately, but the capacitor has a large capacity, so it is difficult to convert this circuit into a semiconductor integrated circuit (IC). This poses a major obstacle if this is the intention. Also, in some prior art, one relay coil and one switching coil of a so-called two-winding latching relay are used.
For series circuits consisting of NPN transistors and one relay coil and the other switching
A series circuit consisting of NPN transistors is connected in parallel between both output terminals of a power supply, and the base of the other switching transistor is connected to the connection point between the one relay coil and the one switching transistor. is taken.
In this configuration, by applying a signal to the base of the one switching transistor to cut it off, the other switching transistor becomes conductive, thereby exciting the other relay coil. Further, by making the one stitching transistor conductive, the one relay coil is excited. In such prior art, current is supplied to the base of the other switching transistor via the one relay coil. Therefore, the base current of the other transistor oscillates during a transient period, and therefore, the excitation current for the other relay coil, which is amplified by this oscillating base current, fluctuates greatly. Therefore, the switching mode of the latching relay does not respond accurately to the input signal, resulting in malfunction. Further, in such prior art, when a high input voltage is applied to each of the series circuits, a large amount of power is consumed by the relay coil.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a drive circuit that allows the switching behavior of a latching relay to accurately respond to input signals.

FIG. 1 is a block diagram showing an electric circuit configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing a specific circuit configuration. Figures 1 and 2 are shown below.
The present invention will be explained in detail with reference to the figures. A so-called two-winding latching relay 1 has relay coils 2 and 3 and relay switches 4 and 5. Once one relay coil 2 of the latching relay 1 is energized, the relay switch 4 is self-maintained in a conductive state even after the energization is released. Once the other relay coil 3 is energized, the relay switch 4 is self-maintained in the cut-off state even after the other relay coil 3 is de-energized. The relay switch 5 is for external connection, and is self-maintained by changing its switching state by excitation of the relay coils 2 and 3. Transistors 6 and 7 as switching elements are connected in series to the relay coils 2 and 3, respectively, and back electromotive force prevention diodes D ₁ ,
_D2 is also provided. These constitute a relay drive circuit A. These relay drive circuits A are respectively connected to a reset output and a set output Q of a flip-flop B consisting of a transistor or the like. This flip-flop B consists of transistors 8 and 9 whose collectors are connected to the bases of each transistor 6 and 7 of the relay drive circuit A.
and NPN transistors 10 and 11 whose emitters are connected to the bases of each transistor 6 and 7 of relay drive circuit A, and this transistor 10,
transistors 12 and 13 whose collectors are connected to the bases of transistors 11 and 2 pairs of transistors 14 which are connected in parallel to the bases of transistors 12 and 13;
and 15, 16, and 17. A line a supplying the base voltage of transistors 8 and 9 of flip-flop B is connected to the output of pulse generating circuit C. This pulse generating circuit is composed of seven transistors 18 to 24, eight resistors _R1 to _R8 , a first stage resistor _R1 , and a capacitor 25a that applies a voltage to the base of the transistor 18. This capacitor _25a resistor
When it is charged through R ₁ and its terminal voltage reaches a value that allows the first stage transistor 18 to conduct, the first stage transistor 18 is turned on. The second to seventh stage transistors are each connected to the collector of the previous stage transistor, so when the transistor 18 is turned on, the second stage is turned off, the third stage is turned on, and so on, and the seventh stage is turned on with a delay. Outputs pulses. Pulse generation circuit C is connected to capacitor 2
5a, 25b and transistors 18 to 2 in each stage
4 and resistors R ₁ to R ₈ have a delay function. When the waveform shown in FIG. 31 is derived from the transistor 28 to the line d, the collector of the transistor 18 has a delay time T ₁ as shown in FIG.
becomes low level with a delay of Therefore, the transistor 19 is cut off, and a charging circuit is formed by this junction capacitance and the resistor _R3 , and as _shown in FIG. Become. transistor 2
0 conducts in response to the output from the collector of transistor 19. Thereafter, the delay times T ₃ and T ₄ are obtained by the operation of the transistors 21 and 23 in the same manner, and the pulse width from the collector of the transistor 24 is (T ₁ +
T ₂ + T ₃ + T ₄ ) output pulses are output. In this way, when the input signal shown in FIG. 3 is applied to the power control circuit D including the Schmitt circuit, the line of the pulse generation circuit C has a time (T ₁ +
A pulse having a pulse width of T ₂ +T ₃ +T ₄ ) is derived. The pulse generating circuit C is operated by the output of the power control circuit D employing a Schmitt circuit configuration. In this power control circuit D, when the input signal input via line b exceeds a predetermined discrimination level, the diode _D3 becomes conductive.
Before that, a transistor 25 is connected via resistors 9 and 10.
turns on, and current flows from the connection point with the emitter of transistor 26 through resistor _R11 . However, when transistor 26 is turned on due to conduction of diode _D3 , transistor 2
Only the saturation voltage between the collector and emitter of transistor 26 is applied between the base and emitter of transistor 5, transistor 25 is turned off, and base bias is supplied to transistor 27 through two diodes D ₄ and D ₅ . is turned on, transistor 28 is also turned on, and an output is produced on line d. The input of this power control circuit D is line b, and this line b is connected to a constant voltage circuit E. In constant voltage circuit E, transistor 2
9 and 30 constitute a thyristor. When the voltage V ₁ on line c exceeds the base-emitter voltage V ₂ at which transistor 29 becomes conductive, transistors 29 and 30 remain conductive. When the sum of the forward voltage drops of the plurality of diodes D ₆ to _{D 11} connected to the base of the transistor 29 is Vd, and the collector-emitter voltage at which the transistor 30 can be conductive is V3, V1>Vd+V3... When (1) is established, the base voltages of the transistors 29 and 31 are fixed to Vd. Transistor 29,3
A diode D ₁₂ is connected to the transistor 30, and a resistor R ₁₂ is connected between the collector and emitter of the transistor 30. The aforementioned resistance R ₁₂
acts to operate the thyristor consisting of transistors 29 and 30 when voltage V1 is applied to line c, and has a high resistance value. A resistor R ₁₃ is connected in series to the transistor 29 .

In this state, even if the voltage on line c fluctuates, diodes D ₁₂ , D ₆ to _{D 11} and transistor 2
9, 30 and resistor R ₁₃ ,
Constant current operation is achieved. Therefore the diode
The forward voltage drop Vd between D ₆ and D ₁₁ is always constant, and a stable constant voltage is output to line b. This constant current value I1 is determined by the second equation.

I1=Vd-V2/R ₁₃ ...(2) By interposing such a constant voltage circuit E between line c and line b, when a high voltage is applied to line c, However, line b
voltage is kept at a constant voltage lower than that.
Therefore, the power consumption in the relay coils 2 and 3 is prevented from being wasted. Furthermore, by stabilizing the voltage on line b, the operations of the pulse generating circuit C and the power control circuit D become stable, and the latching relay 1 can operate reliably.

Referring again to FIG. 1, a signal from DC power supply 33 via switch 32 is applied from line c through constant voltage circuit E to line b.

Referring to FIG. 4, assume that an input signal having a waveform shown in FIG. 4b is applied to line b by pressing the switch 32. The power control circuit D including the Schmitt circuit derives a waveform output shown in FIG. 4D on the line d, and when the line d is at a high level, the pulse generation circuit C operates. The pulse generating circuit C derives the waveform shown in FIG. 4a in response to the output from the power control circuit D.
Here, it is assumed that flip-flop B is in the set state and therefore relay switch 4 is off. As a result, the output of the inverting circuit H becomes high level, the output of the inverting circuit F becomes low level, and the output of the inverting circuit G becomes high level. The output waveform from inverting circuit H is shown in FIG. 4e.
The pulse shown in FIG. 4g is derived from the NAND gate J, which causes the flip-flop B
is reset. The output waveform of the reset output is shown in FIG. 4h. In this way, the transistor 6 becomes conductive, the relay coil 2 is excited, the switching states of the relay switches 4 and 5 change, and the relay switch 4 becomes conductive. The switching mode of relay switch 4 is shown in Fig. 4i.
is shown. By turning off switch 32, power control circuit D is cut off, thereby de-energizing flip-flop B and relay coils 2 and 3. At this time, the switching mode of relay switches 4 and 5 is self-maintained.

When the switch 32 is turned on again, the output of the inverting circuit F is at a high level because the relay switch 4 is on as described above. Therefore, the output from the pulse generating circuit C is derived via the NAND gate I as shown in FIG. 4k. As a result, the transistor 7 of the drive circuit A is turned on, the relay coil 3 is excited, and the relay switch 4 is accordingly turned off, changing the switching mode of the relay switch 5. Thereafter, when the switch 32 is turned off, the excitation of the relay coil 3 is canceled, but thereafter the switching mode of the relay switches 4 and 5 is self-maintained.

The inverting circuit K is composed of a transistor 34 whose base voltage is the output of the pulse generating circuit C, the inverting circuits G and H are composed of transistors 35 and 36 whose base voltage is the output of the relay switch 4, and the inverting circuit F is composed of transistors 35 and 36 whose base voltage is the output of the relay switch 4. The inversion circuit H is composed of a transistor 37 whose base voltage is an output generated at the collector of a transistor 36.

NAND circuits I and J are forward diodes
It is composed of transistors 38 and 39 whose bases are connected to D ₁₃ , D ₁₄ , D ₁₅ , and D ₁₆ . V~
Z is a terminal that becomes an external terminal when integrated into an IC.

As explained above, according to the present invention, the input signal is level-discriminated, pulses are generated thereby to change the stable state of the flip-flop, and the switching mode of the relay switch of the latching relay is changed according to the flip-flop output. Since the latching relay is switched, malfunctions do not occur due to the adverse effects of the inductance of the coil of the latching relay, and the switching mode can be changed accurately in response to the input signal.

Furthermore, the present invention does not set and reset the latching relay by charging and discharging a capacitor as in the prior art, but instead uses a flip-flop in combination with a NAND gate and an inverting circuit.
This has the effect of making it possible to use ICs and progressing toward miniaturization.

[Brief explanation of the drawing]

The drawings show an embodiment of the IC drive control circuit for the latching relay of the present invention, and FIG. 1 is a block diagram;
2 is a specific circuit diagram, FIG. 3 is a waveform diagram of the pulse generating circuit, and FIG. 4 is a waveform diagram for explaining the operation of FIG. 2. 1... 2-winding latching relay, 2, 3... Relay coil, A... Relay drive circuit, B...
Flip-flop, C...Pulse generation circuit, D...
...Electric power control circuit, E... Constant voltage circuit, F, G,
H, K...inversion circuit, I, J...NAND gate,
33...Switch.

Claims (1)

[Claims] 1. A relay drive circuit section that excites a relay coil that changes the switching state of the latching relay in response to the two stable states of the flip-flop, and a first transistor whose base is connected to a constant voltage source via one diode. , the collector-emitter circuit of the first transistor is connected between the base and emitter, and the base is connected to the constant voltage source via a resistor, and is made conductive before the diode is made conductive, and the first transistor is made conductive. and a third transistor that is controlled by the second transistor and conducts when the second transistor is disconnected to generate an output pulse.
a power control circuit section that includes a transistor, a constant voltage circuit section that includes a plurality of series-connected diodes and transistors and that constitutes the constant voltage source, and a plurality of transistors that are connected in series. a pulse generation circuit section configured as shown in FIG. two flip-flops responsive to the output pulse of the latching relay and the switching state of one of the latching relays to set the flip-flop in a stable state corresponding to the switching state of the other one.
A latching relay drive circuit characterized by comprising a NAND gate.