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JPH0317225B2 - - Google Patents
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JPH0317225B2 - - Google Patents

Info

Publication number
JPH0317225B2
JPH0317225B2 JP59029130A JP2913084A JPH0317225B2 JP H0317225 B2 JPH0317225 B2 JP H0317225B2 JP 59029130 A JP59029130 A JP 59029130A JP 2913084 A JP2913084 A JP 2913084A JP H0317225 B2 JPH0317225 B2 JP H0317225B2
Authority
JP
Japan
Prior art keywords
layer
semiconductor substrate
recessed
region
gate region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP59029130A
Other languages
Japanese (ja)
Other versions
JPS60171770A (en
Inventor
Hiroaki Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nihon Inter Electronics Corp
Original Assignee
Nihon Inter Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nihon Inter Electronics Corp filed Critical Nihon Inter Electronics Corp
Priority to JP59029130A priority Critical patent/JPS60171770A/en
Publication of JPS60171770A publication Critical patent/JPS60171770A/en
Publication of JPH0317225B2 publication Critical patent/JPH0317225B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/192Base regions of thyristors
    • H10D62/206Cathode base regions of thyristors

Landscapes

  • Thyristors (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置の製造方法に関し、特に半
導体基板の一主面にカソード領域とゲート領域と
を有し、このゲート領域がカソード領域に凹没す
るように形成されている半導体装置において、ゲ
ート領域となる凹没面直下のPB層の拡散によつ
て形成されるNBゲート領域内への拡散層段差を
極力小さくした半導体装置の製造方法に関する。
Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and in particular, a semiconductor device having a cathode region and a gate region on one principal surface, the gate region being recessed into the cathode region. A method for manufacturing a semiconductor device that minimizes the step difference in the diffusion layer into the N B gate region, which is formed by diffusion of the P B layer directly under the recessed surface that becomes the gate region, in a semiconductor device formed as follows. Regarding.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

大電力用半導体装置、例えばゲート補助ターン
オフサイリスタ、ゲートターンオフサイリスタ
(GTO)、高周波サイリスタ等の半導体装置では
半導体基板の一主面側にカソード領域とゲート領
域が段差が設けられて両領域が互いに絶縁分離さ
れかつゲート領域がカソード領域に微細に入り組
んだ形状に形成される構造のものが多い。
In high-power semiconductor devices, such as gate auxiliary turn-off thyristors, gate turn-off thyristors (GTO), and high-frequency thyristors, a cathode region and a gate region are provided with a step on one principal surface of the semiconductor substrate, so that the two regions are insulated from each other. There are many structures in which the gate region is separated and formed in a finely intricate shape in the cathode region.

上記のような構造の半導体装置を製作する場合
次のような不都合がある。
When manufacturing a semiconductor device having the above structure, there are the following disadvantages.

すなわち第1図に示すように半導体基板1の一
主面側にカソード領域となるNB層2とゲート領
域となるPB層3とを設け、これらの両領域2,
3が互いに絶縁分離されるようにゲート電極が設
けられる箇所を凹没面3aとしている。
That is, as shown in FIG. 1, an N B layer 2 serving as a cathode region and a P B layer 3 serving as a gate region are provided on one main surface side of a semiconductor substrate 1, and both these regions 2,
The portion where the gate electrode is provided so that the gate electrodes 3 and 3 are insulated and separated from each other is defined as a recessed surface 3a.

この凹没面3aは化学エツチング等により、例
えば深さ約50μm程度に形成されるが、この凹没
面3aの作成順序として次の理由によりPB層3
の拡散以前に作成されるのが一般的である。
This recessed surface 3a is formed, for example, to a depth of about 50 μm by chemical etching or the like.
It is generally created before the spread of.

すなわち、PB層3の形成後に化学エツチング
等により凹没面3aを形成すると、ゲート領域面
の抵抗の増大を招き、例えばゲート補助ターンオ
フサイリスタを製作した場合にはターンオン及び
ターンオフ特性等に悪影響を与える結果となる。
That is, if the recessed surface 3a is formed by chemical etching or the like after the formation of the P B layer 3, the resistance of the gate region surface will increase, and for example, when a gate-assisted turn-off thyristor is manufactured, this will adversely affect the turn-on and turn-off characteristics. result in giving.

そこで、一般にあらかじめゲート領域となる部
分に凹没面3aを作成した後にPB層3を形成す
べく拡散を行なうようにしている。
Therefore, in general, a concave surface 3a is created in advance in a portion that will become the gate region, and then diffusion is performed to form the P B layer 3.

しかるに上記の方法を採用すると、凹没面3a
を形成したゲート領域の直下のベース領域となる
NB層4に凹没面3aの深さ、例えば前記の例で
は約50μm程度の深さに相当する拡散層段差4a
が形成され、必要とする耐圧等の特性を維持する
ためにはこの拡散層段差4aを考慮してNB層4
の厚さを、例えば約230μm以上にする必要が生
じてくる。
However, if the above method is adopted, the concave surface 3a
This becomes the base region directly under the gate region where
N B layer 4 has a diffusion layer step 4a corresponding to the depth of the recessed surface 3a, for example, about 50 μm in the above example.
is formed, and in order to maintain the required characteristics such as withstand voltage, the N B layer 4 is
It becomes necessary to increase the thickness to, for example, about 230 μm or more.

しかしながらこのNB層4の厚さを増加させる
と、順方向電圧降下等の増大を招き電気的特性に
悪影響を与えて好ましくないという不都合があ
る。
However, increasing the thickness of the N B layer 4 causes an undesirable increase in the forward voltage drop, which adversely affects the electrical characteristics.

〔発明の目的〕[Purpose of the invention]

本発明は上記の事情に基づいてなされたもので
凹没面が形成されたゲート領域直下のNB層に形
成される拡散層段差を極力小さくし、NB層の厚
さの増加を抑制し順方向電圧降下等の電気的特性
を改善し得る半導体装置の製造方法を提供するこ
とを目的とする。
The present invention has been made based on the above circumstances, and it is possible to minimize the step difference in the diffusion layer formed in the N B layer directly under the gate region where the concave surface is formed, and to suppress the increase in the thickness of the N B layer. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve electrical characteristics such as forward voltage drop.

〔発明の概要〕[Summary of the invention]

本発明は、半導体基板の一主面にカソード領域
とゲート領域とを有し、ゲート領域がカソード領
域に凹没し、両領域間に段差が設けられて絶縁分
離された半導体装置の製造方法において、凹没し
た前記ゲート領域となる凹没面の表面粗さを前記
凹没面を除いた前記半導体基板の表面の表面粗さ
よりも小さくしかつ両者の表面粗さの比を大きく
した後、前記半導体基板の一主面側から不純物を
拡散して前記凹没面直下に拡散層段差の小さいベ
ース領域を形成するようにし、かかるベース領域
の厚さを必要以上に増加させることを防止して電
気的特性の劣化を抑制した半導体装置の製造方法
である。
The present invention provides a method for manufacturing a semiconductor device that has a cathode region and a gate region on one main surface of a semiconductor substrate, the gate region is recessed into the cathode region, and a step is provided between both regions to isolate them. , after making the surface roughness of the recessed surface that becomes the recessed gate region smaller than the surface roughness of the surface of the semiconductor substrate excluding the recessed surface and increasing the ratio of the surface roughnesses of the two, Impurities are diffused from one main surface side of the semiconductor substrate to form a base region with a small step of the diffusion layer directly under the recessed surface, and the thickness of the base region is prevented from increasing more than necessary. This is a method of manufacturing a semiconductor device that suppresses deterioration of physical characteristics.

〔発明の実施例〕[Embodiments of the invention]

以下に本発明の一実施例を図面を参照して説明
する。
An embodiment of the present invention will be described below with reference to the drawings.

本発明はシリコン半導体基板への不純物の拡散
速度が表面粗さに大きく影響され、表面粗さ、す
なわち加工歪等を多く有し表面状態が粗い面では
加工歪等が少なく表面状態が鏡面に近い状態の面
に比較してその拡散速度が極めて速いという現象
を利用している。
In the present invention, the diffusion rate of impurities into a silicon semiconductor substrate is greatly influenced by the surface roughness, and a surface with a large amount of processing strain, etc., and a rough surface condition has less processing strain, etc., and the surface condition is close to a mirror surface. It takes advantage of the phenomenon that the diffusion rate is extremely fast compared to the state.

第2図を参照して本発明を説明すると、例えば
サイリスタ構造を製作する場合、半導体基板11
にカソード領域としてのNE層12、ゲート領域
としてのPB層13、ベース領域としてのNB層1
4、アノード領域としてのPE層15が作成され
るが、前記PB層13を作成する以前に次のよう
な処理を行う。先ず、半導体基板11の一主面、
すなわちPB層13を拡散する以前の半導体基板
11の表面を例えば#600程度の研磨材を使用し
てラツピングする。
To explain the present invention with reference to FIG. 2, for example, when manufacturing a thyristor structure, the semiconductor substrate 11
N E layer 12 as a cathode region, P B layer 13 as a gate region, and N B layer 1 as a base region.
4. The PE layer 15 as an anode region is created, but before creating the P B layer 13, the following process is performed. First, one main surface of the semiconductor substrate 11,
That is, the surface of the semiconductor substrate 11 before the P B layer 13 is diffused is lapped using, for example, a #600 abrasive.

次いで、ゲート電極が取付けられる部分の表面
を化学エツチングによつてエツチングし、深さ約
50μm程度の凹没面13aを形成する。この凹没
面13aは化学エツチングによつて形成するの
で、前記半導体基板11の表面に比較して加工歪
等が少なく表面粗さが小さい。
Next, the surface of the part where the gate electrode will be attached is etched by chemical etching to a depth of approximately
A recessed surface 13a of about 50 μm is formed. Since this recessed surface 13a is formed by chemical etching, it has less processing distortion and the like and has a smaller surface roughness than the surface of the semiconductor substrate 11.

上記の状態で半導体基板11の一主面側から
PB層13を形成すべくP型不純物を拡散すると、
凹没面13aの直下に拡散層段差14aが形成さ
れるが、両表面の表面粗さの相違により凹没面1
3aの直下よりも他の半導体基板11の部分の方
が拡散速度が速いために前記拡散層段差14aは
極めて小さいものとなる。
From the one main surface side of the semiconductor substrate 11 in the above state
When P-type impurities are diffused to form the P B layer 13,
A diffusion layer step 14a is formed directly below the recessed surface 13a, but due to the difference in surface roughness between the two surfaces, the recessed surface 1
Since the diffusion rate is faster in other parts of the semiconductor substrate 11 than directly below the diffusion layer 3a, the diffusion layer step 14a becomes extremely small.

例えばエツチング深さ約50μm程度の凹没面1
3aを形成する場合には拡散層段差14aを約
20μm程度に抑制することができ、その結果、従
来に比較してNB層11の厚さを約30μm程度薄く
することができ順方向電圧降下等の電気的特性を
改善することが可能となる。
For example, the recessed surface 1 with an etching depth of about 50 μm
3a, the diffusion layer step 14a is approximately
As a result, the thickness of the N B layer 11 can be reduced by about 30 μm compared to the conventional method, and electrical characteristics such as forward voltage drop can be improved. .

なお、PB層13内には通常の選択拡散法によ
りNB層12が形成され以後所定の処理が施こさ
れてサイリスタペレツトが製作される。
Note that the N B layer 12 is formed in the P B layer 13 by a normal selective diffusion method, and then a predetermined process is performed to produce a thyristor pellet.

〔発明の効果〕〔Effect of the invention〕

本発明は上記のように凹没面内の表面粗さと
PB層が形成される以前の半導体基板の表面の表
面粗さの差を大幅に変えかつ凹没面内の表面粗さ
に比較して前記半導体基板表面の表面粗さを大き
くしたので、拡散速度の相違により凹没面直下に
形成されるPB層の拡散層段差を小さくすること
ができ、その結果、NB層の厚さを増加させるの
を抑制でき、順電圧降下等の電気的特性を改善す
ることができる。
As mentioned above, the present invention improves the surface roughness within the concave surface.
The difference in surface roughness of the semiconductor substrate surface before the P B layer was formed was significantly changed, and the surface roughness of the semiconductor substrate surface was increased compared to the surface roughness within the concave surface, so that diffusion Due to the difference in speed, it is possible to reduce the step difference in the diffusion layer of the P B layer that is formed directly under the concave surface, and as a result, it is possible to suppress the increase in the thickness of the N B layer, and to reduce electrical problems such as forward voltage drop. Characteristics can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体装置の製造方法によつて
製作された半導体装置の一例を示す一部切欠断面
図、第2図は本発明に係る半導体装置の製造方法
によつて製作された半導体装置の一例を示す一部
切欠断面図である。 11……半導体基板、12……NE層、13…
…PB層、13a……凹没面、14……NB層、1
4a……拡散層段差、15……PE層。
FIG. 1 is a partially cutaway sectional view showing an example of a semiconductor device manufactured by a conventional semiconductor device manufacturing method, and FIG. 2 is a semiconductor device manufactured by a semiconductor device manufacturing method according to the present invention. It is a partially cutaway sectional view showing an example. 11...Semiconductor substrate, 12...N E layer, 13...
...P B layer, 13a...concave surface, 14...N B layer, 1
4a... Diffusion layer step, 15... P E layer.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板の一主面にカソード領域とゲート
領域とを有し、ゲート領域がカソード領域に凹没
し、両領域間に段差が設けられて絶縁分離された
半導体装置の製造方法において、凹没した前記ゲ
ート領域となる凹没面の表面粗さを前記凹没面を
除いた前記半導体基板の表面の表面粗さよりも小
さくしかつ両者の表面粗さの比を大きくした後、
前記半導体基板の一主面側から不純物を拡散して
前記凹没面直下に拡散層段差の小さいベース領域
を形成することを特徴とする半導体装置の製造方
法。
1. In a method for manufacturing a semiconductor device having a cathode region and a gate region on one main surface of a semiconductor substrate, the gate region is recessed into the cathode region, and a step is provided between both regions to isolate them. After making the surface roughness of the recessed surface that will become the gate region smaller than the surface roughness of the surface of the semiconductor substrate excluding the recessed surface and increasing the ratio of the two surface roughnesses,
A method for manufacturing a semiconductor device, characterized in that impurities are diffused from one main surface side of the semiconductor substrate to form a base region with a small step difference in the diffusion layer directly under the recessed surface.
JP59029130A 1984-02-17 1984-02-17 Manufacturing method of semiconductor device Granted JPS60171770A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59029130A JPS60171770A (en) 1984-02-17 1984-02-17 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59029130A JPS60171770A (en) 1984-02-17 1984-02-17 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS60171770A JPS60171770A (en) 1985-09-05
JPH0317225B2 true JPH0317225B2 (en) 1991-03-07

Family

ID=12267711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59029130A Granted JPS60171770A (en) 1984-02-17 1984-02-17 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60171770A (en)

Also Published As

Publication number Publication date
JPS60171770A (en) 1985-09-05

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