JPH0317252B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a PLL frequency synthesizer with improved S/N ratio. (Prior Art) A conventional PLL frequency synthesizer was constructed as shown in FIG. 1a or 1b. The conventional PLL frequency synthesizer shown in FIG. The phase of the output and the phase of the oscillation output of the reference oscillator 3 are compared in phase by a phase comparator 4, and the output of the phase comparator 4 is fed back as a control voltage to the voltage controlled oscillator 1 via the low-pass filter 5. The oscillation frequency of 1 is controlled. On the other hand, when the frequency synthesizer shown in Figure 1a is used as a local oscillator in a synthesizer-type FM receiver, the receiving frequency band is 76M.
Hz ~ 90MH, intermediate frequency 10.7MH, oscillation frequency of reference frequency oscillator 3, that is, reference frequency 100K
When it is Hz, the frequency division ratio of the programmable frequency divider 2 can be varied from 653 to 793. However, the S/N of a PLL frequency synthesizer is generally independent of the frequency division ratio, and the higher the frequency response of the loop, the better the S/N becomes and approaches the reference frequency S/N.
However, when considering the presence of noise generated by the phase comparator, it is better to compensate for the decrease in gain due to a large frequency division ratio by amplifying the output of the phase comparator and obtain the necessary loop gain. It is possible to obtain a PLL frequency synthesizer with a higher S/N by reducing the gain in the stage subsequent to the phase comparator by making it smaller. For this reason, there is a conventional PLL frequency synthesizer that uses a heterodyne as shown in FIG. 1b, which allows the frequency division ratio to be reduced. Figure 1b
The PLL frequency synthesizer shown in FIG.
The frequency conversion circuit A includes a mixing circuit 7 and a low-pass filter 8, and converts the oscillation output of the oscillator 6 and the oscillation output of the voltage-controlled oscillator 1 into the frequency conversion circuit A.
is input, the frequency conversion circuit A converts it into the output of the frequency difference between both inputs, the frequency of the output of the frequency conversion circuit A is divided by the programmable frequency divider 9, and the phase of the output of the programmable frequency divider 9 is calculated. and reference oscillator 3
The phase of the output from the phase comparator 4 is compared with the phase of the output of the oscillator 1, and the output of the phase comparator 4 is fed back to the voltage controlled oscillator 1 via a low-pass filter 5 as a control voltage. When the PLL frequency synthesizer shown in Figure 1b is used as a local oscillator in a synthesizer-type FM receiver, the oscillation frequency of oscillator 6 is
When set to 65MHz, the frequency division ratio of the programmable frequency divider 9 is 3 to 3 under each of the above frequency conditions.
It is only necessary to change the frequency up to 143, and the frequency division ratio will be lower than in the case of FIG. 1a. In the case of the above-mentioned frequency relationship, it is difficult to completely limit the oscillation frequency of the voltage controlled oscillator 1 within the set frequency range of 65.3 to 79.3 MHz, and it is difficult to completely limit the oscillation frequency of the voltage controlled oscillator 1 to the set frequency range of 65.3 to 79.3 MHz. It often works up to. In the case of the PLL frequency synthesizer shown in Fig. 1b, the frequency relationship of the output of the frequency conversion circuit A is set to the frequency obtained by subtracting the reference frequency (65MHz) from the oscillation frequency of the voltage controlled oscillator 1, and this frequency is divided into programmable frequencies. It is assumed that the frequency is divided by the device 9.
However, contrary to the case where the frequency obtained by subtracting the reference frequency from the oscillation frequency of the voltage controlled oscillator 1 is divided,
Even at a frequency obtained by subtracting the oscillation frequency of the voltage controlled oscillator 1 from the reference frequency, the frequencies input to the programmable frequency divider 9 may be the same frequency. When the PLL frequency synthesizer operates in the above-mentioned relationship, the direction in which the oscillation frequency of the voltage controlled oscillator 1 changes is opposite to that of the frequency division ratio of the programmable frequency divider 9. For example, when the frequency division ratio of the programmable frequency divider 9 is set to 3, the frequency of the output from the frequency conversion circuit A input to the programmable frequency divider 9 is 100K.
Hz, the PLL circuit locks, but in this case, the oscillation frequency of voltage controlled oscillator 1 is 65.3MHz.
and 64.7MHz (the oscillation frequency of voltage controlled oscillator 1 is
It had the disadvantage of locking to both frequencies (because oscillations at frequencies lower than 65.3 MHz could occur). (Object of the Invention) The present invention has been made in view of the above, and is a PLL that can reduce the frequency division ratio and improve the S/N, and that does not lock onto two frequencies depending on the set frequency division ratio. The purpose is to provide a frequency synthesizer. The present invention will be explained below with reference to Examples. (Structure of the Invention) FIG. 2 is a block diagram showing the structure of an embodiment of the invention. The PLL frequency synthesizer in one embodiment of the present invention supplies the oscillation output of the voltage controlled oscillator 1 and the oscillation output of the oscillator 6 to a frequency conversion circuit A consisting of a mixing circuit 7 and a low-pass filter 8, A converts the oscillation frequency of the voltage controlled oscillator and the oscillation frequency of the oscillator 6 into an output of the difference frequency, and the frequency of the output of the frequency conversion circuit A is divided by the programmable frequency divider 9. There is. Similarly, the oscillation output of the voltage controlled oscillator 1 and the oscillation output of the oscillator 10 are connected to the mixing circuit 11.
and a low-pass filter 12, and is converted by the frequency conversion circuit B into an output of the difference frequency between the oscillation frequency of the voltage controlled oscillator 1 and the oscillation frequency of the oscillator 10. Programmable frequency divider 13
The structure is such that the frequency is divided by . Further, the phase of the output of the programmable frequency divider 6 and the phase of the output of the programmable frequency divider 13 are compared by the phase comparator 4, and the phase comparison output is passed to the low-pass filter 5.
It is configured so that it is fed back to the voltage controlled oscillator 1 as a control voltage via the voltage controlled oscillator 1. (Operation of the invention) In one embodiment of the present invention configured as described above, the difference frequency between the oscillation frequency of the oscillator 6 and the oscillation frequency of the voltage controlled oscillator 1 is divided by the programmable frequency divider 9, The difference frequency between the oscillation frequency and the oscillation frequency of the voltage controlled oscillator 1 is divided by a programmable frequency divider 13. The phase of the output of the programmable frequency divider 9 and the phase of the output of the programmable frequency divider 13 are compared by a phase comparator 4,
The output of the phase comparator 4 is smoothed by a low pass filter 5 to control the oscillation frequency of the voltage controlled oscillator 1. Therefore, the oscillation frequency of oscillator 6 is set to ₁ , and oscillator 10
Assume that the oscillation frequency of is ₂ , the set frequency division ratio of the programmable frequency divider 9 is n, the set frequency division ratio of the programmable frequency divider 13 is m, and the relationship between the frequency division ratios n and m is n+m=k=constant. , and when the oscillation frequency of the voltage controlled oscillator 1 is _v , ₁ < _v < ₂ .
Further, the mixing circuit 7 outputs a frequency ( _v − ₁ ) obtained by subtracting the oscillation frequency 1 of the oscillator 6 from the oscillation frequency _v of the voltage-controlled oscillator ₁ , and the mixing circuit 11 outputs the oscillation frequency v of the voltage-controlled oscillator 1 as the oscillation frequency _v of the oscillator 10.
Assume that the frequency ( ₂ − _v ) subtracted from the oscillation frequency _{2 of} is output. In this case, the frequency division ratios n and m are both integers with n, m>0. When the PLL frequency synthesizer is in the lock state, the relationship between the frequencies at the output of programmable frequency divider 9 and the output of programmable frequency divider 13 is ( _v - ₁ )/n=( ₂ - _v )/m. That is, 0<m/n= ₂ − _v / _v − ₁ . In the above equation, m/n is m/n>0, the denominator and numerator on the right side are both positive, and ( ₂ − _v )/( _v − ₁ )
locks when is equal to m/n, and ( _v −
₁ ) or ( ₂ − _v ) becomes negative, ( ₂ − _v )/( _v − ₁ ) becomes negative, indicating that lock does not occur. That is, if _v falls outside the set frequency range of voltage controlled oscillator 1, _v < ₁
When it becomes, ( ₂ − _v )>0, ( _v − ₁ )<V0
Therefore, ( ₂ − _v )/( _v − ₁ ) will be negative, but in this case it will not be locked. Conversely, when _v increases outside the set frequency range of voltage controlled oscillator 1 and _v < ₂ , ( ₂ − _v )
<0, ( _v − ₁ )>0, and it is not locked at this time either. Therefore, if the oscillation frequency of voltage controlled oscillator 1 falls outside the set frequency range,
PLL frequency synthesizer does not lock. This is ( _v − ₁ ) in mixing circuit 7, and mixing circuit 11
This is because the configurations are opposite to each other to output a frequency of ( ₂ − _v ) at
A phenomenon in which _v cannot be uniquely determined does not occur. Furthermore, when the frequency _v is within the set frequency range, the oscillation frequency _v of the voltage controlled oscillator 1 in the lock state is _v = 1/n + m (n ₂ + m ₁ ), which is uniquely determined by the set frequency division ratios n and m. It will be decided. Of course, as mentioned above, n+m=k=constant. Furthermore, the frequency relationship also holds true when ₁ > _v > ₂ . In addition, the maximum value of the set frequency division ratio of the programmable frequency divider 9 is n _MAX , the minimum value is n _MIN , the maximum value of the set frequency division ratio of the programmable frequency divider 13 is m _MAX , and the minimum value is
When m _MIN , n _MAX +m _MIN =n _MIN +m _MAX =k
The minimum value _VMIN and maximum value _VMAX of the oscillation frequency of the voltage controlled oscillator 1 at the time of lock are _VMIN = 1/m + n (n _{MIN 2} + m _{MAX 1} ) _VMAX = 1/m + n (n _{MAX 2} + m _{MIN 1} ) . Here, the PLL cycle break number synthesizer of this embodiment is
An example of the case where the present invention is applied to a synthesizer type FM receiver having the frequency conditions described in the conventional example will be described. The frequency relationship between the mixing circuits 7 and 11 is the same as above, and the oscillation frequency _v of the voltage controlled oscillator 1 is
65.3 to 79.3MHz, and the oscillation frequency of oscillator 6 is
When the oscillation frequency of the oscillator 10 is set to 65MHz and the oscillation frequency of the oscillator 10 is set to 79.6MHz, the frequency of the output of the frequency conversion circuit A is 0.3MHz to 14.3M relative to the required local oscillation frequency.
Hz, and the frequency of the output of frequency conversion circuit B is
14.3MHz to 0.3MHz. Comparison frequency is 0.1MHz
Then, the division ratio of the programmable frequency divider 9 is 3
The frequency division ratio of the programmable frequency divider 13 may be varied from 143 to 3 while maintaining the sum of the frequency division ratio of the programmable frequency divider 9 at 146. For example, the frequency division ratio n of the programmable frequency divider 9 is set to 3, and the frequency division ratio m of the programmable frequency divider 13 is set to 3.
The oscillation frequency of voltage controlled oscillator 1 is 65.3MHz in the lock state when is set to 143, 72.3MHz when the division ratio is set to n=n=73, and when the division ratio is set to n=143 and m=3. 79.3M when set to
Each is uniquely defined in Hz. Other frequency division ratios n, m
The same applies to the case of . Here, the relationship between the frequency division ratios n, m and the oscillation frequency _v of the voltage controlled oscillator 1 is shown in Table 1.

【table】

Claims (1)

[Claims] 1 First and second oscillating at mutually different frequencies
an oscillator, a voltage controlled oscillator, a first frequency conversion circuit that generates an output of a difference frequency between the oscillation frequency of the first oscillator and the oscillation frequency of the voltage controlled oscillator, and a second frequency conversion circuit that generates an output with a difference frequency from the oscillation frequency of the second oscillator; a first programmable frequency divider to which the output of the first frequency conversion circuit is supplied; and the second frequency conversion circuit. a second programmable frequency divider to which the output of the circuit is supplied and whose frequency division ratio is set such that the sum with the set frequency division ratio of the first programmable frequency divider becomes a predetermined constant value; The output of the programmable frequency divider and the second
and a phase comparator which is supplied with the output of the programmable frequency divider as an input and compares the phases of both inputs, and the output of the phase comparator is fed back to the voltage controlled oscillator. frequency synthesizer.