JPH031760B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a non-volatile random access memory device, and more particularly to a non-volatile random access memory device constructed by combining volatile dynamic memory cells and floating gate circuit elements. Regarding.

Background of the Technology Recently, in static random access memory devices, nonvolatile memory cells have been created by combining volatile memory cells with floating gate circuit elements, and nonvolatile memory devices using such nonvolatile memory cells have been developed. is being configured. In such a static random access memory device, the circuit configuration of each memory cell tends to become complicated and the size of each memory cell tends to increase. Since this tendency leads to a decrease in the reliability and degree of integration of the memory device, it is desired to improve the reliability and the degree of integration of the memory device by improving the circuit configuration.

Prior Art and Problems FIG. 1 shows a memory cell used in a conventional non-volatile static random access memory device. This memory cell consists of MIS (metal-insulator-semiconductor) transistors Q ₁ , Q ₂ , Q ₃
and a volatile static memory cell section 1 including a transistor Q ₄ and a non-volatile memory cell section 2 including an MIS transistor Q ₆ having a floating gate. This memory cell can store 1 bit of data. In addition to the MIS transistor Q ₆ , the nonvolatile memory cell section 2 includes an MIS transistor Q ₅ , a tunnel capacitor TC ₁ and
TC ₂ , a capacitor module CM ₁ , and capacitors C ₁ and C ₂ . A capacitor that produces a tunnel effect when a voltage is applied between its electrodes is called a tunnel capacitor.

In the circuit of FIG. 1, the static memory cell section 1 has a flip-flop type configuration similar to that used in conventional volatile static random access memory devices. Data is written and read in the static memory cell section 1 through transfer gate transistors connected to nodes _N1 and _N2 . In the nonvolatile memory cell section 2, the MIS transistor
The circuit including the gate of Q ₆ is in a floating state, separated from other circuits. Data can be stored depending on whether or not electrons are injected into this floating gate circuit. Therefore, the data in the static memory cell section is transferred to the non-volatile memory cell section 2 before the power supply V _CC of the memory device is cut off, and the data is transferred from the non-volatile memory cell section 2 conversely when the power supply V _CC is turned on. By using a configuration in which data is transferred to, or recalled from, the memory cell section 1, it becomes possible to realize a high-speed nonvolatile memory device.

For example, it is assumed that predetermined data is written in the static memory cell section 1, the node _N1 is at a low level (V _SS ), and the node _N2 is at a high level (V _CC ). If data in the static memory cell section 1 is to be transferred to the nonvolatile memory cell section 2 in this state, the control power supply _VEE is raised from the normal 0V state to, for example, 20 to 30V. At this time the node
Since N ₁ is at a low level, transistor Q ₅ is cut off and the capacitor module
Since the electrode _D1 of _CM1 is in a floating state, the gate of the transistor _Q6 is pulled up to a high voltage by capacitive coupling when the power supply _VEE is pulled up. Capacitance C (D ₁ , D ₂ ) and electrode between electrodes D ₁ and D ₂ of capacitor module CM ₁
Since the capacitance C (D ₁ , D ₃ ) between D ₁ and D ₃ is both sufficiently larger than the capacitance of tunnel capacitors TC ₁ and TC ₂ , the gate voltage of transistor Q ₆ is almost equal to the power supply V _HH. It can be raised to a similar voltage. As a result, a high voltage is applied across the tunnel capacitor _TC1 , and electrons are injected from the power supply _VSS to the floating gate side of the transistor _Q6 due to the tunneling phenomenon, and the floating gate is charged with a negative charge. The transistor _Q6 is turned off. This negative charge is retained for a long period of time even after the power supplies V _CC and V _HH of the memory device are cut off, and data is stored nonvolatilely.

When the node _N1 of the static memory cell unit 1 is at a high level and the node _N2 is at a low level, the transistor _Q5 is turned on, so even when the power supply _VHH is raised to, for example, 20 to 30V, the capacitor remains Electrode D ₁ of module CM ₁ is maintained at a low level. As a result, a high voltage is applied across the tunnel capacitor _TC2 , and electrons are extracted from the floating gate side of the transistor _Q6 to the power supply _VHH side due to the tunneling phenomenon, and the floating gate is charged with positive charges. Ru.

Next, an explanation will be given of the operation when data in the nonvolatile memory cell section 2 is transferred to the volatile memory cell section 1, for example, when the power is turned on. First, start from a state where the power supplies V _CC and V _HH are both 0V (= V _SS ), for example.
Raise only V _CC to e.g. 5V. At this time, if electrons are accumulated in the floating gate of transistor Q ₆ , transistor Q ₆ is in a cut-off state, and capacitor C ₂ and node N ₂
It is cut off between. Node N ₁ is a capacitor
Since it is connected to C ₁ , when the power supply V _CC is raised, the node N ₁ side, which has a large load capacity, goes to a low level.
The flip-flop circuit of the volatile memory cell section 1 is set so that the node _N2 side is at a high level. Conversely, if electrons are extracted from the floating gate of transistor Q ₆ and the floating gate is charged with positive charges, transistor Q ₆ is turned on, and node N ₂ and capacitor C ₂ are connected. capacitor
Since the capacitance of _C2 is sufficiently larger than the capacitance of capacitor _C1 , the flip-flop circuit of volatile memory cell section 1 is configured such that by raising the power supply V _CC , node _N2 becomes low level and node _N1 becomes high level. is set. In this way, data corresponding to the charge on the floating gate of the transistor _Q6 is set in the volatile memory cell section 1, and by using the circuit shown in FIG. 1, a nonvolatile memory device is constructed.

However, in the conventional device described above, a static flip-flop circuit is used as the volatile memory cell section, and the number of tunnel capacitors required is two, and the number of circuit elements increases. There was a problem that it was not necessarily suitable for achieving high integration and improving yield.

OBJECTS OF THE INVENTION In view of the problems with the conventional type described above, an object of the present invention is to reduce the number of circuit elements in a memory device based on the concept of adding a non-volatile memory cell section to a volatile dynamic random access memory cell. Reduce the number of tunnel capacitors by 1
The object of the present invention is to realize high integration and yield improvement of individual memory devices.

Structure of the Invention In the present invention, one memory cell is configured by pairing a volatile memory cell section and a nonvolatile memory cell section for saving storage information in the volatile memory cell section, and The digital memory cell section includes a capacitor section that stores an amount of charge according to information to be stored, a first transistor that transfers the information in the capacitor section to the bit line, and a gate connected to the capacitor section. a second transistor that is turned on or off according to information stored in the capacitor section; the nonvolatile memory cell section includes a third transistor whose gate is in a floating state; A tunnel effect occurs between the first and second capacitors, to which a write voltage is applied to one electrode when writing information of the section into the nonvolatile memory cell section, and the third transistor. a third capacitor connected between the gate and the other electrode of the first capacitor; the gate is connected to the other electrode of the second capacitor and the second transistor; a fourth transistor for changing the potential of a common connection point of the first and third capacitors according to whether the transistor is turned on or off;
and a fifth transistor connected between the transistor and the capacitor section and made conductive when information in the nonvolatile memory cell section is recalled to the volatile memory cell section. A random access memory device is provided.

Embodiment of the Invention A memory cell used in a nonvolatile random access memory device as an embodiment of the invention is a second memory cell.
As shown in the figure. This memory cell includes a volatile dynamic memory cell 3 and a nonvolatile memory cell section 5.
Equipped with. The volatile dynamic memory cell 3 consists of a first transistor _Q11 and a second transistor _Qc . The gate capacitance of the transistor Q _c constitutes the capacitor section of this cell and stores data in the volatile dynamic memory cell 3 .
As the capacitor section, a separate dedicated capacitor may be provided as shown by the broken line. transistor
The drain of _Q11 is connected to the bit line BL, and the source is connected to the gate of transistor _Qc .
On the gate of transistor _Q11 is the word line WL
is connected. The source of transistor Q _c is the power supply
Connected to V _SS (usually 0V). The connection point between the source of transistor _Q11 and the gate of transistor _Qc is designated as node _N11 .

The nonvolatile memory cell section 5 is a third transistor.
Q ₁₂ , a fourth transistor Q ₂₁ , a fifth transistor Q ₁₃ , a first capacitor C ₂₁ , a tunnel capacitor TC ₂₁ as a third capacitor, and a capacitor module CM ₂₁ . The capacitor module CM ₂₁ has three electrodes D ₂₁ , D ₂₂ and
D ₂₃ and the capacitance between electrodes D ₂₁ and D ₂₂ is the second
used as a capacitor. Electrodes D ₂₁ and D ₂₃
There is also capacitance between them. Transistor Q ₁₂
The drain of is connected to the power supply V _CC (typically +5V),
The source is connected to the drain of transistor _Q13 , and this connection point is designated as node _N13 . The voltage connected to the drain of this transistor _Q12 is the power supply
It does not have to be a fixed power supply like V _CC , it only needs to rise to the level of V _CC at the time of recall.

The source of transistor _Q13 is connected to node _N11 of the volatile memory cell. A high voltage for writing _VHH is applied to one terminal of the capacitor _C21 . The other terminal of capacitor _C21 is connected to one electrode of tunnel capacitor _TC21 , and this connection point is designated as node _N21 . capacitor module
Capacitor included in CM ₂₁ and capacitor C ₂₁
The capacitance of is selected to be sufficiently large compared to the capacitance of the tunnel capacitor TC ₂₁ . Electrode D ₂₁ of capacitor module CM ₂₁ is transistor Q _c
is connected to the drain of transistor Q21 and the gate of transistor _Q21 , and this connection point is designated as node _N12 . Electrode D ₂₂ of capacitor module CM ₂₁ is connected to the high voltage V _HH , electrode D ₂₃ is connected to the other electrode of tunnel capacitor TC ₂₁ and to the gate of transistor Q ₁₂ , and this connection point is connected to node N ₂₂ . do. The drain of transistor Q ₂₁ is connected to node N ₂₁ and the source is connected to the power supply V _SS (usually 0V). A recall (RC) signal is supplied to the gate of transistor _Q13 .

Next, the operation of the memory cell of this embodiment will be explained. Volatile dynamic memory cell 3 stores one bit by accumulating charge at node _N11 . First, the case where the storage contents of the volatile dynamic memory cell 3 are transferred to the nonvolatile memory cell section 5 will be described. When the word line is low, transistor _Q11 is cut off. When the charge is stored at the node _N11 and is at a high level, the transistor _Qc is turned on (conducting) and the node _N12 is at a low level. Transistor _Q21 is in a cut-off state, and node _N21 is in a floating state. High voltage V _HH from 0V
When raised to 25V, the floating gate (node N ₂₂ ) connects to the electrode of capacitor module CM _21.
The capacitive coupling between D ₂₁ and electrode D ₂₃ results in a low level (several volts), and node N ₂₁ is at approximately 22V due to capacitor C ₂₁ . In this way, between the ends of the tunnel capacitor TC ₂₁
A potential difference of about 20V occurs. Since the thickness of the insulating layer between the two electrodes of the tunnel capacitor is approximately 150 angstroms, an electric field of 10 MV/cm or more is applied to this insulating layer, causing a tunnel effect. Due to the tunneling effect, electrons are injected from node N ₂₂ to node N ₂₁ and node N ₂₂ is charged with positive charge when the high voltage V _HH is removed.

When the node _N11 is at a low level, the transistor _Qc is cut off and the node _N12 is in a floating state. Here, the high potential V _HH is set to 0
to 25V, node N ₁₂ will be approximately 22V due to the capacitive coupling between electrodes D ₂₁ and D ₂₂ of capacitor module CM ₂₁ . Therefore, transistor Q ₂₁ is turned on and the node
N ₂₁ becomes low level (0V). _{Furthermore , the} floating gate (node
N ₂₂ ) will be approximately 20V. As a result, a potential difference of about 20V is applied to both poles of tunnel capacitor TC ₂₁ , and electrons are transferred to node N ₂₁ due to the tunnel effect.
is injected into node _N22 , and when the high potential _VHH is removed, node _N22 is charged with negative charge. The positive or negative charge charged in this way is retained for a long period of time even if the power is cut off, and can be used for nonvolatile memory.

Transferring the stored contents from the nonvolatile memory cell section 5 to the volatile memory cell is performed as follows. When the recall signal goes high and is applied to the gate of transistor Q ₁₃ , transistor Q ₁₃
is in the on state. If positive charge is stored at node _N22 , transistor _Q12 is also turned on, and current is passed from power supply _Vcc to node _N11 , charging the capacitor formed by transistor _Qc . When negative charge is accumulated in the node _N22 , the transistor _Q12 is in the cut-off state, so no current is applied to the node _N11 , and the transistor _Qc
is not charged. In the case of recall, all the contents of the volatile memory cells 3 are initially set to a low level, and all word lines WL are also set to a low level.

A circuit diagram of a memory cell according to a modification of this embodiment is shown in the third example.
As shown in the figure. This circuit has a transistor between node _N12 and transistor _Qc in the circuit of Figure 2.
Q ₂₂ is provided, and the power supply V _CC is applied to its gate. The voltage applied to the gate need not be a fixed voltage, but may be a signal that reaches the V _CC level only when data is transferred from the volatile dynamic memory cell to the nonvolatile memory cell. In this way, the voltage applied to the drain of transistor Q _c is limited by transistor Q ₂₂ , and the voltage applied to the drain of transistor Q c is limited.
The influence of the drain voltage on the gate circuit of Q _c can be reduced, and the adverse effect (possibility of malfunction) on the dynamic memory cell can be reduced. The drain voltage of transistor Q _c is suppressed to V _CC −V _th by transistor Q ₂₂ .

Effects of the Invention According to the present invention, the number of circuit elements in a memory device can be reduced, and the number of tunnel capacitors can be reduced to 1.
It is possible to reduce the cell size and achieve higher integration and yield of the memory device.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a memory cell used in a conventional nonvolatile static random access memory device, and FIG. 2 is a circuit diagram of a memory cell used in a nonvolatile random access memory device as an embodiment of the present invention. , and FIG. 3 are circuit diagrams of a memory cell showing a modification of the embodiment of the present invention. 1... Volatile static memory cell section, 2... Nonvolatile memory cell section, 3... Volatile dynamic memory cell, 5... Nonvolatile memory cell section, C ₁ , C ₂ ,
C ₂₁ ... Capacitor, CM ₁ , CM ₂₁ ... Capacitor module, Q ₁ , Q 2 , Q ₃ , Q ₄ , Q ₅ , _{Q 6 ,} Q ₁₁ , Q ₁₂ ,
Q ₁₃ , Q ₂₁ , Q ₂₂ , Q _c ... MIS transistor, TC ₁ ,
TC ₂ , TC ₂₁ ...Tunnel capacitor.

Claims (1)

[Scope of Claims] 1. One memory cell is configured by pairing a volatile memory cell section and a nonvolatile memory cell section for saving storage information in the volatile memory cell section, and The memory cell section includes a capacitor section that stores an amount of charge according to the information to be stored, a first transistor that transfers the information in the capacitor section to the bit line, and a gate connected to the capacitor section. a second transistor that is turned on or off according to information stored in the capacitor section, and the nonvolatile memory cell section includes a third transistor whose gate is in a floating state; When writing information into the nonvolatile memory cell section, a write voltage is applied to one electrode of the first and second capacitors, and a gate of the third transistor that causes a tunnel effect between the electrodes. and the other electrode of the first capacitor, the gate of which is connected to the other electrode of the second capacitor and the second transistor, and the second transistor a fourth capacitor for changing the potential of the common connection point of the first and third capacitors depending on whether the capacitor is turned on or off;
and a fifth transistor connected between the third transistor and the capacitor section and made conductive when information in the nonvolatile memory cell section is recalled to the volatile memory cell section. A nonvolatile random access memory device characterized by: 2. The non-volatile random access memory device according to claim 1, wherein the capacitor section is constituted by the gate capacitance of a second transistor.