JPH0318275B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to semiconductor memories. [Technical Background of the Invention] Recently, semiconductor memories have been considered in which a plurality of bits, for example, two bits of information are stored in a memory cell made up of one transistor. By distinguishing between four types of transistor channel length, channel width, and transistor gate threshold voltage, it is possible to store two bits of information in one transistor, making it possible to store a large amount of information in a small memory cell size. ing. In other words, as shown in Table 1 below, the combinations of "0" and "1" stored in the two bits O ₁ and O ₂ are "00", "10", "11", and "01". It is a seed.

[Problems with background technology]

Conventional sense amplifiers and detection circuits for detecting column line potentials as described above have the disadvantage of slow data read speed because normal data is not output until a memory cell is selected and the column line potential stabilizes. It was hot. [Object of the Invention] The present invention has been made in order to eliminate the above-mentioned drawbacks, and provides a semiconductor that not only makes it possible to reduce the size of an IC (integrated circuit) chip, but also makes it possible to increase the speed of reading data from memory cells. The purpose is to provide memory. [Summary of the Invention] That is, the present invention stores multiple bits of data in one memory cell, and changes the potential of a column line connected to a selected memory cell to multiple potentials depending on the content of the stored data. In the semiconductor memory to be set, data is read by detecting differences in charging speeds of column lines due to differences in channel shapes of selected memory cells. Therefore, the operation of reading data for a plurality of bits from each memory cell can be performed quickly. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 is a diagram showing the principle of the same embodiment.
used in the semiconductor memory shown in Figure 2.
It is assumed that all MOS transistors are, for example, N-channel type. Memory matrix 8 includes a plurality of memory cell transistors _10ij . The gates of these transistors 10 _ij are word lines (row lines) 12
i, and its drain is connected to the data line (column line)
16j, and its source is grounded. These sources may be connected to a suitable negative power supply, but are typically connected to ground, which is a 0V circuit. For example, the transistors 10ij are formed to have different channel shapes (at least one of channel length and channel width) depending on the content of two bits of stored data, or are formed to have different gate threshold voltages depending on the stored data. One of VTH ₁ , VTH ₂ , VTH ₃ , VTH ₄ depending on the content of
is set to Each word line 12i of the matrix 8 is connected to a row decoder 14,
Each data line 16j of the matrix 8 is also connected to the source of a column gate transistor 18j of the N-channel enhancement mode MOS transistor. Each gate of these column gate transistors 18j is connected to a column decoder 20. Furthermore, the drains of these transistors 18j are commonly connected to the data detection point S. This detection point S is the depletion mode MOS load transistor 22.
is connected to the positive power supply VD (for example, +5V) through the source-drain path of the Column address data a0,0 is input to the decoder 20, but address data A0,0 corresponding to these data a0,0 is not input to the decoder 14. The detection point S corresponds to, for example, one of four channel widths, four channel lengths, or four gate threshold voltages VTH1, VTH2, VTH3, and VTH4 of the selected memory cell transistor 10ij. A detected voltage VS is generated.
In this way, by using four types of channel width, channel length, or gate threshold voltage,
Four types of the above-mentioned detection voltages VS appear. From then on,
The following will explain the threshold voltages in columns. The above threshold voltage is
The relationship is VTH1<VTH2<VTH3<VTH4, and each corresponds to the contents of the related 2-bit stored data D1 and D2. These expanded data D1, D2 and the above threshold voltages VTH1 to VTH4
The relationship between the two is shown in Table 2 below. For example, when distinguishing by channel length as shown in FIG. 1, VTH1 corresponds to the shortest channel length, and VTH4 corresponds to the longest channel length.

[Table] The potential VS at the detection point S is the threshold voltage of the selected memory cell transistor 10ij as described later.
Since it changes depending on VTH (or channel length or channel width), stored data D1 and D2 can be detected from the level of potential VS. This potential VS
are the first comparator 30 and the second comparator 40
and is input to the third comparator 50. These comparators 30, 40, 50 each have a first
comparison voltage level V1, second comparison voltage level V2,
A third comparison voltage level V3 is provided. The comparator 30 becomes logic “1” at VSV1,
The first comparison output E becomes logic “0” when VS>V1
Outputs 10. Similarly, comparator 40 is VS
It outputs a second comparison output E20 which becomes logic "1" at V2 and becomes logic "0" when VS>V2.
The comparator 50 outputs a third comparison output E30 which becomes logic "1" at VSV3 and becomes logic "0" when VS>V3. These comparison outputs E10, E20, and E30 are applied to selection logic circuit 60. This logic circuit 60
The address data A0, 0 corresponding to the row address data of the row decoder 14 is inputted to the row decoder 14. Here, when VSV1, output E10, E2
0, E30 becomes (1, 1, 1). At this time,
Regardless of A0,0, the circuit 60 outputs a gate output E40 of logic "0". This is the threshold voltage
From the memory cell transistor 10ij of VTH1,
A case is shown in which stored data of “logic 0” is read. When V1<VSV2, output E10, E20,
E30 becomes (0, 1, 1). At this time, A0
If = “1” then E40 = “0”, if A0 = “0”
E40 becomes “1”. This shows a case where 2-bit stored data corresponding to the address indicated by A0 is read out from the memory cell transistor 10ij having the threshold voltage VTH2. When V2<VSV3, the outputs E10, E20, and E30 become (0, 0, 1). At this time, E40="1" regardless of A0, 0
becomes. This shows a case where 2 bits of "logic 1" stored data is read out from the memory cell transistor 10ij having the threshold voltage VTH3. V3＜VS
When , the outputs E10, E20, E30 are 0, 0,
It becomes 0. At this time, if A0="1", E40="
If A0="0", E40="0".
This shows a case where 2-bit stored data is read out from the memory cell transistor 10ij with the threshold voltage VTH4. The output E40 of the selection logic circuit 60 is applied to an output buffer 70. When the chip select signal CS input to the buffer 70 is at logic "1", the output E40 is read out from the buffer 70 as read data E50. Here, the above-mentioned components 30 to 60 form a sense amplifier 80. FIG. 3 shows the temporal change in the detected potential VS due to charging of the data line 16 when, for example, the threshold voltage VTH of the selected memory cell transistor 10ij is taken as a parameter.As is clear from FIG.
The detection period of VS includes (i) transition period (before time TS,
dVS/dt≠0) (ii) Quiet period (dVS/dt after time TS
There are two types: dt~0). During this transition period, the potential VS
By detecting this, the readout time can be shortened. Also,
When detecting the potential VS during the quiescent period, the circuit of the memory device becomes simpler. In addition, in FIG. 3, the threshold voltages VTH1, VTH2,
Comparison voltages V1, V2, and V3 are shown to be higher than the static levels VS1, VS2, and VS3 of the detection voltage VS when reading the memory cell of VTH3, respectively. Of course, it may be set like this. However, this was done only for convenience.
If V1=VS1+V2=VS2 and V3=VS3, data reading will be performed at TS1 to TS3 before TS, and stored data will be detected during the transition period described above. FIG. 4a shows a semiconductor memory according to a more detailed embodiment of the present invention. used here
All MOS transistors are of N-channel type.
In FIG. 4a, the detection potential VS is detected during the transition period of FIG. 3 described above. The word line 12i includes a dummy cell transistor 120i,
Each gate of 122i and 124i is connected. These transistors 120i, 122i, 124
Each source of i is grounded. These transistors 120i, 122i, and 124i constitute a dummy cell array 128. transistor 120
The drain of i is connected to the dummy data line ₁₃₀₁ . The drain of transistor 122i is connected to dummy data line ₁₃₀₂ . transistor 1
The drain of 24i is connected to dummy data line ₁₃₀₃ . Each data line 16i is grounded through a drain-source path of a discharge transistor 24j. In addition, dummy data lines 130 ₁ , 13
0 ₂ and 130 ₃ are discharge transistors 126, respectively.
₁ , 126 ₂ , 126 ₃ drain/source paths to ground. Transistor 24j, 126
A discharge pulse φ1 is applied to the gates ₁ to 126 ₃ . Gate threshold voltage VTH of transistor 120i
11 is set so that VTH1<VTH11<VTH2. This can be achieved by setting the channel length L11 of the transistor 120i to L1<L11<L2. Here, L1 to L4 are each threshold voltage VTH1 to
This is the channel length corresponding to a transistor with VTH4. Similarly, transistors 122i, 12
The gate threshold voltages VTH22 and VTH33 of 4i are VTH2<VTH22<VTH3 and VTH3<
It is set so that VTH33<VTH<4.
This means that the channel lengths L22 and L33 of transistors 122i and 124i are L2<L22<L, respectively.
3. It can also be realized by setting L3<L33<L4. Alternatively, the equivalent resistance of the transistors 134 ₁ to 134 ₃ may be smaller than that of the transistor 26, and in this case, VTH1=VTH11,
It is also possible to set VTH2=VTH22 and VTH3=VTH33. Data line 16i is connected to detection point S via gate transistor 18j. This detection point S is connected to the positive power supply VD via the source-drain path of the enhancement mode MOS transistor 26. Dummy data lines 130 ₁ to 130 ₃ are connected to the sources of enhancement mode MOS transistors 132 ₁ to 132 ₃ , respectively. These transistors 132 ₁ to 132 ₃ are transistors 1
It has the same size as 8j. transistor 1
The drains of 32 ₁ to 132 ₃ are enhancement type.
It is connected to the sources of MOS transistors 134 ₁ to 134 ₃ . The drains of the transistors 134 ₁ to 134 ₃ and the gates of the transistors 132 ₁ to 132 ₃ are connected to the power supply VD. transistor 26,1
A charge pulse φ2 is applied to the gates 34 ₁ to 134 ₃ . These transistors 2
6,134 ₁ to 134 ₃ form a load circuit for charging the data line. The detection potential VS is the first comparator 30A, the second
The signal is input to a comparator 40A and a third comparator 50A. The first comparison signal VC1 generated at the source of the transistor ₁₃₄₁ is input to the comparator 30A. A second comparison signal VC2 produced at the source of transistor ₁₃₄₂ is input to comparator 40A. The third comparison signal VC3 generated at the source of transistor ₁₃₄₃ is input to comparator 50A. These comparators 30A, 40
Timing pulse φ3 is applied to A and 50A. After receiving this timing pulse φ3, the comparators 30A, 40A, 50A output the detected potential VS and the first to third comparison signals VC1, VC2, VC3.
The comparison results E10, 10, E20,
Output E20, E30, 30. FIG. 4b shows a circuit that generates pulses φ1 to φ3 in synchronization with a chip enable signal (chip operation signal). 5A to 5E show operation timing charts of the circuits of FIGS. 4a and 4b. The signal enables the entire memory IC chip including the configuration shown in FIG.
Specify whether to make it inoperable state. =“0”
The memory becomes operational. this signal
The CE is input to a negative edge trigger type monostable multivibrator (mono multi) 140. This monomulti 140 is triggered by the signal change point (time t10 in FIG. 5),
Pulse φ1 is generated for a predetermined time (time t ₁₀ to t ₁₂ in FIG. 5). This pulse φ1 is input to a negative edge triggered bistable multivibrator, for example, a flip-flop 142. This flip-flop 142 is triggered by the change point of pulse φ1 (time t12 in FIG. 5) and generates pulse φ2 (FIG. 5C). The pulse φ2 is delayed by the delay circuit 144 for a certain period of time (from time t ₁₂ in FIG.
t ₁₄ ) It is delayed and becomes pulse φ3. The circuits of FIGS. 4a and 4b operate as follows. That is, when data is read from the memory, it becomes ="0" (FIG. 5A). Then,
Pulse φ1 becomes logic "1" (FIG. 5B). The transistor 24j is turned on by the pulse φ1="1". Then, the data line 16j is discharged and becomes VS=0 (from time t10 to t1 in FIG.
2). Also, by φ1="1", transistor 1
26 ₁ to 126 ₃ are also turned on. Then, dummy data lines 130 ₁ to 130 ₃ are also discharged, and VC1 to VC
3 becomes 0 (Figure 5, time t10-t12).
The time interval t10 to t12 is preferably as short as possible to completely discharge the data line 16j and the dummy data lines 130 ₁ to 130 ₃ . This time interval t
If 10 to t12 are long, the reading time from the start of reading t10 to the end of reading t14 will also become long. When the pulse φ1 returns to logic "0", φ2 becomes "1" (FIGS. 5B and 5C). With φ1="0", the transistors 24j, 126 ₁ to 126 ₃ are turned off again. At the same time, transistors 26, 134 ₁ to 134 ₃ are turned on due to φ2="1". Then, the data line 16 selected by the decoder 20
Then, charging of the dummy data lines 130 ₁ to 130 ₃ is started (time t12 in FIG. 5). data line 1
6 and dummy data lines 130 ₁ to 130 ₃ and when φ3 becomes “1” (Fig. 5, time t1
4) Comparators 30A, 40A, and 50A compare their respective inputs. This comparison is data line 1
6 and dummy data lines 130 ₁ to 130 ₃ are being charged at time t14. This is an important feature of the circuits of FIGS. 4a and 4b. Now selected memory cell transistor 10ij
Assuming that the threshold voltage of is VTH1, at time t
14, VS<VC1<VC2<VC3. At this time, E10, E20, and E30 become 1, 1, 1, and "logic 0" is read out regardless of address data A0, 0. When the threshold voltage of the selection transistor 10ij is VTH2, VC1<VS<VC2<VC3
becomes. In this case, the outputs E10, E20, E30
are 0, 1, and 1, and 2-bit data "logic 0" or "logic 1" distinguished by address data 0 is read out. selection transistor 1
When the threshold voltage of 0ij is VTH3, VC1<VC2<
VS＜VC3. In this case, the outputs E10, E2
0, E30 become 0, 0, 1, and "logic 1" is read out regardless of address data A0, 0. The threshold voltage of the selection transistor 10ij is VTH4
When , VC1<VC2<VC3<VS. in this case,
Outputs E10, E20, and E30 become 0, 0, 0, and 2-bit data "logic 1" or "logic 0" separated by address data A0 is read out. Delay time t in the delay circuit 144 of FIG. 4b
The shorter the period 12 to t14 is, the shorter the time for reading stored data is. However, as the delay time becomes shorter, the level difference between VS, VC1 to VC3 becomes smaller, so the comparators 30A and 40
A, data detection at 50A becomes difficult. Therefore, it is preferable to minimize the delay times t12 to t14 within a range where the level comparison operations by the comparators 30A, 40A, and 50A can be performed reliably. In this way, the read speed can be further increased. FIG. 6 shows a specific circuit example of the comparator 30A shown in FIG. 4a. Comparator 40
A and 50A may have the same configuration as in FIG. 6, but the comparison signal inputs must be set to VC2 and VC3, respectively.
Detection potential VS is applied to the gate of enhancement mode MOS transistor 150. The drain of transistor 150 is connected to the gate and source of depletion mode MOS transistor 152, and its source is connected to the source of enhancement mode MOS transistor 154. The first comparison signal VC1 is applied to the gate of this transistor 154. Further, the drain of this transistor 154 is connected to the gate and source of a depletion mode MOS transistor 156. The drains of transistors 152 and 156 are connected to the positive power supply VD. The sources of transistors 150 and 154 are connected to the drain of depletion mode MOS transistor 157. The gate and source of this transistor 157 are the enhancement mode MOS transistor 1.
58 drain-source paths to ground. Timing pulse φ3 is input to the gate of transistor 158. The drain of the transistor 150 is connected to the gate of an enhancement mode MOS transistor 160. The source of this transistor 160 is connected to corresponding drains and gates of enhancement mode MOS transistors 162 and 164. The gate of transistor 162 and the drain of transistor 164 are connected to the source of enhancement mode MOS transistor 166. The drains of transistors 160 and 166 are connected to power supply VD. transistor 16
2 and 164 sources are in enhancement mode
It is grounded through the drain-source path of MOS transistor 168. Timing pulse φ3 is input to the gate of transistor 168. The first comparison output E from the drain of the transistor 162
10 is output. Output 10, which is an inverted signal of output E10, is output from the drain of transistor 164.
is output. Here, the transistor 15
0,154 may be a depletion mode MOS transistor. A comparator 40 having a configuration similar to that shown in FIG. 6 above.
A, 50A outputs E20, 20, E3
0.30 is obtained. In the comparator 30A shown in FIG. 6, when the timing pulse φ3=“0”, the output E10=10=“1”. If VS<VC1 when timing pulse φ3 becomes “1”, E10 becomes “1” and 10 becomes “0”. VS＞VC1
If so, E10="0" and 10="1". Similarly, in the comparator 40A having the same configuration as in FIG. 6, when the timing pulse φ3="1", VS
<For VC2, E20=1, 20=0, VS>
For VC2, E20="0" and 20="1". The same goes for the comparator 50A, if VS<VC3 when timing pulse φ3=“1”, E30=
“1”, 30=0, and if VS>VC3, E30=
0,30=1. Figure 7 shows the output E of comparators 30A and 40A.
10 and E20 to synthesize the first stored data D1 (Table 2), or a first selection logic circuit 60A (which is equivalent to a part of the selection logic circuit in FIG. 2). The outputs E10 and E20 are input to the first and second input terminals of the NOR gate 200. The output E200 of this gate 200 is converted into an inverted output E202 by an inverter 202. Output E20
2 is applied to the gate of enhancement mode MOS transistor 204. The source of this transistor 204 is grounded, and its drain is connected to the source of a depletion mode MOS transistor 206. The output E200 is input to the gate of this transistor 206. Enhancement mode on the drain of transistor 206
It is connected to the positive power supply VD through the source-drain path of the MOS transistor 208. An output enable signal OE is input to the gate of the transistor 208. The drain of transistor 204 is grounded through the drain-source path of enhancement mode MOS transistor 210. The gate of the transistor 210 has an inverted output enable signal.
OE is entered. These signals OE, are set to OE= when enabling the logic circuit 60A.
“1”, = “0”. The above output E200 is enhancement mode
Applied to the gate of MOS transistor 212.
The source of this transistor 212 is grounded, and its drain is connected to the source of a depletion mode MOS transistor 214. The output E202 is input to the gate of this transistor 214. The drain of transistor 214 is connected to power supply VD through the source-drain path of enhancement mode MOS transistor 216. The gate of transistor 216 has a signal OE.
is input. The drain of the transistor 212 is the enhancement mode MOS transistor 21
It is grounded through the drain-source path of 8.
A signal is input to the gate of the transistor 218. An output E212 derived from the drain of transistor 212 is connected to the gate of enhancement mode MOS transistor 220. The source of transistor 220 is grounded, and its drain is connected to enhancement mode MOS transistor 2.
It is connected to the power supply VD through 22 source-drain paths. An output E204 derived from the drain of the transistor 204 is input to the gate of the transistor 222. transistor 220
The first stored data D1 is derived from the drain of. Figure 8 shows the output E of comparators 30A and 50A.
10 and 30 to synthesize the second stored data D2 (Table 2), or a second selection logic circuit 60B (equivalent to a part of selection logic circuit 60 in FIG. 2). The outputs E10 and E30 are input to the first and second input terminals of the NOR gate 300. Output E300 of gate 300 is converted by inverter 302 into an inverted output E302. Output E30
2 is applied to the gate of enhancement mode MOS transistor 304. The source of this transistor 304 is grounded, and its drain is connected to the source of a depletion mode MOS transistor 306. The output E300 is input to the gate of this transistor 306. The drain of transistor 306 is in enhancement mode.
It is connected to the positive power supply VD through the source-drain path of the MOS transistor 308. An output enable signal OE is input to the gate of the transistor 308. The drain of transistor 304 is grounded through the drain-source path of enhancement mode MOS transistor 310. The gate of the transistor 310 has an inverted output enable signal.
OE is entered. These signals OE, are set to OE= when enabling the logic circuit 60B.
“1” and OE="0". The output E300 is in enhancement mode.
Applied to the gate of MOS transistor 312.
The source of this transistor 312 is grounded, and its drain is connected to the source of a depletion mode MOS transistor 314. The output E302 is input to the gate of the transistor 314. The drain of this transistor 314 is connected to the power supply VD through the source-drain path of an enhancement mode MOS transistor 316. A signal OE is input to the gate of the transistor 316. The drain of transistor 312 is an enhancement mode MOS transistor 318
grounded through the drain-source path of the A signal is input to the gate of the transistor 318. Output E312 derived from the drain of transistor 312 is in enhancement mode.
Connected to the gate of MOS transistor 320.
The source of transistor 320 is grounded, and its drain is connected to the power supply through the source-drain path of enhancement mode MOS transistor 322.
Connected to VD. An output E304 derived from the drain of the transistor 304 is input to the gate of the transistor 322. Second stored data D2 is derived from the drain of the transistor 320.

〔Effect of the invention〕

As explained above, according to the present invention, data for multiple bits can be stored in one memory cell, and the chip size can be reduced.
Furthermore, since the data is read by detecting the difference in the charging speed of the data line due to the difference in channel length or channel width of the selected memory cell, the readout speed can be greatly improved. Further, the present invention provides the main body memory cell array 8 and the dummy cell array 128 in close proximity to each other as shown in FIG. 4a, and the row lines 12 ₁ , 12 ₂ , . . . Therefore, even if noise appears on the row lines, the main body memory cells and dummy cells are equally affected, the main body memory cells and dummy cells are equally affected, and the column line potential on the main body side and the dummy column line potential are equally affected. Therefore, the relative potential relationship remains unchanged and malfunctions (especially in potential comparison) do not occur. Furthermore, since the dummy cell is provided adjacent to the main body memory cell, the length and capacitance of the column line of the main body memory cell and the column line of the dummy cell are very similar, thereby preventing malfunctions as described above.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a channel shape of a memory cell transistor of a semiconductor memory that stores multi-bit data, FIG. 2 is a principle diagram showing the basic configuration of a semiconductor memory according to the present invention, and FIG. A diagram showing an example of the relationship between the detected potential VS and time for the data line shown in the figure, FIG. Block circuit diagram for creating pulses φ1 to φ3 in FIG. 4a from signals, FIGS. 5A to E
is an operation time chart for explaining the circuits in FIG. 4a and b, and FIG. 6 is the comparator 3 in FIG. 4a.
A detailed circuit diagram of 0A, FIGS. 7 and 8 are block diagrams of logic circuits for extracting predetermined data D1 and D2 from the output of the comparator, and FIG. 9a shows address data A i from address data A _{i '.} , Fig. 9b is a block diagram of the circuit that produces _i .
Detailed circuit diagram of the row decoder shown in Figure 10
The figure is a block diagram of a circuit that generates pulses B i, _i from data A _i , _i , Figure 11 is a block diagram of a circuit that generates pulses φ1 from pulses B _i , _{i, and} Figure 12 is a block diagram of a circuit that generates pulses φ1 from pulses φ1 to pulses φ2, φ3. 13A-M and 14A-M are time charts for explaining the operation of the circuits shown in FIGS. 9a-12, respectively. FIG. 7 is a configuration explanatory diagram showing a main part of still another embodiment of the invention. 8...Memory matrix, 10...Memory cell, 1
6,130...Data line (column line), 12...Word line (row line), 30,30A,40,40A,50,50
A... Comparator, 60, 60A, 60B,... Selection logic circuit, 70... Buffer, 80... Sense amplifier, 26, 134... Charging transistor, 24,
126...discharge transistor, VS...detection potential,
V1, V2, V3, VC1, VC2, VC3...Comparison potential, φ1~φ3...Pulse, D1, D2...Output data, a0~ai,0~, A0~Ai,0~
Ai, Ai', B0~Bi, 0~...address data, CE...chip enable signal.

Claims (1)

[Scope of Claims] 1. A row line, a memory cell selectively driven by the row line, a column line receiving data from the memory cell, and a first load circuit connected to the column line; a dummy memory cell provided adjacent to the memory cell and selectively driven by the row line;
A dummy column line that receives data from this dummy memory cell, a second load circuit connected to this dummy column line, and a dummy column line that detects the difference in speed of change between the potential of the column line and the dummy column line, and The memory cell includes a plurality of sense amplifiers for detecting a line potential, and the memory cell stores a plurality of bits of data, and sets the potential of the column line to a potential corresponding to the data stored in the memory cell. In order to set the potential of the dummy column line to the voltage between the adjacent potentials of each set column line potential, a plurality of dummy column lines are provided, and each of these dummy column lines adjusts the potential between the adjacent potentials respectively. A semiconductor memory characterized in that a plurality of bits of data stored in the memory cell are detected by differentiating dummy cells connected to each of the dummy column lines so as to output the data. 2. The semiconductor memory according to claim 1, further comprising means for controlling the load circuit and the sense amplifier by a pulse signal synchronized with a change in address data or a chip operation signal. 3. The semiconductor according to claim 1, wherein the memory cell is composed of one MOS transistor, and is configured to store 2 bits of information by changing its channel length into four types. memory. 4. Claim 3, wherein the 2-bit information is data of two addresses.
Semiconductor memory described in section. 5. The semiconductor memory according to claim 3, wherein the two bits of information are data at the same address but different output destinations.