JPH0318330B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a silicon single crystal semiconductor device including:
The present invention relates to a silicon single crystal semiconductor device in which crystal defects are not present on the main surface of a silicon single crystal substrate forming the semiconductor device.

Conventionally, silicon single crystal wafers used in silicon single crystal semiconductor devices have been supplied as dislocation-free single crystal wafers, regardless of the Cz method or the Fz method. Impurities (mainly oxygen and carbon) cause crystal defects such as micro defects, stacking faults, and dislocations. These crystal defects have a negative effect on the semiconductor device (large leakage current) and reduce the yield of the semiconductor device.

Various methods have been tried in the past to prevent the introduction of crystal defects during the manufacturing process of semiconductor devices. For example, there is a method in which a crushing layer is provided on the opposite side of the main surface on which the semiconductor device is formed of a silicon single crystal substrate, and heavy metal impurities and the like on the main surface on which the semiconductor device is formed are absorbed by the strain field of this crushing layer. However, the method using the fracture layer requires a step of introducing the fracture layer, and the fracture layer becomes a source of dislocations that penetrate to the main surface on which the semiconductor device is formed, giving an adverse effect. A recently proposed method is called intrinsic gettering, in which a silicon single crystal substrate is heat-treated at an appropriate temperature in advance to precipitate oxygen and carbon impurities in the silicon single crystal, and these precipitates are removed. This is a method of absorbing heavy metal impurities on the main surface of a semiconductor device. However, with this method, the silicon single-crystal substrate must be heat-treated at a special temperature for a long time, and crystal defects may occur due to the relationship between the oxygen and carbon concentrations in the silicon single-crystal substrate and the semiconductor device manufacturing heat treatment. There is a drawback that it makes you The present invention eliminates the above drawbacks and provides a silicon single crystal device in which no crystal defects exist on the main surface on which the semiconductor device is formed.

The present invention will be explained in detail below using the drawings.

P-type 1 containing boron formed by Cz method
~5Ωcm diameter 76mm silicon single crystal substrates were formed with oxygen concentrations of 22~24ppm, 30~32ppm, and 36~38ppm, respectively, and silicon single crystals were heated at 600°C, 800°C, and 2°C, respectively.
Heat treated in a nitrogen atmosphere for 1 hour, slice lap mirror polished, and then heat treated in an oxygen gas atmosphere at 1100°C for 30 hours. After this heat treatment, the silicon single crystal substrate is selectively etched to detect crystal defects. FIG. 1 shows the relationship between defect density and interstitial oxygen concentration in a cross section of a silicon single crystal substrate. The solid line indicates the case where the donor killer treatment temperature was 600℃ in a _2HN2 atmosphere.
The dotted line shows the case where the temperature was 800℃. As can be seen from FIG. 1, the defect density in the cross section of a silicon single crystal substrate varies considerably depending on the interstitial oxygen concentration of the silicon single crystal substrate and the donor killer treatment temperature. That is, depending on the initial state of the silicon single crystal substrate,
Even if the subsequent heat treatment is the same, the crystallinity of the silicon single crystal substrates is completely different. On the other hand, the relationship between the minute defects and stacking faults on the surface of the silicon single crystal substrate and the defect density in the cross section of the silicon single crystal wafer is shown in FIG. The solid line is the microdefect density and the dotted line is the stacking fault density. As shown in Figure 2, the defect density in the cross section of a silicon single crystal wafer is 5×10 ⁴ cm ^-2
It has been experimentally confirmed that if it exceeds this limit, stacking defects (line defects) occur frequently, and when devices are formed using such single crystal wafers, the defective rate of device characteristics increases. Experiments have shown that the defective rate of device characteristics is also affected by minute defects, and that the defective rate of device characteristics due to minute defects increases when the defect density of the cross section of a single crystal wafer is 7×10 ³ cm ^-2 or less. It turned out to be true. Furthermore, from FIG. 2, it can be seen that when the defect density in the cross section of a single crystal wafer is less than 7×10 ³ cm ⁻² , micro defects occur frequently. The conclusion drawn from Figures 1 and 2 is that Figure 1 shows the various conditions of the silicon single crystal substrate (e.g. oxygen concentration and final heat treatment).
The density of crystal defects in the cross section of a silicon single crystal substrate changes depending on the However, the crystal defect density on the main surface of the silicon single crystal semiconductor device shown in FIG. determined uniquely. Therefore, in a silicon single crystal semiconductor device in which no crystal defects exist on the main surface where the silicon single crystal semiconductor device is formed, the crystal defect density in the cross section of the silicon single crystal semiconductor device is 7×10 ³ cm ^-2 to 5×
The device is in the range of 10 ⁴ cm ^-2 .

[Brief explanation of drawings]

Figure 1 is a diagram showing the relationship between crystal defect density and interstitial oxygen concentration in a cross section of a silicon single crystal substrate. In the figure, the broken line indicates a silicon single crystal heat-treated in a nitrogen atmosphere at 80°C for 2 hours before slicing, and the solid line indicates before slicing
This is about a silicon single crystal heat-treated at 600°C for 2 hours in a nitrogen atmosphere. Figure 2 is a diagram showing the relationship between the crystal defect density on the silicon single crystal semiconductor device forming surface and the crystal defect density in the cross section of the silicon single crystal substrate. The broken line shows the stacking fault (line defect) density.

Claims (1)

[Claims] 1. In a silicon single crystal semiconductor device, the crystal defect density of the silicon single crystal cross section is in the range of 7 × 10 ³ cm ^-2 to 5 × 10 ⁴ cm ^-2 to reduce the crystal defect density of the main surface of the device formation. A silicon single crystal semiconductor device characterized by: