JPH0318371B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delayed pulse generation circuit for a semiconductor integrated circuit.

In general, delayed pulses have a delay time that depends on power fluctuations.
Performance is required to not change due to temperature fluctuations. However, when building it inside an integrated circuit, it has to be kept as small as possible, and due to constraints such as the number of elements, compensation for power supply fluctuations and temperature fluctuations has not been considered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a delay pulse generation circuit whose delay time does not change little with respect to power supply fluctuations and temperature fluctuations.

This will be explained below using the drawings.

FIG. 1 is a logic diagram of a delayed pulse generation circuit.
It consists of a two-input NOR gate (hereinafter referred to as NOR gate) 3 and two in-phase gates (hereinafter referred to as AMP gate) 1 and 2. The number of AMP gates may be one or more may be connected as required.

FIG. 2 shows operating waveforms of the delayed pulse generation circuit of FIG. 1. When a high level (hereinafter referred to as H) is applied to the input terminal IN, the output of the NOR gate 3 is at a low level (hereinafter referred to as L). When the input terminal changes from H to L, AMP gate 1 slowly transitions from H to L. When the input terminal falls to the threshold of AMP gate 2 (hereinafter referred to as V _TH ), the output of AMP gate 2 slowly changes as with AMP gate 1. H to L
to move to.

When the voltage drops to _VTH of NOR gate 3, the output of the NOR gate becomes H.

Input terminal IN changes from H to L and AMP gate 1
The delay time for the output of AMP gate 2 to fall to V _TH of AMP gate 2 is T ₁ , and from this time the output of AMP gate 2 falls to V _TH of NOR gate 3.
If the delay time is T ₂ , the delay time T ₄ of the delayed pulse generation circuit is T ₁ + T ₂ and the delay time of NOR gate 3.
It is obtained by the sum of T ₃ .

The delay time T ₃ of NOR gate 3 is very small compared to T ₁ and T ₂ , so if we ignore it, the delay time T ₄ will be
It can be represented by T ₁ + T ₂ .

The less the delay time T ₄ changes due to power supply fluctuations and temperature fluctuations, the better the performance of the delay circuit can be said.

AMP gates 1 and 2 create the delay time. The present invention focuses on AMP gates.
The following explanation focuses on the AMP gate.

Figure 3 shows the logic diagram in Figure 1 as a low-power shotgun.
TTL (transistor, transistor, logic circuit)
It is a conventional equivalent circuit diagram realized by.

Although the equivalent circuit diagrams of AMP gates 1 and 2 and NOR gate 3 are each indicated by dotted lines, the explanation will focus on AMP gate 1.

The configuration of the AMP gate 1 will be explained.

The base of the input gate PNP transistor 21 is connected to the input terminal IN, the collector is connected to the ground potential (hereinafter referred to as GND), the emitter is connected to the power supply Vcc via the resistor 11, and the anode of the level shift diode 31 is connected to the input terminal _IN . It is connected to the. The anode of the level shift diode 32 is connected to the cathode of the level shift diode 31, and this cathode is connected to the base of the transistor 22 and, at the same time, to GND via the resistor 12. The emitter of transistor 22 is GND
The collector is connected to the power supply via resistor 13.
It is connected to V _cc and at the same time to the base of transistor 23 .

The emitter of the transistor 23 is connected to GND, the collector is connected to the power supply _Vcc via the resistor 14, and further connected to the base of the transistor 26.

Transistors 26 and 27 are Darlington connected, and the collectors are connected to the power supply via a current limiting resistor 18.
It is connected to _Vcc , and the base and emitter of the transistor 27 are connected through a resistor 17. It is connected from the power supply V _cc to the base collector of the transistor 25 via the resistor 15, and further connected to the base of the transistor 24, the emitters of the transistors 24 and 25 are connected to GND, and the collector of the transistor 24 is connected to the emitter of the transistor 27. is,
Furthermore, the cathode of a diode 33, which is actually used as a capacitor, is connected. The anode of diode 33 is connected to the emitter of transistor 23.

The resistor 15 and the transistors 24 and 25 constitute a constant current circuit, and the current flowing through the resistor 15 is approximately equal to the collector current of the transistor 24.
(However, it is assumed that the transistors 24 and 25 are transistors of the same size and performance under the same conditions, and have the same emitter area.) Next, the operation of this AMP gate 1 will be explained.

In a steady state when L is applied to the input terminal IN, the current flowing through the resistor 11 flows to the PNP transistor 21, and the current does not flow to the base of the transistor 22 through the level shift diodes 31 and 32, and the transistor 22 is cut off (hereinafter referred to as OFF). ). The current flowing through the resistor 13 flows to the base of the transistor 23, the transistor 23 is in a conductive state (hereinafter referred to as on), and the collector potential is equivalent to about 0.3V. Therefore, transistors 26 and 27 are turned off, and the output potential of AMP gate 1 is reduced to about 0.3V. In a steady state where H is applied to the input terminal IN, the current flowing through the resistor 11 does not flow through the PNP transistor 21, but instead flows through the level shift diodes 31, 3.
The current flowing through resistor 13 flows to the collector of transistor 22 and does not flow to the base of transistor 23, and transistor 23 is turned off.

The collector of the transistor 23 is raised to the power supply voltage _Vcc by the resistor 14, and the emitter of the Darlington-connected transistor 27 is 2VBE ^~ _- from _Vcc .
The potential has dropped by 2VF (VBE is the base-emitter forward voltage), and it is approximately 3.5V when the power supply voltage _Vcc is 5V. At this time, the diode 33 is reverse biased and charged.

When the input terminal IN becomes H or L, the transistor 22 is turned off at high speed, the transistor 23 is similarly turned on, and the off-buffer transistors 26 and 27 are turned off. The charge stored in the diode 33 starts discharging at a constant current that is approximately equal to the collector current of the transistor 24, or in other words, the current flowing through the resistor 15. The threshold of the next stage AMP gate 2 is
Considering that VTH≒VF, the discharge time of AMP gate 1, or in other words, the delay time _T1, can be expressed by the following formula.

T ₁ ≒ C・R ₁₅・V _cc −2VBE−VTH/V _cc −VBE≒C・R ₁₅・ (V _cc −3VF/V _cc −VF) C: Equivalent capacitance of diode 33, R ₁₅ : Equivalent capacitance of resistor 15 The delay time T ₁ will fluctuate as the resistance value and, therefore, the power supply fluctuates.

Furthermore, since the resistance 15, VBE, and VTH vary with temperature, the delay time varies greatly.

Figure 4 shows the circuit of the present invention in a low power
FIG. 2 is a circuit connection diagram of an embodiment realized using TTL.

A clamp circuit 4 has been added, and some other points have changed.

The emitter of the transistor 23 is connected to GND, the collector is connected to the power supply _Vcc via the resistor 14, and further connected to the base of the charging transistor 28, the collector of the charging transistor 28 is connected to the power supply Vcc, and the collector is connected to the power supply _Vcc through the resistor 14. is transistor 24
connected to the collector. transistor 24
The emitter of is connected to GND via resistor 16,
The base is connected to the base and collector of a transistor 25 whose emitter is connected to GND, and at the same time is connected via a resistor 15 to the emitter of a transistor 29 constituting the clamp circuit 4. Transistor 29 whose collector is connected to the power supply V _cc
The base of is connected to the power supply V _cc via a resistor 19 and at the same time to the anode of a diode 35, and the diodes 35, 36, 37, 38, and 39 are connected in series in sequence, and the cathode of the diode 39 is connected to GND. They are connected to form a clamp circuit 4. The base of transistor 28 is diode 3
The cathode of diode 34 is connected to the anode of diode 36 to clamp the high level.

The cathode of the capacitive diode 33 is connected to the collector of the transistor 24, and the anode is connected to the base of the transistor 23. (Diode 3
Although the anode No. 3 may be connected to GND, it is the same as the conventional example for convenience of explanation here. ) When the input terminal IN is H, the output of AMP gate 1 (A
Point) H is the clamp diode 34, 36, 37,
Clamped at 38, 39 5VF−VBE4VF
(approximately 2.9V). Further, the emitter of a clamped transistor 29 is connected to the resistor 15 of the constant current circuit, and 5VF-VBE4VF (approximately 2.9V) is applied thereto. The delay time T ₁ of this circuit is T ₁ =C·VOH−VTH/IC≈C3VF/IC where C is the capacitance of the diode 33, IC is the collector current of the transistor 24, and VOH is the high level output voltage. The discharge current is the transistor 24
With a collector current of IC≒3VF/ _R15 , _R15 is the resistance value of resistor 15.

Therefore, since T ₁ ≈C·R ₁₅ , it can be seen that the delay time does not change with respect to power supply fluctuations.

Since the resistance created in the integrated circuit changes with temperature, _R15 has temperature dependence, but if the transistors 24, 25 and resistor 16 are selected appropriately, the apparent
The same effect as R ₁₅ does not change with temperature can be obtained. To explain, transistor 2
If you change the emitter area of 4 and 25, the VBE of the transistor with a larger emitter area will be higher for the same current.
The collector current of the transistor 24 can be corrected for temperature fluctuations by taking advantage of the large temperature dependence of . In other words, the current flowing through the resistor 15 will decrease as the temperature rises (for example, if the resistance becomes larger), but by making the emitter area of the transistor 24 larger than the area of the transistor 25, the current flowing through the resistor 15 will decrease due to the rise in temperature.
The VBE of transistor 4 tends to become smaller than the VBE of transistor 25. This can be corrected because the collector current of the transistor 25 moves in the direction of increasing by the difference that VBE becomes smaller.

Therefore, a very effective delay pulse generation circuit is created in which the delay time T ₁ and hence the delay time T ₄ do not vary with power supply and temperature fluctuations. In addition, AMP
Although only the gate has been described, when used as an inverter gate, for example, by removing the phase inversion transistor 22 and the resistor 13 and connecting the base of the transistor 23 to the cathode of the level shift diode 32, it can be used as an inverter gate. (The anode of the capacitor diode 33 is
Connect to GND. ) Even in this case, using the time when the output of the inverter gate changes from H to L,
By passing the input signal and the signal passed through the inverter through a NAND gate, it is possible to create a pulse generation circuit with a constant L time.

[Brief explanation of the drawing]

Figure 1 is a logic diagram of the delayed pulse generation circuit, Figure 2 is a diagram showing the operating waveforms of the delayed pulse generation circuit, and Figure 3 is a diagram showing the operating waveforms of the delayed pulse generation circuit.
FIG. 4 is a circuit connection diagram showing an example of a conventional delayed pulse generation circuit realized using a low power shot TTL, and FIG. 4 is a circuit connection diagram showing an embodiment of the present invention realized using a low power shot TTL. 1, 2...AMP gate, 3...NOR gate, clamp circuit, 4, 11, 12, 13, 14, 15,
16, 17, 18, 19...Resistor, 21...PNP transistor, 22, 23, 24, 25, 26, 2
7, 28, 29...NPN transistor, 31, 3
2... Level shift diode, 33... Diode for creating junction capacitance, 34, 35, 36, 3
7, 38, 39...clamp diode.

Claims (1)

[Claims] 1. In a delay pulse generation circuit having an in-phase gate circuit that receives an input signal and a gate circuit that generates a delayed pulse based on the input signal and an output signal of the in-phase gate circuit, the in-phase gate circuit has a It has a charging transistor connected to it, a discharging transistor connected to the output point, and a clamp circuit that clamps the potential of the output point, the collector of which is connected to one end of the power supply, and the base of the clamp circuit that is connected to one end of the power supply. a clamping transistor connected to one end of a power supply via a first resistor; a first diode circuit having at least one diode connected to the base of the clamping transistor; and a second diode circuit having a series connection of a plurality of diodes connected between the first diode circuit and the other end of the power supply.
The connection point with the diode circuit is connected to the base of the charging transistor via another diode, the emitter of the clamping transistor is connected to the base of the discharging transistor via a resistor, and the discharging transistor is connected to the base of the discharging transistor via a resistor. A delay pulse generation circuit characterized by having a temperature compensation means for resistance.