JPH0318774B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PLL circuit, and more particularly to a PLL circuit in which a PLL loop is provided with a voltage-controlled oscillator that can change the free-running frequency.

[Conventional technology]

As shown in FIG. 1, a conventional PLL circuit receives a reference signal _fr from an input signal generating circuit (not shown) such as a VFO through a terminal 1. reference signal
f _r is outputted from terminal 2 as oscillation signal f _p via phase comparator 3 , low-pass filter 4 , and voltage-controlled oscillator 5 . Reference signal f _r input from terminal 1
The frequency range of is limited by the minimum oscillation frequency and maximum oscillation frequency of the voltage controlled oscillator 5. When the error signal V _i output from the low-pass filter 4 to the voltage-controlled oscillator 5 is zero, the voltage-controlled oscillator 5 oscillates at a free-running frequency. The difference between the frequency of the reference signal f _r and the free-running frequency determines the level of the error signal V _i . When the feedback signal f _d (oscillation signal f _p in the example of FIG. 1) fed back from the voltage controlled oscillator 5 to the phase comparator 3 matches the frequency and phase of the reference signal _fr , it is said to be in a locked state. When it is desired to match the frequency handled by the PLL circuit with the frequency range of the reference signal f _r , a mixer (not shown) is installed in the previous stage to convert the frequency to the desired frequency. The frequency change width of the reference signal f _r cannot be expanded by conversion.

As shown in FIG. 2, there is also an application method in which the reference signal f _r ' is generated by a reference signal generator (not shown) and inputted to the terminal 1. In this example, the frequency of the reference signal f _r ' does not change. When the free-running frequency of the voltage controlled oscillator 5 is divided by the programmable counter 7 and the frequency and phase of the feedback signal f _d and the reference signal f _r ' match, the error signal V _i approximates zero. When the frequency division ratio is changed, the level of the error signal V _i changes correspondingly. Frequency division ratio information for determining the frequency division ratio of the programmable counter 7 is formed by a frequency division ratio setting circuit 8. The frequency division ratio information is usually organized in a binary mode, and by decoding it, the frequency of the oscillation signal f _p can be found. In order to eliminate the frequency difference between the feedback signal f _d and the reference signal f _r ', a tracking time related to the feedback loop characteristics determined by the time constant of the low-pass filter 4 is required.
This time is called lockup time. Naturally, as the level range of the error signal V _i increases, the lockup time increases. The length of lockup time is highly important from the viewpoint of the overall design goal of a system such as a wireless communication device incorporating a PLL circuit. To shorten the lockup time, the voltage at terminal 6 of the voltage controlled oscillator 5 is set in advance to the oscillation signal _f by using the frequency division ratio information generated by the frequency division ratio setting circuit 8, that is, the frequency information of the oscillation signal fp. It is preset to a level that approximates the error signal V _i of frequency _p .

Another design objective for PLL circuits is the carrier noise ratio (hereinafter referred to as C/N). Each component and circuit of the PLL circuit, such as the phase comparator 33, low-pass filter 4, and voltage-controlled oscillator 5, has an additional effect on the signal being handled due to the noise figure of each part, mutual interference, drift due to temperature and power fluctuations, and operating characteristics. Generates noise. Especially in the voltage controlled oscillator 5,
Since the free-running frequency is locked by the error voltage ΔV _i , the changing frequency Δf _p of the oscillation signal f _p has non-periodicity and asymmetrical properties, and the C/N tends to deteriorate. In order to improve the C/N, it is sufficient to reduce the changing frequency Δf _p with respect to the changing voltage ΔV _i , that is, to lower the sensitivity of the voltage controlled oscillator 5. When the sensitivity of the voltage controlled oscillator 5 is lowered, the error signal V _i and the oscillation signal
As the operating curve of f _p changes from the a curve to the b curve shown in Figure 3, the oscillation frequency variation range narrows from oscillation frequencies ₁ to ₄ to ₂ to _{5 3} , corresponding to the variation range of the error signal _{V1 to} V2. . Since the oscillation frequency change range depends on the free-running frequency, if a plurality of free-running frequencies can be set corresponding to the frequency of the oscillation signal f _p , the C/N can be improved while maintaining the overall oscillation frequency. Therefore, in order to activate the reactance element built in the voltage controlled oscillator 5 shown in FIG.
A circuit has been proposed in which A ₁ , A ₂ . . . are connected to the voltage controlled oscillator 5 via connections X ₁ , _{X 2} . This circuit generates a free-running frequency corresponding to frequency information by activating a reactance element.

In order to control the voltage controlled oscillator 5 whose free-running frequency changes by the above-mentioned reactance connection using frequency information, predicted frequency information such as the division ratio setting circuit 8 that forms the frequency information is required. The circuit of FIG. 1 in which no information is obtained has the disadvantage that the voltage controlled oscillator 5 cannot be controlled.

[Problem to be solved by the invention]

The present invention has been made in view of the above points, and
The purpose of the present invention is to provide a PLL circuit that is built into a system such as a wireless communication device, eliminates spurious signals from signals such as VFO, and improves the carrier-to-noise ratio.

[Means to solve the problem]

The present invention provides a voltage controlled oscillator whose free running frequency changes by activating a reactance element. It also includes an error signal level range determining means for determining when the error signal has a level outside a predetermined range, and a configuration that connects the reactance element to the voltage controlled oscillator when the error signal goes outside the predetermined range.

〔Example〕

FIG. 4 is a block diagram including a partial circuit diagram of a PLL circuit showing one embodiment of the present invention. FIG. 4 will be explained. In the figure, 9 has a voltage controlled oscillator, 12 has an error signal level range discriminator, and a reactance switch 16.
A feedback loop to the phase comparator 3 is formed via the -Y' connection.

The error signal level range discriminator 12 includes a lower limit comparator 13, an upper limit comparator 14, and a comparison voltage 15. low pass filter 4
The output side of is connected to terminals 9a and 12c of voltage controlled oscillator 9 and error signal level range discriminator 12, respectively. A terminal 12c of the error signal level range discriminator 12 is connected to one input side of the lower limit comparator 13 and one input side of the upper limit comparator 14. Further, the other input side of the lower limit comparator 13 is connected to a comparison voltage terminal 15a,
It is connected to the comparison voltage terminal 15b on the other input side of the upper limit comparator 14. The lower limit comparator 13 changes the output side logic when the level of the error signal V _i input to one input side is lower than the level of the lower limit comparison voltage applied from the comparison voltage terminal 15a to the other input side. Changes from “0” to “1”. The upper limit comparator 14 has a terminal 15 whose level of the error signal V _i input to one input side is a comparison voltage.
When the level is higher than the upper limit comparison voltage applied from b to the other input side, the logic on the output side changes from "0" to "1".

The reactance switch 16 is an AND circuit 17 and 1
8, a pulse generating circuit 19 and an up/down counter 20. Terminal 12a of error signal level range discriminator 12 and reactance switch 1
The terminals 16a and 12b of No. 6 are connected to each other, and the terminals 16a and 16b are connected to each other.
are connected to one input side of AND circuits 17 and 18, respectively. Further, the input sides of the AND circuits 17 and 18 are connected to the output side of the pulse generation circuit 19. When the lower limit comparator 13 of the error signal level range discriminator 12 becomes active, the AND circuit 17
One input side of pulse generation circuit 1 becomes H level.
The pulse output from 9 is sent to the D terminal of the up-down counter 20. Lower limit comparator 1
3 becomes inactive, it stops sending out pulses. When the upper limit comparator 14 becomes active and one input side of the AND circuit 18 becomes H level, the pulse output from the pulse generation circuit 19 is sent to the U terminal of the up-down counter 20 via the other input side. The up-down counter 20 counts the pulses input to the D terminal or the U terminal. Depending on the count value, the terminals B ₁ , B ₂ ... of the reactance switch 16 are
Switch any one of B _o to H level. In addition,
Terminal B ₁ is LSB, terminal B _o is MSB, and when the count value is zero, all terminals are at L level. Terminals B ₁ to _{B o} of the reactance switch 16 are connected to terminals P ₁ to _{P 2} of the voltage controlled oscillator 9. Terminals P ₁ ~ _{P o}
When becomes H level, the diodes D ₁ -D _o become conductive and the coils L ₁ -L _o become active. Voltage controlled oscillator 9
The operating characteristics of the error signal V _i and the oscillation signal f _p are shown in Figure 5 b ₀
The inductance of the coils L ₀ to L _o is determined so as to form the ~b _o curve. In addition, in FIG. 4, numeral 11 is a field effect transistor, 10 is a variable capacitance diode,
C ₁ to _{C o} are high frequency bypass capacitors. Here, the frequency and phase of the reference signal f _r and the oscillation signal f _p match, and the error signal V _i is locked at a point between the levels V ₁ and V ₂ on the b ₁ curve shown in FIG. , the output side logic of the lower limit comparator 13 and the upper limit comparator 14 of the error signal level range discriminator 12 are both "0", and the up-down counter 20 of the reactance switch ₁₆ is It is maintained at H level. By manipulating the VFO (not shown) and increasing the frequency of the reference signal f _r , the error signal V _i increases toward level V ₂ . When the error signal V _i further increases and becomes higher than the level V ₂ , the upper limit comparator 14 becomes active. For this reason,
The AND circuit 18 of the reactance switch 16 becomes active, and a pulse is sent to the U terminal of the up-down counter 20. Therefore, the terminal _B1 is at L level and the terminal _B2 is at H level.

When the terminal _B2 becomes H level, the coil _L2 becomes active, and the operating characteristics are switched to the _b2 curve (not shown) which handles an oscillation frequency higher than the _b1 curve. Due to the switching, the free running frequency of the voltage controlled oscillator 9 becomes high, and the level of the error signal _Vi , which was higher than the level _V2 , moves to the vicinity of the level _V1 .
Therefore, the upper limit comparator 14 becomes inactive, the up-down counter 20 stops counting, and the terminal _B2 remains at the H level. The pulse generation period is determined to ensure the above transition process. After switching, if the error signal V _i is still higher than the level V ₂ , the next pulse period causes the next higher coil L ₃
- Switched to _Lo . Note that the acceptance ranges of the b ₀ curve to _{b o} curve for the lower limit level V ₁ and upper limit level V ₂ of the error signal V _i are defined as the upper limit of one acceptance range and the lower limit of the other acceptance range. Irregular operation near the upper and lower limits can be prevented by forming the upper and lower limits so that they overlap each other and doubling the receiving ranges at the upper and lower limits.

In the above embodiment, the up-down counter 20 has a single output, but it may be formed to have multiple outputs in a binary mode or the like so that a plurality of reactance elements are activated simultaneously. Further, the information outputted from the up-down counter 20 may be decoded into information in a desired format via a ROM or the like. Alternatively, the information output from the up-down counter 20 may be processed using a microcomputer or the like.

Further, a means for programming the frequency of the oscillation signal, such as a programmable counter, may be provided in the feedback loop.

〔Effect of the invention〕

The PLL circuit according to the present invention includes an error signal level range determination means that utilizes the fact that the error signal has reached a level outside a predetermined range, and changes the free-running frequency of the voltage-controlled oscillator to another free-running frequency in accordance with the determination. Since the configuration includes connection means for connecting the reactance element to the voltage controlled oscillator, it has a feature that information for switching the free-running frequency can be obtained from the error signal. Therefore, if applied to a PLL circuit in which the reference signal is changed by a VFO or the like, the circuit configuration can be simplified compared to a method of obtaining switching information using information other than an error signal.

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams of conventional PLL circuits, Figure 3 is a graph showing the operating characteristics of a voltage controlled oscillator, and Figure 4 shows an embodiment of the present invention.
Block diagram including a partial circuit diagram of the PLL circuit, No. 5
The figure is a graph showing the operating characteristics of the voltage controlled oscillator of FIG. 4. 1, 2... terminal, 3... phase comparator, 4... low pass filter, 5, 9... voltage controlled oscillator, 7
...Programmable counter, 8...Division comparison setting circuit, 10...Variable capacitance diode, 11...
Field effect transistor, 12...Error signal level range discriminator, 13...Lower limit comparator, 14
... Comparator for upper limit, 15 ... Comparison voltage, 1
6... Reactance switch, 17, 18... AND circuit, 19... Pulse generation circuit, 20... Up/down counter, L ₀ to L _o ... Coil, C ₁ to _{C o}
... High frequency bypass capacitor, D ₁ ~ D _o ... Diode.

Claims (1)

[Claims] 1. A voltage controlled oscillator whose free running frequency changes due to the connection of a reactance, a phase comparator that detects the phase difference between the output signal of the voltage controlled oscillator and a reference signal, and an error signal by smoothing the output signal of the phase comparator. and a low-pass filter that generates and outputs the error signal to the voltage controlled oscillator, the error signal level range determining means for determining that the level of the error signal is outside a predetermined range; connection means for connecting the reactance to the voltage-controlled oscillator so as to change the free-running frequency to another free-running frequency according to the determination by the level range determining means; It is characterized by being configured to change the free running frequency according to the frequency.
PLL circuit.