JPH0319984B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vector processing device that includes a vector register and determines the length of the vector register.

[Conventional technology]

Conventionally, in vector processing devices such as CRAY-1, a fixed length (64 in CRAY-1) is used.
It is equipped with a plurality of vector registers, and performs vector operations on vector data in the vector registers. Since the fixed length is the maximum vector length held by one vector register, it is hereinafter referred to as maximum vector length (MVL).

In the case of a vector operation, before the vector operation is executed, the number of vector elements to be executed is stored in advance in a storage means called a vector length register that holds the number of operations to be executed (number of vector elements). After being set by an instruction, vector operations are performed. In the vector arithmetic unit, operations specified by instructions are executed for the number of times set in the vector length register on vector elements read one after another from the vector register, and the operation results are sequentially stored in the vector register or main memory. . At this time, if the loop length (N) of the loop in which the original vector operation written in FORTRAN etc. is to be executed exceeds the maximum vector length (MVL), this loop is divided into multiple pieces and The vector operation is executed multiple times so that the vector operation does not exceed the maximum vector length.
As a result, vectorization of the loop where loop length (N)>maximum vector length (MVL) is performed. That is, if loop length (N)≦maximum vector length (MVL), loop length (N) is set in the vector length register and vector operation is executed.
If loop length (N) > maximum vector length (MVL), divide the loop into [(N-1)/MVL]+1 pieces, and add 1 to the remainder of (N-1)/MVL to obtain the vector length. It is set in a register and the first vector operation is executed. Next, the maximum vector length (MVL) is set in the vector length register and the remaining [(N-1)/MVL] vector operations are executed. ([x] is the largest integer not exceeding x.)
In this way, a loop where loop length (N)>maximum vector length (MVL) can be vectorized even in a vector processing device having a vector register with a fixed maximum vector length. At this time,
In conventional devices such as CRAY-1, the maximum length of the vector register is not only fixed, but also needs to be set as a constant in the object program. This means that, for example, in the future, VLSI
When technology realizes high-speed, large-capacity storage elements,
It becomes possible to provide a vector register with a larger capacity in the processing device, and in this case, the maximum length of the vector register also becomes larger.

[Problem that the invention seeks to solve]

However, in conventional devices, the maximum vector length is set as a constant in the object program, so it is possible to enable large-capacity vector registers without recompiling conventional programs created for smaller-capacity vector registers. It cannot be used. Further, when commercializing a vector processing device, a plurality of models may be set depending on the capacity of the vector register in order to optimize the performance/price ratio and make the product more suitable for the user. At this time, the maximum vector length usually differs between models, but in conventional equipment, the maximum vector length (MVL) is a constant as described above, so there is no object-level compatibility between modems. There is.

SUMMARY OF THE INVENTION An object of the present invention is to provide a vector processing device that solves the above-mentioned drawbacks and provides object-level compatibility between models having different vector register capacities.

[Means for solving problems]

The processing device of the present invention includes a main memory storing instructions and operands, at least one scalar register accessible by the instructions, and a plurality of vector registers each holding a plurality of ordered vector elements. A vector processing device comprising at least one arithmetic unit for calculating the contents of the vector register, and at least one vector length holding means for holding the number of arithmetic elements to be executed by the arithmetic unit. The maximum vector length that the register can hold is a power of 2, and the maximum vector length storage means stores an encoded maximum vector length corresponding to the maximum vector length and can be set from the outside. vector length converting means connected to the encoded maximum vector length to convert the value of the encoded maximum vector length into a value of (maximum vector length - 1); The encoded maximum vector length in the storage means is converted through the vector length conversion means (maximum vector length -
1) and a control means for converting the value into the value of 1) and reading it into the scalar register or the main storage device.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, in one embodiment of the present invention, 8
vector registers 1, each vector register 1 is ordered from address 0 to address 63.
The maximum vector length (MVL) is 64 since it can hold 64 vector elements. Each vector register 1 is connected to an arithmetic unit 3 such as an adder/subtractor. Vector length register (VL)
Reference numeral 2 denotes a register which holds the number of vector calculation elements to be executed by each calculation unit 3, and is connected to the calculation unit 3. The contents of the register 2 can be set by a command, and in this embodiment, the contents are set through the scalar register 4.

In the vector processing device of this embodiment, an instruction is read from the main memory 5, set in the instruction register 6, and decoded by the decoder 10. If the instruction is a vector operation instruction, the decoding result is sent to the appropriate operation unit 3. In the arithmetic unit 3, the vector elements from the vector register 1 specified by the instruction are sequentially read out, the specified operation is executed, and the vector elements resulting from the operation are stored in the vector register 1 one after another. The number of vector operations executed at this time is executed the number of times set in the vector length (VL) register 2 in advance.

There are 16 scalar registers 4 used for scalar operations and address calculations, each having a length of 32 bits, and like the vector register 1, they are connected to the arithmetic unit 3.

Maximum vector length register (MVR) 7 in Figure 1
is a register that encodes and holds the maximum vector length of the vector register 1. By encoding and retaining the data, a small number of bits can be used. In this example, the maximum vector length (MVL) of vector register 1 is 64, but assuming that it can be expanded from 128 to 256 in the future,
Maximum vector length register (MVR) 7 is 2.
The length shall be in bits. Maximum vector length (MVL) =
64 is “00”, maximum vector length (MVL) = 128
When the maximum vector length (MVL) = 256, "11" shall be set in the maximum vector length register (MVR) 7. That is,
In this example, the maximum vector length register (MVR)
7 is set to “00”. The setting means 8 may be a jumper wire or a switch, as shown in FIG. 1, or may be a service processor (SVP) for maintenance and diagnosis. In addition to such setting means 8, setting may be performed through a special path such as a scan path, and a value uniquely determined depending on the configuration of the vector register is set.

Next, the conversion circuit 12 in FIG. 1 is a conversion means for decoding the contents of the maximum vector length register 7 into the maximum vector length of the vector register 1.
This is a circuit that adds 1 to the bit and generates the constant "63".

In FIG. 1, an instruction is fetched from main memory 5 to instruction register 6, and if the instruction is an instruction to read the maximum length of vector register 1, scalar register 4 specified by bits 8-11 of the instruction is selected. Selected by circuit 9. Next, the contents of the maximum vector length register 7 are converted to a value of (maximum vector length - 1) through the conversion circuit 12, and loaded into the selected scalar register 4. In this example,
The maximum vector length is assumed to be read out to the scalar register 4, but the maximum vector length is read out to the main memory 5.
It may also be configured to transfer directly to Note that the reason why the value of the maximum vector length minus 1 is read out is that it is convenient to calculate the remainder of division by a power of 2.

FIG. 2 shows a second embodiment in which the maximum vector length -1 is transferred to the main storage device 5 through the main storage control device 11. In this case, bit 12 of the instruction to transfer the maximum vector length - 1
-31 specifies the address of the main storage device 5.

Figure 3A is based on the embodiment shown in Figure 1.
The source program for the vector control portion of the FORT-RAN DO loop is shown, and FIG. 3B shows its object program. In FIG. 3B, ← indicates that the contents on the right side are set (loaded) in the storage means on the left side.

In FIG. 3B, at step (10), the loop length N of the source program shown in FIG. 3A is loaded into the scalar register S1. In step (2), the contents of the vector register (maximum vector length - 1), that is, the maximum vector length register, are decoded and
"63" is loaded into the scalar register S2. In step (3), the numerical value N-1 is loaded into the register S3. In step (4), scalar register S2
1 is added to the contents of and the maximum vector length (MVL)
is required. In step (5), the scalar register S
3 and S2 are ANDed and loaded into scalar register S5. step
In the series of processes from step (3) to step (5), the remainder of (N-1)/MVL is usually found by utilizing the fact that the maximum vector length (MVL) is a power of two.
In step (6), 1 is added to the remainder,
The addition result is loaded into scalar register S6.
In this embodiment, the address information is in units of bytes, and one vector data is 4 bytes long. Therefore, in step (7), the contents of the scalar register S6 are shifted to the left by 2 bits, that is, multiplied by 4. This corresponds to finding the distance between vector elements when the loop is divided. In step (8), as in step (7), the distance between vector elements at the maximum vector length is determined. In step (9), the relative base address of the first vector element is set. The steps up to this point are the preprocessing portion of the DO loop in FIG. 3A.

In step (10), the contents of the scalar register S6 are loaded into the vector length register 2. The content of the scalar register S6 is either the remainder of (N-1)/MVL+1 or the maximum vector length (MVL). In step (11), the relative base address of the vector is determined for the next iteration of the loop. In step (12), the distance between vector elements between loops is transferred to the scalar register S7.
In step (13), the contents of the scalar register S6 are subtracted from the contents of the scalar register S1 to determine the number of remaining vector elements to be calculated.
In step (14), the contents of scalar register S4,
That is, the maximum vector length MVL is transferred to the scalar register S6. In step (15), it is determined whether there are any remaining vector elements to be calculated, and if there are any remaining vector elements, the process branches to LOOP and the loop is further repeated.

As is clear from FIG. 3B, this embodiment is not an object program in which the maximum vector length that the vector register can hold is a constant, so even if the model has a different maximum vector register length, , the same object program can be used.

Effects of the Invention The present invention is provided with means for storing a value corresponding to the maximum vector length that can be held in a vector register that can be set externally, and the maximum vector length is stored in a register visible to the program or in main memory by an instruction. The read configuration has the effect of providing object-level compatibility to programs between vector processing devices having vector registers with different vector lengths.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing one embodiment of the present invention, Fig. 2 is a diagram showing another embodiment of the invention, and Fig. 3A is a diagram showing an embodiment of the present invention.
A diagram showing a coding example of a FORT-RAN DO loop control portion and FIG. 3B are diagrams showing an example of an object program corresponding to the source program of FIG. 3A according to the present invention. 1...Vector register, 2...Vector length register, 3...Arithmetic unit, 4...Scalar register, 5...Main storage device, 6...Instruction register,
7... Maximum vector length register, 8... Setting means, 9... Selection circuit, 10... Decoder, 11...
...Main memory control device, 12...Conversion circuit.

Claims (1)

[Scope of Claims] 1. A main memory that stores instructions and operands, at least one scalar register accessible by the instructions, and a plurality of vector registers that hold a plurality of ordered vector elements; A vector processing device comprising at least one arithmetic unit for calculating the contents of these vector registers, and at least one vector length holding means for holding the number of arithmetic elements to be executed by the arithmetic unit, wherein the vector The maximum vector length that the register can hold is a power of 2, and a maximum vector length storage means that stores an encoded maximum vector length corresponding to the maximum vector length and can be set from the outside; vector length converting means connected to the maximum vector length storage means for decoding the value of the encoded maximum vector length into a value of (maximum vector length - 1); and control means for converting the encoded maximum vector length of the maximum vector length storage means into a value of (maximum vector length - 1) through vector length conversion means and reading it into the scalar register. vector processing device. 2. In the vector processing device according to claim 1, in response to detection of a read command from the maximum vector length storage means, the encoded maximum vector length in the maximum vector length storage means is converted to the encoded maximum vector length by the vector length conversion means. via (maximum vector length - 1)
A vector processing device comprising control means for converting the maximum vector length into a value of (maximum vector length - 1) and reading the value of (maximum vector length - 1) to the main storage device.