JPH0320166B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method and apparatus for generating a bipolar signal including a bipolar rule error.

(Prior art) In a bipolar signal of a transmission code format, for example, a B3ZS code, in order to eliminate consecutive logic "0" signals during data transmission, a third logic signal is applied to three consecutive logic "0" signals. In order to convert a "0" signal into a logical "1" signal (hereinafter simply written as "1", "0", etc.) and distinguish it from a data signal, the bipolar rule of the signal is taken into account, and the "1"
The signal has the same polarity as the previous bipolar signal. It is a bipolar signal in which an additional bit signal B of "1" is added immediately after the data signal so that the violation signals V of the "1" signals have opposite polarities.

Therefore, when three consecutive bits of the "0" signal are present, it is converted to "B, 0, V" or "0, 0, V".
Here, B is a pulse that follows the bipolar rule, and V is a pulse that violates the bipolar rule. B is inserted so that a mark between V pulses, that is, a signal of "1" becomes a parsimonious number.

As PCM communication has developed, each device has come to have the ability to detect bit errors that occur in the middle of a transmission path, and automatically correct the bit errors. Therefore, in order to test whether the function of detecting and correcting bit errors occurring in the middle of the transmission path operates normally, a device is required that intentionally generates a pattern signal containing errors. In addition, if the transmitter and receiver are separated in a PCM communication measuring instrument, etc., in order to check whether the receiver is working properly,
First, the receiver indicates that there is no error when the signal from the transmitter does not contain any errors, or when the transmitter inserts errors in the signal at a certain rate, that is, a bipolar error occurs. When this occurs, a measuring device is required to measure whether the receiver can correctly display errors in the signal.
That is, in order to perform each operation test on the transmitting side and the receiving side, a measuring device that intentionally generates a pattern signal containing an error is required.

Conventionally, for example, a regular bipolar signal generator for the above-described B3ZS code has used the circuit configuration shown in FIG. 6, and FIG. 7 shows its time chart.

In FIG. 6, 11 is a data signal input terminal;
2 is a clock input terminal, 13 to 18 are shift registers, 19 and 20 are flip-flop circuits,
21 to 23 are AND circuits, 24 to 26 are OR circuits, 27 is a NOR circuit, 28 is an inverter,
29 is a unipolar-bipolar conversion circuit.

A brief explanation using the time chart of FIG. 7 is as follows. That is, among the unipolar digital data signals input to the data signal input terminal 11, the shift registers 13, 14, 1
5. Three consecutive "0" bits are detected by the OR circuit 24 and the NOR circuit 27, and the violation signal V is output from the NOR circuit 27 at the third position of the three consecutive "0" bits. is inserted. The AND circuit 21 determines whether the number of "1"s arriving between the violation signals V is an odd number or an even number, and outputs an additional bit signal B when the number is even. This additional bit signal B is added to the output of the shift register 15 by an OR circuit 25, and the output of the OR circuit 25 becomes a unipolar digital data signal containing the violation signal V and the additional bit signal B. The unipolar digital data signal including the violation signal V and the additional bit signal B output from the shift register 16 is as follows:
Flip-flop circuit 20 and AND circuit 22,2
3, polarity distribution is performed. When the outputs of the AND circuits 22 and 23 whose polarities have been sorted are applied to the unipolar-bipolar conversion circuit 29, a B3ZS-encoded bipolar signal is output.

A conventional bipolar signal generation device that intentionally inserts a bipolar error signal uses a circuit configuration shown in FIG. That is, in FIG. 8, a unipolar digital data signal is input to the code conversion circuit 51, and a violation signal V is input.
The code is converted into a unipolar digital data signal containing the additional bit signal B. This code-converted unipolar digital data signal is
The signal is converted into a bipolar signal by the unipolar-bipolar conversion circuit 52, and a bipolar error is generated by the error signal. By the way, since the error signal input to the unipolar-bipolar conversion circuit 52 is input regardless of the pattern of the unipolar digital data signal, the error signal that should be a bipolar error signal as shown in FIG. E is input to a bipolar signal which is code-converted periodically at regular intervals T ₀ , for example, once every 10 ⁴ bits.

(Problem to be Solved by the Invention) Therefore, when a receiving unit that receives a bipolar signal containing a bipolar error inversely converts the bipolar signal, the bipolar error is not detected and the bipolar signal is regarded as normal data. This has the disadvantage that different results occur between the transmitter and the receiver.

Figure 2 shows a concrete example.
In the B3ZS code, the third "1" in the pattern "1, 0, 1" as shown in Figure 2 A.
When an error signal E that generates a bipolar error is mechanically inserted into the bit position of , the pattern output from the unipolar-bipolar conversion circuit 52 is changed to the third bit "1" as shown in FIG. " is output as a signal with the same polarity as the first bit "1". When the receiver receives this pattern of signals, the first bit is “1”.
is the additional bit signal B explained above, and the third bit "1" is the violation signal V.
Code data pattern and judgment (the second bit “0” is naturally judged as “0”, so “B,
0, V" data pattern), and the data pattern is "0, 0,
0" and reverse inversion.

The present invention aims to solve the above-mentioned drawbacks by generating a bipolar error at a bit position (a specific pattern position) that does not produce an appropriate code conversion pattern, and thereby making it possible to distinguish between data and the intentionally inserted bipolar error. It is an object of the present invention to provide a method and apparatus for generating a bipolar signal including bipolar errors that can be clearly identified in a receiving section.

(Means for Solving the Problems) Therefore, the bipolar signal generation method and device including bipolar errors of the present invention are such that the logic "0",
A conversion circuit that receives a unipolar digital data signal consisting of "1" and a bipolar error signal for generating a bipolar error, and converts the code into a unipolar pulse train containing the logic "1" of a violation signal, and the unipolar pulse train after the code conversion. A determination circuit that determines whether adjacent bits of a pulse train are both logic "1"; a pulse generation circuit that generates a pulse for generating the bipolar error at a predetermined period; and an output from the pulse generation circuit. a holding circuit that holds the unipolar pulse until it is reset by a reset signal; and the determination circuit that determines that the adjacent bits of the unipolar pulse train are both logic "1", and that the pulse is held in the holding circuit. a gate circuit that outputs the pulse as the bipolar error signal for generating a bipolar error and also outputs the pulse to the holding circuit as a reset signal for the holding circuit; The pulse train is converted into a bipolar signal according to a predetermined code conversion rule, and when the bipolar error signal is received from the gate circuit, the polarity of the second "1" of the adjacent bits of the unipolar pulse train is changed. 1st “1”
and a unipolar-bipolar conversion circuit that generates the bipolar error by converting the unipolar pulse train into a bipolar signal so that the polarity is the same as that of the unipolar digital data signal consisting of logic "0" and "1". Receives a bipolar error signal for generating an error, converts the code into a unipolar pulse train containing the logic "1" of the violation signal, and determines the state in which adjacent bits of the unipolar pulse train both become logic "1". , converts the unipolar pulse train into a bipolar signal according to a predetermined sign rule conversion rule, and when the determination result is that the adjacent bits of the unipolar pulse train are both logical "1", the phase of the unipolar pulse train is Generating the bipolar error in the bipolar signal by converting the unipolar pulse train into a bipolar signal so that the polarity of the second "1" of an adjacent bit becomes the same as the polarity of the first "1". It is characterized by the fact that An embodiment of the present invention will be described below with reference to the drawings.

(Embodiment) FIG. 1 shows the configuration of an embodiment of the present invention.
1 is a judgment circuit, 2 is a shift register, and 3 is a “1,”
1" detection circuit, 4 a pulse generation circuit, 5 a holding circuit, 6 a gate circuit, 7 a conversion circuit, and 8 a unipolar-bipolar conversion circuit.

In the determination circuit 1, the "1, 1" detection circuit 3 detects that the adjacent bits extracted from the conversion circuit 7 input to the determination circuit 1 are "1, 1". Here, the violation signal V described above is also included in "1". When the adjacent bits from the conversion circuit 7 are "1, 1", the determination circuit 1
outputs "1". On the other hand, the pulse generation circuit 4
For example, one every 10 ⁴ or 1 every 5 × 10 ⁴ incoming bits of a unipolar digital data signal.
Pulses are generated periodically at regular intervals. The pulse generated by this pulse generating circuit 4 becomes an intentionally generated bipolar error which will be explained later.

The pulse generated by the pulse generation circuit 4, that is, the error signal, is held in a holding circuit 5 such as a flip-flop circuit, and is then transferred to the conversion circuit 7 described above.
When the adjacent bits extracted from the data are both "1", that is, "1, 1", the signal is delayed by the shift register 2 and inputted to the unipolar-bipolar conversion circuit 8 via the gate circuit 6. The output timing of the error signal output from the gate circuit 6 is set on the condition that the determination circuit 1 outputs "1", that is, when the adjacent bits extracted from the conversion circuit 7 are "1, 1".
When this happens, the gate of the gate circuit 6 is opened and the error signal held in the holding circuit 5 is output. Therefore, even if the error signal E that generates a bipolar error generated from the pulse generation circuit 4 is generated at a constant period _T0 as in the conventional example shown in FIG. 3, the timing at which the bipolar error occurs depends on the incoming unipolar digital It varies as shown in FIG. 3 depending on the data signal pattern. Note that the error signal outputted from the gate circuit 6 acts on the holding circuit 5 to reset the holding circuit 5 and prepare to receive the next pulse generated by the pulse generating circuit 4.

The conversion circuit 7 receives the error signal and the unipolar digital data signal and converts it into a unipolar digital signal including a violation signal V and an additional bit signal B in accordance with a predetermined code rule conversion rule. This converted unipolar digital signal is then converted into a bipolar signal by a unipolar-bipolar conversion circuit 8.

Here, the bit position at which a bipolar error should occur will be explained.

When two adjacent bits of a unipolar digital data signal are "1, 1" and "1" in succession, when this unipolar digital data signal is converted into a normal bipolar signal, the first bit is "1". and the second bit "1" are bipolar signals with different polarities. Now, tentatively, the second
If the second bit ``1'' was converted to a bipolar signal with the same polarity as the first bit ``1'', this bipolar signal of the second bit ``1'' is clearly a signal that violates the bipolar rule. It is. The only bipolar signal that is allowed to violate the bipolar rule is the violation signal V described above. Moreover, the bit immediately before this violation signal V is "0".
Must. The bit ``0'' immediately before the violation signal V, the n (n is an integer including 0) bit ``0'' consecutively before this bit ``0'', and the bit ``0'' before this bit ``0''. Due to the presence of a "1" bit which is present in the bit and has the same polarity as the violation signal V, when the "1" bit is in the additional bit signal B, the code-converted bipolar signal is the same as the "1" bit. It is a data signal with a pattern in which everything from the bit to the bit of the violation signal V means "0". Further, when the bit of "1" is not the additional bit signal B, the code-converted bipolar signal is the bit of "1".
This is a data signal with a pattern in which everything from the next "0" bit to the bit of the violation signal V means "0".

Therefore, a bipolar error that violates the bipolar rule occurs at the position of the second bit "1" where two adjacent bits of the unipolar digital data signal are "1, 1" and "1". By making the second bit "1" the same polarity as the first bit "1", the receiving side can distinguish a bipolar error that violates the bipolar rule from the violation signal V, and also distinguish the bipolar error that violates the bipolar rule from the violation signal V. can be detected without being played incorrectly. Furthermore, when two or more adjacent bits of the unipolar digital data signal are "1, 1" and "1", the position at which a bipolar error occurs is the position of any one bit after the second bit. It is sufficient that the position is the position where the gate circuit 6 outputs the error signal. This means that common codes that are converted, such as the B3ZS code,
Applies to B6ZS code etc.

FIG. 2 shows the position where a bipolar error occurs in the B3ZS code, and A in FIG. 2 is a normal bipolar signal before a bipolar error is generated. In Figure 2B, a bipolar error that violates the bipolar rule has occurred in the third bit, and when the receiving side receives this bit string, the second and third “1” are of the same polarity. Therefore, the receiving side detects that the third "1" bit of the diagonal line shown in FIG. 2C is a bipolar error signal.

FIG. 4 shows the configuration of an embodiment of a specific circuit for intentionally generating a bipolar error in a B3ZS code, and 11 to 29 correspond to the circuit shown in FIG. 6 already explained. The circuit configuration in Fig. 4 is
The circuit shown in the figure has an error pulse insertion circuit 30 for holding a pulse that should cause a bipolar error, and AND circuits 34 and 35 added thereto. The error pulse insertion circuit 30 includes a shift register 31,
It is composed of a flip-flop circuit 32 and a NAND circuit 33, and is periodically connected to a trigger terminal at regular intervals, for example, once every 10 ⁴ or once every 5×10 ⁴ , for incoming bits of a unipolar digital data signal. By the trigger input to 36,
Flip-flop circuit 32 is ready to generate an error signal which should be a bipolar error.
The NAND circuit 33 inputs “1,” of the unipolar digital data signal input to the data signal input terminal 11.
1" and "1, 1" due to the insertion of the violation signal V. When these "1"s are consecutive, the gate of the NAND circuit 33 is opened, and the "1" from the flip-flop circuit 32 is passed through. Outputs an error signal E that should generate a bipolar error. This error signal E is transmitted to the shift register 31.
The inverted output of the shift register 31 is configured to be shifted and input to the AND circuits 34 and 35, and to reset the flip-flop circuit 32.

Fig. 5 is a time chart of Fig. 4, and Fig. 5 shows that the unipolar digital data signal input to the data signal input terminal is the second "1, 1" of two consecutive "1"s. ” position,
The case where a bipolar error is generated is shown, and FIG. 5 shows the case where a bipolar error is generated at the position of "1" which is converted to "V, 1" by the violation signal V.

In the time chart of FIG. 5, among the unipolar digital data signals input to the data signal input terminal 11, shift registers 13, 14,
15, 3 by OR circuit 24 and NOR circuit 27
Consecutive bits of "0" are detected, and the NOR circuit 27 is placed at the third position of the three consecutive "0" bits.
A violation signal V output from the shift register 15 is inserted into the output of the shift register 15. Now, for example, when a trigger signal is input to the trigger terminal 36 at the seventh clock, an error signal E that should generate a bipolar error at the ninth clock is output from the NAND circuit 33, and the shift register 31
As a result, the error signal E that should generate the bipolar error is delayed by one clock.

On the other hand, the AND circuit 21 determines whether the number of "1"s arriving between the violation signals V is an odd number or an even number, and the error pulse insertion circuit 30 outputs an error signal E that should cause a bipolar error.
Only when is output, the number of "1"s that arrive between the violation signals V is subtracted by "-1", and then it is determined whether the number is an odd number or an even number. In this way, when the number of "1"s arriving between the violation signals V is an even number, the AND circuit 21 outputs the additional bit signal B. This additional bit signal B is sent to the shift register 15 by the OR circuit 25.
is added to the output of The unipolar digital data signal including the violation signal V and the additional bit signal B outputted from the shift register 16 is sent to a flip-flop circuit 20 and an AND circuit 2.
2 and 23, polarity distribution is performed. When the error pulse insertion circuit 30 outputs an error signal E that should cause a bipolar error, polarity distribution is performed as follows. That is, at the corresponding clock of the error signal E that should generate a bipolar error, that is, at the 11th clock, the same polarity distribution as the previous polarity distribution is performed by the output of the AND circuit 35, and the bipolar error signal is output from the AND circuit 23. error signal
Er is output. Therefore, when the outputs of the AND circuits 22 and 23 whose polarities have been assigned are applied to the unipolar-bipolar conversion circuit 29, signals of "1" of the same polarity are output at the 10th and 11th clocks.
The “1” signal output at the 11th clock is the intentionally generated bipolar error signal Er.
It is. At the output of the shift register 13,
7th and 8th with two “1”s consecutively “1, 1”
Data signal “1, 1” at the time of the th clock
It is shown that a bipolar error has been generated in the second "1" position of .

In the time chart of FIG. 5, insertion of the violation signal V and additional bit signal B is the same as in the case of FIG. shift register 15
At the output of , a violation signal V is inserted at the 6th and 15th clock, respectively, and becomes "V, 1". That is, "1" is converted into two consecutive "1, 1".

For example, suppose that a trigger signal is input from the trigger terminal 36 at the third clock.
The error signal E that should cause a bipolar error at the sixth clock is output from the NAND circuit 33, and the error signal E that should cause the bipolar error at the sixth clock is delayed by one clock and an error pulse is inserted. It is output from the circuit 30.

On the other hand, as explained above, when the error signal E that should cause a bipolar error is output from the error pulse insertion circuit 30, the AND circuit 21 calculates "-1" from the number of "1"s that arrive between the violation signals V. Since it is determined whether the number is even or odd, the additional bit signal B is not inserted between the violation signals V output from the NOR circuit 27.

When the polarity is distributed between the violation signals V, the error pulse insertion circuit 30 outputs the signal E that should generate a bipolar error, so at the eighth clock, the AND circuit 2
2 outputs a bipolar error signal Er having the same polarity as the immediately preceding violation signal V. Therefore, when the outputs of the AND circuits 22 and 23 with different polarities are applied to the unipolar-bipolar conversion circuit 29, "1" of the same polarity is generated at the 7th and 8th clocks.
signal is output. The "1" signal output at the eighth clock is an intentionally generated bipolar error. shift register 1
At the output of 3, the ``0'' of the data signal ``0, 1'' at the fourth and fifth clocks is converted to a violation signal V and becomes ``1''.
A bipolar error is generated at the position of the second "1" where two consecutive "1, 1" occur, that is, "V, 1".

Note that the pulses output from the pulse generating circuit 4 may be at arbitrary intervals.

(Effects of the Invention) As explained above, according to the present invention, a bipolar error is generated at a bit position of a specific pattern that does not cause false code conversion, and data and the intentionally inserted bipolar error are received. A bipolar signal can be generated that includes bipolar errors that can be clearly identified in the section. The present invention can generate bipolar signals containing bipolar errors not only in the B3ZS code but also in other conversion codes such as the B6ZS code.

[Brief explanation of drawings]

Fig. 1 shows the configuration of an embodiment of the present invention, Fig. 2 shows a time chart explaining the bit position at which a bipolar error signal should be generated, and Fig. 3 shows a time chart explaining the timing at which the bipolar error signal is generated. , FIG. 4 is a circuit configuration of an embodiment of the present invention in B3ZS code, FIG. 5 is an operation time chart of FIG. 4, and FIG. 6 is a circuit of a bipolar signal generator that generates a conventional B3ZS code bipolar signal. FIG. 7 is an operation time chart of FIG. 6, and FIG. 8 is an example of the configuration of a conventional bipolar signal generator including a bipolar error. In the figure, 1 is a judgment circuit, 2 is a shift register, and 3
is the “1, 1” detection circuit, 4 is the pulse generation circuit, 5
1 is a holding circuit, 6 is a gate circuit, 11 is a data signal input terminal, 12 is a clock input terminal, 13 to 18 are shift registers, 19 and 20 are flip-flop circuits, 21 to 23 are AND circuits, 24
26 to 26 are OR circuits, 27 is a NOR circuit, 28 is an inverter, 29 is a unipolar-bipolar conversion circuit, 30 is an error pulse insertion circuit, 31 is a shift register, 32 is a flip-flop circuit, 33
is a NAND circuit, 34 and 35 are AND circuits, 51 is a code conversion circuit, and 52 is a unipolar-bipolar conversion circuit.

Claims (1)

[Claims] 1. Receives a unipolar digital data signal consisting of logic "0" and "1" and a bipolar error signal for generating a bipolar error, and codes it into a unipolar pulse train including logic "1" of the violation signal. converting and determining a state in which adjacent bits of the unipolar pulse train both become logic "1",
The unipolar pulse train is converted into a bipolar signal according to a predetermined sign rule conversion rule, and when the determination result is that the adjacent bits of the unipolar pulse train are both logic "1", the adjacent bits of the unipolar pulse train are a bipolar pulse train that generates the bipolar error in the bipolar signal by converting the unipolar pulse train into a bipolar signal such that the polarity of the second "1" of the bit is the same as the polarity of the first "1"; Bipolar signal generation method with errors. 2. A conversion circuit 7 that receives a unipolar digital data signal consisting of logic "0" and "1" and a bipolar error signal for generating a bipolar error, and converts the code into a unipolar pulse train containing logic "1" of a violation signal. a determination circuit 1 that determines whether adjacent bits of the code-converted unipolar pulse train are both logic "1"; and a pulse generation circuit 4 that generates a pulse for generating the bipolar error at a predetermined period. and; a holding circuit 5 that holds the output from the pulse generation circuit until it is reset by a reset signal; and the determination circuit determines that the adjacent bits of the unipolar pulse train are both logic "1"; and a gate circuit 6 that outputs the pulse as the bipolar error signal for generating a bipolar error when the pulse is held in the holding circuit, and also outputs the pulse as a reset signal of the holding circuit to the holding circuit. and; converting the unipolar pulse train outputted from the conversion circuit into a bipolar signal according to a predetermined sign rule conversion rule, and converting the adjacent bits of the unipolar pulse train when receiving the bipolar error signal from the gate circuit. the second “1” of
and a unipolar-bipolar conversion circuit 8 that generates the bipolar error by converting the unipolar pulse train into a bipolar signal so that the polarity of the signal becomes the same as the polarity of the first "1". Signal generator.