JPH0322102B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a logic circuit constituted by MOS transistors. Traditionally, readable and writable RAM (random access memory),
In semiconductor memories such as ROM (read only memory), in order to improve the transfer efficiency of switching transistors or reduce power consumption, the load transistor of the output stage buffer is an enhancement type (hereinafter referred to as E type), and "1" Logic circuits with a booster circuit in the output stage were often used to provide a sufficient output level. However, conventionally, there was no means to maintain this boosted voltage, and after a certain period of time, the boosted voltage would drop to the power supply voltage or lower due to leakage current from the P-N junction etc. connected to the boost terminal. There was a problem.

Conventional circuits of this type are shown in FIGS. 1a-c. Figure 1a shows a general logic circuit that obtains a boosted voltage at the output, where the decoder output or logic signal is connected to the input terminal A of the buffer B1, and the output terminal B of the logic circuit is connected to the input terminal A of the buffer B1.
Capacitor C ₁ is connected through inverters I ₁ and I ₂ . In this circuit, terminal A changes from “0” to “1”
, terminal B changes from “0” to “1”,
After a certain delay time by inverters I ₁ and I ₂ , the "1" level of B is boosted by capacitor C ₁ .
This boosted output B is supplied to the gate of a switching transistor, a row line in a semiconductor memory, or the like.

FIG. 1b shows another conventional example. This is a signal generation circuit composed of a delay circuit section 1 and a booster circuit section 2, and the delay circuit section 1 is of N-channel type (all transistors shown below are of N-channel type).
Consisting of transistors T ₀₁ to T ₀₄ , booster circuit section 2
is composed of transistors T1 to T5. In this circuit, when the signal φ _p is “1” and the signal φ ₁ is “0”, the terminals C, D, E, F and output G are “0”, respectively.
They are "1", "1", "0", "0". Next, after the signal φ _p becomes “0”, when the input φ ₁ becomes “1”, the terminal G becomes the “1” level by the signal φ ₁ through the transistor T1, but at this time, the terminal D is still “1”. Terminal F for “1” is “0”.
Next, through the delay circuit 1, the signal _φ1 reaches the terminal D with a delay, and when the terminal D becomes "0", the terminal E becomes "0" through the transistor T2, and at the same time, the transistor T1 turns off, and the transistor T
5 is turned off, the terminal F becomes "1", and the output G is boosted by the capacitor _C2 .

FIG. 1c shows another conventional example. This is a circuit often used in decoders etc., and the transistor T
Consists of 6 to T10. In this circuit, when decoder D1 is selected and output I changes from "0" to "1",
The terminal J also changes from "0" to "1" through the transistor T6, but since the terminal K is "1", the transistor T10 is turned on and the terminal L is still "0". Next, after a certain delay time by inverter _I3 , when terminal K becomes "0", terminal L becomes "1",
Terminal J is boosted by capacitor _C3 . At this time, transistor T6 is cut off. Therefore, the transistor T7 operates as a triode tube, and a sufficient "1" level is outputted to the terminal L. Here terminal L
is connected to a row line or the like of a semiconductor memory.

However, in Figure 1 a, b, and c,
The boosted voltages of the boosting terminals B, G, and J tend to drop after a certain period of time due to leakage current from the PN junctions connected thereto, resulting in a drawback that sufficient operation is no longer possible.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to prevent a drop in the boosted voltage due to leakage current by supplying another steadily boosted voltage to the boost terminal. The present invention provides a logic circuit that moves up and down between a boosted level that is higher than the power supply voltage and approximately zero volts.

FIG. 2 shows an embodiment of the present invention. Since this FIG. 2 is an improved version of FIG. 1a, corresponding parts are given the same reference numerals and their explanation will be omitted. That is, a depletion type transistor T is connected to the output terminal B.
11 (hereinafter referred to as D type) is connected, and the drain is connected to the D type as a switching transistor.
transistor T1 as well as type transistor T12
3, connected to the source connection point M of transistor T
12 drains are constantly connected to a boosted voltage (e.g.
8V), the drain of the transistor T13 is connected to the power supply V _C , and the gates of the transistors T11 and T12 are connected to the inverter I ₂
The gate of the transistor T13 is connected to the output terminal O of the inverter _I1 . A boost voltage supply circuit 3 is provided by the transistors T11 to T13.
is provided.

In this circuit, first, when terminal A is "0", terminals B and O are "0" and terminal N is "1", so the gm of transistors T13 and T11 is
If the ratio is set sufficiently large, the connection point M will be approximately at the potential of the power supply V _C (5V), and the gate voltage of the transistor T12 (here, the potential of the output terminal O) will be set to V ₀ ,
If the threshold voltage is V _TH12 and the relationship V ₀ −V _TH12 <V _C is satisfied, the transistor T12 is cut off,
The boosted potential does not drop through the transistor T12. Next, when the terminal A becomes "1" and the terminal B also becomes "1", the terminal N becomes "0" after the delay time of the inverter _I1 , the transistor T13 is cut off, and then the terminal after the delay time of the inverter _I2 becomes "0". At the same time that O becomes "1" and the "1" level of the output terminal B is boosted by the capacitor _C1 , the transistor T12 is turned on, and the boost terminal H is connected to the output terminal B through the transistors T12 and T11. Ru.
Since the terminal H can steadily supply a boosted voltage, as long as the terminal B has a current supply capacity sufficient to cover the PN junction leakage current, etc., the output terminal B can constantly obtain a boosted voltage. What is important here is that the current supply capacity of the circuit that normally generates the boosted voltage is very small, so when the terminal B is "0", the transistor T1
Second, if the cut-off or conduction resistance is not sufficiently large, the potential of the boosting terminal H will drop.

The advantage of the above configuration is that the switch means (for example, T
12), the boosted potential from terminal H is switched. In other words, for example, when input A in FIG.
is irrelevant. Note that when input A is “1”,
The transistor T12 is turned on, but since the point B is at a high potential at this time, it is enough to compensate for the leakage current from the boosting means before the terminal H, and the circuit operation of the boosting means is not affected in any way. Therefore, when it is desired to provide a plurality of the circuits shown in FIG. 2, the present invention has a function that allows the circuit shown in FIG. 7 to be used in common, for example, so that only one booster is required.

FIG. 3 is an improved version of FIG. 1b, in which a boosted voltage supply circuit 3 similar to that in FIG. 2 is provided in FIG. 1b. The source of the transistor T11 is connected to the boosted voltage output terminal G, the gate of the transistor T13 is connected to the delay circuit output terminal D, and the gates of the transistors T11 and T12 are connected to the terminal F, respectively. In this circuit, the signal φ _P is “1” and the signal φ ₁
When is "0", terminal D is "1", terminals F and G are "0", transistor T13 is turned on, connection point M becomes approximately V _c potential, and transistor T12
is cut off. Next, the signal φ _P is “0”, and the signal φ ₁
When becomes "1", the terminal G becomes "1" through the transistor T1, and when the terminal D becomes "0" after the delay time by the delay circuit 1, the terminal E also becomes "0", and at the same time as the transistor T1 is cut off, the terminal G becomes "1". F becomes "1", the "1" level of the terminal G is boosted, and the transistor T12 is turned on, and the boosted terminal H is passed through the transistors 12 and T11.
is connected to the output terminal G, and holds the boosted potential of the output terminal G.

Figure 4 is an improved version of Figure 1c, and Figure 2,
This is an example using a boosted voltage supply circuit different from that shown in FIG. In Figure 4, the boost output terminal J and the boost terminal H
An enhancement type transistor (hereinafter referred to as E type) T as a switching transistor is connected between
15 is connected, and an E-type transistor T14 is connected between the gate terminal P of this transistor T15 and the decoder output terminal I, and its gate is connected to the power supply.
Connected to V _c . In addition, the terminal P and the oscillation circuit 10
A capacitor _C4 is connected between the output terminal OSC and the output terminal OSC. The oscillation circuit 10, capacitor C ₄ , and transistors T14 and T15 constitute a boosted voltage supply circuit 4.

The operation shown in FIG. 4 will be explained according to the timing chart shown in FIG. The oscillation circuit 10 oscillates and the output terminal
A constant oscillation output can be obtained from the OSC. At this time, terminal H is supplied with a boosted voltage (approximately 8V).
When the decoder D1 is not selected and the output I is "0", the terminal P,
J is “0” and transistor T10 is turned on,
Terminal L also becomes "0". Transistor T15 is turned off and terminals H and J are disconnected. Next, when the decoder D1 is selected and the terminal I becomes "1", J and P become "1" level through the transistors T6 and T14, and after the delay time of the inverter _I3 , the terminal L becomes "1", and the terminal The "1" level of J is boosted. On the other hand, the terminal _P1 charged to the "1" level (approximately 4V) by the transistor T14 is boosted by the capacitor _C4 , and the boosted voltage (approximately 8V) and the low "1" level (approximately 8V) are adjusted to the oscillation frequency of the terminal OSC. 4V). Therefore, when the boosted voltage at terminal J drops due to P-N junction leakage, etc., transistor T15 turns on while P is boosted, supplies the boosted voltage to terminal J, and otherwise turns off. It's off.

FIG. 6 shows another modification of the boost supply circuit 4 shown in FIG. 4, which is connected to the circuit shown in FIG. 1a. That is, an E-type transistor T18 is provided between the output terminal B of FIG. 1a and the output terminal B' of the buffer B1, and its gate is connected to the power supply _Vc . An E-type transistor T17 is connected between the gate end Q of the transistor T15 and the capacitor output end P, and its gate is connected to the terminal P. An E-type transistor T16 is provided between terminals Q and B', and its gate is connected to the power supply _Vc . A transistor T14 is connected between terminals P and B', and its gate is connected to the power supply _Vc .

In this circuit, terminal A becomes "1", B',
B becomes "1", and after the delay time of inverters I ₁ and I ₂ , the voltage at terminal B is boosted, while a waveform similar to the waveform at terminal P in FIG. 5 is obtained at terminal P, which is rectified by transistor T17. Since a constant boosted voltage is obtained at the terminal Q, the transistor T15 is turned on at the same time as the boosted voltage at the terminal B decreases, and the boosted voltage is supplied from the terminal H.

FIG. 7 shows a general circuit for obtaining a boosted voltage H. This circuit consists of an oscillation circuit 5 having five stages of inverters _I11 to _I15 , and a four-phase
It consists of a booster circuit 6 having stages of boosters 6 ₁ to 6 ₄ . Here, C ₁₁ to C ₁₅ are capacitors, and T21 to T2
8 is an enhancement type transistor. In this circuit, as shown in FIG. 8, the booster circuit 6
A voltage waveform that gradually increases is obtained at terminals a to d of the boost voltage supply terminal H, and the voltage at the boost voltage supply terminal H gradually increases and eventually settles down to, for example, 8V, but this voltage amplitude is The higher the number of stages of the sections 6 ₁ to 6 ₄ is, the higher the height can be raised. Further, instead of the output waveform at the oscillation output terminal S, the voltage can be increased efficiently by using a pulse signal in which the respective "1" levels do not overlap.

As explained above, according to the present invention, since another steadily boosted voltage is supplied to the boosted voltage output terminal that outputs the "1" level boosted above the power supply voltage, the boosted voltage due to leakage current is reduced. It is possible to provide a logic circuit that can prevent the deterioration.

[Brief explanation of the drawing]

1A to 1C are logic circuit diagrams having a conventional booster circuit, FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams showing different embodiments of the present invention. , FIG. 5 is a timing waveform diagram showing the circuit operation of FIG. 4, FIG. 6 is a circuit diagram showing still another embodiment of the present invention, FIG. 7 is an example circuit diagram for obtaining a boosted voltage, and FIG. FIG. 3 is a timing waveform diagram showing the operation of the same circuit. 1... Delay circuit, 2... Boost circuit, 3, 4, 4'...
Boosted voltage supply circuit, 5... Oscillation circuit, 6... Boost circuit, T12, T15... Switching transistor.

Claims (1)

[Scope of Claims] 1. A logic circuit section that outputs a boosted voltage higher than the power supply voltage or approximately zero volts depending on the input level, a booster that maintains a voltage higher than the power supply voltage, this booster, and this booster. A switch is provided between the output of the means and the output of the logic circuit section and is controlled by the logic circuit section, and when the output of the logic circuit section is a boosted voltage higher than the power supply voltage, the switch of the logic circuit section is switched. A logic circuit characterized in that the logic circuit comprises switch means for continuing to supply the high voltage of the booster means via the switch. 2. Claim 1, wherein the switch is comprised of a switching transistor.
Logic circuit described in Section. 3. The switching transistor is controlled to be in an OFF state when the boosted voltage output of the logic circuit section is at a level before boosting, and to be in an ON state when the boosted voltage output is at a level after boosting. Logic circuit according to item 2.