JPH0322107B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention uses a CPU (Central
This invention relates to a circuit that performs frequency offset adjustment in a wireless communication device that uses a processing unit.

[Conventional technology]

To give an example of the circuit configuration of a conventional wireless communication device using a CPU, as shown in FIG. The PLL determines the operating frequency of the wireless communication device.
(Phase Locked Loop) controls the frequency of the local oscillator 2, and also displays the digital frequency display 3.
However, since the frequency register output data and the displayed frequency do not normally match, there is a configuration in which the operating frequency is supplied to the display through a preset adder/subtractor 12 that adds or subtracts a correction number determined by the configuration of the intermediate frequency, etc.

In order to perform so-called frequency offset adjustment (this adjuster is called clarifier or RIT in amateur radio equipment), which operates by slightly shifting the transmitting and receiving frequencies, the above-mentioned steps are required.
Insert a variable capacitance diode 2A in parallel or series with the oscillation crystal of the reference oscillator and local oscillator (both crystal controlled oscillators) in the PLL control local oscillator circuit,
There is a method of changing the oscillation frequency by changing the reverse voltage applied to this. When the offset switch 4 is ON, this offset control voltage circuit is connected to the voltage variable offset regulator 5 ,
When it is OFF, it is connected to the fixed voltage circuit 6 . In addition, a rotation that reverses ON and OFF during transmission and reception may be added, but this is omitted from the diagram.

Although it is possible to offset the frequency relatively easily using the above method, the method of frequency display does not change, so the actual frequency and the displayed frequency will not match.
Since the relationship between the amount of adjustment by the offset adjuster 5 and the amount of frequency offset is not exactly proportional, there is a disadvantage that the amount of frequency offset is uncertain.

[Problem that the invention attempts to explain]

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit that can easily and accurately adjust the offset by matching the actual frequency at the time of offset adjustment with the displayed frequency in a digital frequency display system for a wireless communication device.

[Means to solve the problem]

A frequency register for holding frequency data, an offset selection means in which the output of the frequency register is connected to a direct path and a frequency offset adder/subtractor by a switch, and the output side of the offset selection means is connected to a PLL oscillator and a preset adder/subtractor. In the oscillation frequency control circuit, the frequency offset adder/subtractor is connected so as to be supplied with a first counter count value of a counting means consisting of an arithmetic unit that outputs a pulse signal and a first counter, and further includes an arithmetic unit and a first counter. A second counter and its output as D/
A comparator compares the voltage converted by the A conversion circuit and the offset voltage adjusted by the offset regulator, and if they match, outputs a coincidence detection signal to the arithmetic unit to stop pulse output, and then outputs a match detection signal to the arithmetic unit to stop the pulse output. This is a frequency offset circuit having an offset setting means consisting of a counting control means for stopping the measurement of the frequency.

〔Example〕

FIG. 2 is a block diagram of an offset circuit showing one embodiment of the present invention, which will be explained with reference to FIG. Tuner 1 to frequency register 11 of CPU 10
When an interrupt pulse and a U/D signal are input from , and the output of the frequency register 11 selects a direct path by the switches 13 and 14 controlled by the offset selector 7, the output of the frequency register 11 is connected to the PLL oscillator 2 and preset addition/subtraction. The preset adder/subtractor 12 corrects the signal by the intermediate frequency and adds it to the frequency display 3. This circuit is similar to FIG. 1 of the prior art.

Next, the offset selector 7 selects the switches 13,
14 to the offset side, an offset adder/subtractor 15 is inserted into the output circuit of the frequency register 11, and digital data equal to the frequency shift amount is added to or subtracted from the output of the frequency register 11.
The signal is supplied to a frequency display 3 via a PLL oscillator 2 and a preset adder/subtractor 12. The digital data of the frequency shift amount is the output of the N-bit first counter 16 (the number of bits is determined by the required frequency accuracy), and reading of the clock pulse is started with a reset pulse from the arithmetic unit 17 of the CPU 10 . It holds data when the clock is stopped. At the same time, the reset pulse and clock pulse are also applied to the N-bit second counter 8, and the output thereof is converted into an analog voltage by the D/A conversion circuit 9 and applied to one input terminal of the comparator 20. In addition, an offset regulator 5 is connected to the other input terminal of the comparator 20 as a reference voltage for comparison.
The adjusted offset voltage is supplied and compared.

The output of comparator 20 is connected to the lock signal terminal of arithmetic unit 17 of CPU 10 . When the voltages applied to the two input terminals of the comparator 20 match, the match detection output locks the arithmetic unit 17 to stop outputting clock pulses. As a result, the first counter 16 also becomes the second counter 8.
Also stops measurement. The data of the first counter 16 and the second counter 8 are held fixed. The data of the first counter 16 is the frequency offset adder/subtractor 1
5, and the data of the first counter 16 is set in the frequency offset adder/subtracter 15 as offset data.

In the circuit shown in FIG. 2, when the offset on/off switchers 13 and 14 are on, the offset frequency setting circuit is selected, and the frequency offset adder/subtracter 15
The frequency data output from the frequency register 11 is offset by the offset data set in .
Further, when the on/off switchers 13 and 14 are off, the frequency data of the frequency register 11 on the direct path side is directly supplied to the PLL oscillator 2 and the preset adder/subtractor 12.

〔Effect of the invention〕

The present invention provides a circuit that adds and subtracts offset frequency data to the frequency data in the frequency register as described above, so that the offset frequency is input to the preset adder/subtractor that converts it to the operating frequency displayed on the frequency display. Therefore, the operating frequency and display frequency are the same, and there is no need to make any special modifications to the PLL oscillation circuit, resulting in excellent frequency stability.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional circuit using a CPU for frequency control, FIG. 2 is a block diagram of a frequency offset circuit showing an embodiment of the present invention, and FIG. 3 is a flowchart thereof. DESCRIPTION OF SYMBOLS 1... Tuner, 2... PLL oscillator, 3... Frequency display, 4... Offset switch, 5... Offset adjuster, 8... Second counter, 9... D/A conversion circuit, 10 ... CPU, 11... Frequency register, 12
...Preset adder/subtractor, 13, 14...Switcher, 1
5... Offset adder/subtractor, 16... First counter, 17... Arithmetic unit, 20... Comparator.

Claims (1)

[Claims] 1 A frequency register that holds frequency data,
An offset selection means for outputting the output of the frequency register through a direct path or a frequency offset adder/subtractor, and a preset adder/subtracter for converting the output of the offset selection means into a PLL oscillator and an operating frequency to be displayed on a display. In an oscillation frequency control circuit consisting of a circuit, an arithmetic unit that outputs a pulse signal, first and second counting means that count the pulse signal, and a D/A that converts the output of the second counting means into an analog signal. a converter and the D/
It has a comparator that compares the output of the A converter with an offset setting value, outputs the output of the comparator to the arithmetic unit, and stops the pulse output with the output of the comparator,
A frequency offset circuit characterized in that the output of the first counting means at this time is set in a frequency offset adder/subtractor to offset frequency data.