JPH0322112B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field to which the invention pertains) The present invention relates to a digital data transmission system that transmits digital data consisting of a bit sequence of "0" and "1". The present invention relates to a stuff bit insertion method for digital data transmission that allows reliable and simple transmission when using a digital data transmission line.

(Prior Art) Conventionally, in a digital transmission path that transmits digital data consisting of a bit sequence of "0" and "1", there is no restriction on the occurrence of the bit sequence to be transmitted; A transmission path that can transmit even a “1” sequence (hereinafter referred to as a transmission path with BSI): BSI is a Bit Sequence
There are transmission paths (hereinafter referred to as transmission paths for which BSI is not ensured) that do not guarantee correct transmission for certain bit sequences of "0" and "1".

In a transmission path where BSI is not secured, data synchronization signals are extracted from the transmitted bit sequence, so if "0" or "1" continue for a long time, synchronization cannot be extracted. Therefore, for example, the conditions are that the bit sequence to be transmitted has 15 or fewer consecutive occurrences of "0" and that any 24-bit sequence has three or more "1"s.

There is a staffing method for transmitting data with no restrictions on bit sequences over such transmission lines where BSI is not secured. This means that the input bit sequence is divided into blocks of a certain length, and that the bit sequences in the divided blocks do not satisfy the above condition, that is, the zero-constraint constraint that restricts the series of "0"s. When a sequence occurs (hereinafter referred to as "when a violation occurs"), 1 bit "1" is forcibly inserted into n bits (n is an integer) in the input bit sequence and transmitted. In addition, code data (staff flag) indicating that "1" has been forcibly inserted into the sequence is transmitted at the same time, and on the receiving side, the block whose staff flag indicates that a staff code is included is n The input bit sequence is reproduced by removing the "1" placed in each bit.

Here, since the occurrence of a violation is checked for each block, processing at the boundaries of the blocks becomes a problem.

Conventionally, the first bit and multiple bits at the end of a block are fixed to "1" to increase the occurrence of "1"s at block boundaries, thereby eliminating the need to check for occurrences of violations across blocks. It was a simple process. However, if "1" is fixedly inserted, it cannot be used for transmitting input digital data, so there is a drawback that the transmission efficiency decreases.

(Objective of the Invention) In order to eliminate such drawbacks, the present invention strengthens the conditions for inspection of violations at the border, and at the same time reduces the insertion of fixed "1", thereby achieving efficient and efficient inspection. This invention aims to provide a stuff bit insertion method for digital data transmission that enables reliable data transmission, and will be described in detail below with reference to the drawings.

(Structure and operation of the invention) FIG. 1 is a block diagram of an embodiment showing the structure of the present invention, in which 100 is a digital data transmitter, 200 is a digital data receiver, 30 is a digital data transmitter, and 30 is a digital data receiver.
0 is a digital transmission path, 1 is an input terminal, and 2 is an output terminal.

In the digital data transmitting device 100, 1
0 is a memory, 11 is a staff control circuit, 12 is a memory, 13 is a selection circuit, 14 is a multiplexing circuit, 15
indicates a pulse generation circuit.

The signal supplied from the input terminal 1 is digital data including images and sounds, and the bit sequence thereof is not subject to any restrictions. This signal is written into the memory 10, output from the memory 10 in response to the read clock output from the staff control circuit 11, and supplied to the memory 12 and the staff control circuit 11.

The staff control circuit 11 is for detecting the presence or absence of a violation contained in a bit sequence from the data input via the memory 10. Therefore, first, the pulse generation circuit 15
generates a pulse of a certain period. That pulse is
Pulses with a block width that is the unit of stuff insertion, and pulses during the observation period for violation detection, for example, if the occurrence of consecutive “0”s is 15 bits or less,
In a transmission path that requires the two conditions that there be three or more "1"s in any 24-bit sequence, two pulses with a width of 15 samples and a pulse with a width of 24 samples are used. At the end of the block, a pulse shorter than the above pulse is used, for example, under the above conditions, the pulse is 9 samples wide at the beginning and 8 samples wide at the end.

Next, in the staff control circuit 11, the memory 10
For digital data input via
It is detected whether or not the violation occurs during the pulse period generated by the pulse generating circuit 15. That is, the first 9 samples of the block are detected as violations unless there are at least two "1"s, and the last 8 samples of the block are detected as violations.
A violation is detected unless there is at least one "1". However, for reasons described later, a case will be described in which the first bit of the block is always set to "1".

Furthermore, in the middle of the block, a violation is detected unless there is at least one "1" in 15 samples and at least three "1"s in 24 samples.

Here, processing at block boundaries will be explained in more detail using FIG. If each violation is detected within a block, the fifth
As shown in Figure a, both the Mth block and the M+1th block satisfy the conditions that the number of consecutive "0"s is 15 or less and that there are three or more "1"s in 24 samples. However, on the transmission path, both blocks are connected as shown in Figure 5b, and three or more "1"s out of 24 samples are connected.
This condition is not satisfied. Therefore, as shown in Figure 5c, if violations are detected within a block, even at the end of the block there is one or more "1"s in 8 samples, and
If we add the condition that the beginning of the block contains 2 or more 1's in 9 samples, then any part of the bit sequence will satisfy the condition of 3 or more 1's in 24 samples.

In the above description, it is assumed that the first bit of the block is "1", but this assumption is not an essential condition for the present invention. If this assumption does not exist, the present invention can be implemented by further strengthening the violation inspection conditions at the front end of the block and the rear end of the block. For example, each of the 24 bits at the front end and the rear end of the block is divided into 8 bits x 3, and which 8
The condition may be that there is one or more "1" bits.

Figure 2 is a diagram showing an example of the configuration of a violation detection circuit.
An example of detecting whether or not there are two "1"s will be shown.

Here, 30 and 31 are input terminals, 32 is a counter, 33 is a 24 sample delay circuit, 34 is a subtracter,
35 is a comparison circuit.

Digital data is supplied to a counter 32 via an input terminal 30, and a block pulse indicating the period of the block is input via an input terminal 31 to a reset terminal of the counter 32, resetting the counter at the beginning of each block. After the reset,
The number of "1"s in digital data input via the input terminal 30 is counted.

The output of the counter 32 is supplied to a subtracter 34 and a 24 sample delay circuit 33, and the counter output delayed by 24 samples is also input to the subtracter 34. With this configuration, the subtracter 34 outputs the number of "1"s present in the 24 samples.

The number of "1"s output from the subtracter 34 is compared with the value 3 determined from the conditions in the comparator 35, and if it is larger than 3, it is determined that a violation has been detected and is output via the output terminal 36. Outputs detection signal “1”.

It can be easily inferred that detection of other conditions can also be performed with a completely similar configuration.

With the above method, when a violation is detected in a certain block, the staff control circuit 11
A staff selection signal is sent to the selection circuit 13 and a read control signal is sent to the memory 12. the result,
Digital data for a 7-bit period is read from the memory 12 and sent to the multiplexing circuit 14 via the selection circuit 13.
The selection circuit 13 selects the stuff bit "1" and supplies it to the multiplexing circuit 14 while prohibiting reading from the memory for the next one bit period. Therefore, consecutive occurrences of “0” are 15 bits or less, and there are 3 consecutive occurrences of “0” in any 24-bit sequence.
It is possible to satisfy the condition that there are more than one "1".

Additionally, a stuff flag "1" indicating that the block is stuffed is output to the multiplexing circuit 14. Furthermore, since the transmission speed of input data decreases due to stuffing, the stuffing control circuit 11 outputs a read speed control signal to the memory 10 to match the data speed.

The multiplexing circuit 14 multiplexes the digital data output from the selection circuit 13 and the staff flag output from the staff control circuit 11, and transmits the data to the transmission line 30.
Send to 0.

Next, in the digital data receiving apparatus 200, 20 is a separation circuit, and 21 is a stuff removal circuit.

When digital data is supplied to the separation circuit 20 via the transmission line 300, the separation circuit 20 establishes frame synchronization from the input signal and separates it into a staff flag and other digital data.

The digital data and the staff flag are input to the staff removal circuit 21, and when the staff flag is "1" (when the staff is inserted)
Remove stuff from digital data and output. Furthermore, when the staff flag is "0", the input data is output as is.

Next, block boundary processing from the perspective of frame configuration will be described.

Digital data output from the multiplexing circuit has a frame structure. Then, transmission synchronization patterns, control information, etc. necessary for transmission are arranged.

Figure 3 shows an example of a frame configuration. Here, one transmission frame is composed of 193 bits,
One multiframe consists of 24 transmission frames.
Furthermore, three transmission frames constitute the aforementioned staff detection insertion unit block. Note that bit number 0 in the figure is a bit used for multiframe synchronization, and bit numbers 1 to 192 are bits used for data transmission.

Here, we will focus on the bit at the beginning of the frame.

Figure 4 shows an example of the contents of the bit number 0 at the beginning of each frame in a multi-frame configuration, where is the frame number, is the bit corresponding to the multi-frame synchronization code, is "1" added for staff protection, indicates empty bits used for other controls.

First, in order to make it difficult for violations to occur at block boundaries, the bit at the beginning of the block is forcibly set to "1". Therefore, "1" is inserted into the first bit of the frame every three transmission frames (frame numbers 1, 4, 7, 10, . . . ). Also,
For multi-frame synchronization, insert a code of 1 bit every 4 frames (frame number 4, 8, 12).
…). Here, the bits of the common multiple of the 3 transmission frames and the 4 transmission frames (frame numbers 4, 16...
), a synchronization pattern is determined so that it always becomes "1".

As mentioned above, as a result of arranging a synchronization pattern that always becomes "1" for bits that are a common multiple of 3 transmission frames and 4 transmission frames, multi-frame synchronization and staff It is possible to have two roles for arranging "1" in the first bit of the block.

In addition, in the above example, the frame length, the number of multi-frames, and the number of blocks are respectively set for simplicity.
Although the explanation has been made using 193 bits, 24 bits, and 3 bits, it is obvious that it can be applied to other numerical values as well.

(Effects) As explained above, the present invention detects the occurrence of "0" using short observation bits at the boundaries of blocks, which are units in which stuffing is performed, thereby determining whether or not stuffing is needed independently for each block. This can be detected, and the "1" forcibly inserted at the beginning of the block can also be used as part of multiframe synchronization. Therefore, there is an advantage that stuffing can be achieved relatively easily, reliably, and efficiently with respect to the amount of information.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment showing the configuration of the present invention, FIG. 2 is a diagram showing an example of the configuration of a violation detection circuit, FIG. 3 is a diagram showing an example of a frame configuration, and FIG. FIG. 5 is a diagram showing an example of a frame structure, and is a diagram illustrating processing at block boundaries. 100...Digital data transmitting device, 200...
Digital data receiving device, 300... Digital transmission path, 1... Input terminal, 2... Output terminal, 10, 1
2... Memory, 11... Stuff control circuit, 13... Selection circuit, 14... Multiplexing circuit, 15... Pulse generation circuit, 20... Separation circuit, 21... Stuff removal circuit,
30, 31...Input terminal, 32...Counter, 33...
24 sample delay circuit, 34...subtracter, 35...comparison circuit, 36...output terminal.

Claims (1)

[Scope of Claims] 1. A bit sequence of input digital data is divided into blocks at regular intervals, and the bit sequence is observed at a sample time determined within this block, and as a result, the bit sequence of the same type included in the bit sequence is If the following conditions are not met: the number of bits in a row is less than a predetermined number, and the density of bits of the same type is less than a certain value, the number of consecutive bits of a different type is A digital data transmitting device that has a function of inserting bits into a bit sequence, converting the data, and transmitting the data; and excluding the inserted bits from the converted data of the digital data transmitting device that is input via a transmission path. In a digital data receiving device having a function of reproducing a bit sequence before conversion, the digital data transmitting device may detect sample time ranges of observation at the leading and trailing ends of the block.
A stuff bit insertion method for digital data transmission, characterized in that the number of bits of the same type contained therein is observed for a period shorter than a predetermined time. 2 In a digital data transmitting device, a bit sequence of input digital data is divided into blocks at regular intervals, and a “1” is forcibly placed at the beginning of the block, and a part of the placed “1” is used as a multi-frame synchronization pattern. 2. The digital data transmission stuff bit insertion method according to claim 1, wherein the stuff bit insertion method is shared with a part of "1" of the digital data transmission.