JPH0324066B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that has fewer disconnections and short circuits in a multilayer wiring structure and has excellent moisture resistance.

Conventionally, the flattening technology (technique for smoothing the surface) of semiconductor elements having a multilayer wiring structure is as follows:
A technique called glass flow was commonly used.

That is, in forming an interlayer insulating film, a silicon oxide film (phosphorus glass film) containing phosphorus at a high concentration of 8 to 15 mol % is usually first formed by vapor phase growth. Thereafter, heat treatment is performed in a high-temperature nitrogen atmosphere to impart fluidity to the phosphorus glass film and make the surface smooth, thereby making it difficult for the upper wiring layer on the interlayer insulating film to be disconnected.

Such a glass flow process has the following drawbacks. First, a high concentration phosphorus glass film is
There are many defects, and these defects are particularly aggravated by the hydrofluoric acid-based etching solution used in the post-process, resulting in a very low interlayer dielectric strength voltage, which causes short circuits between interconnects in a multilayer interconnect structure, lowering yield. Ta.
In addition, since the highly concentrated phosphorus glass film has high hygroscopicity,
It was extremely susceptible to water intrusion, reducing reliability.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device with very few disconnections and short circuits in multilayer wiring and excellent moisture resistance.

Hereinafter, the present invention will be explained based on embodiments and with reference to the drawings.

First, as in the conventional method for manufacturing an N-channel Si gate MOS semiconductor device, feed oxide films 2a and 2b of about 1 μm and gate oxide film 3 of about 500 Å are sequentially formed on a P-type crystalline silicon substrate 1. ,
A gate electrode 4 made of polycrystalline silicon doped with N-type impurities and a polycrystalline silicon wiring layer 5,
Source and drain regions 6 and 7 are formed. Furthermore, thermal oxide films 8a, 8b, 8c, and 8d are formed by thermal oxidation (FIG. 1).

Next, a film with a thickness of about 0.5 μm, for example, 4
A low-concentration phosphorus glass film 9 having a phosphorus concentration of mol % is formed (FIG. 2). Note that an oxide film or a nitride film that does not contain phosphorus may be used instead of the phosphorus glass film 9.

Furthermore, a high concentration phosphorus glass film 10 having a phosphorus concentration of, for example, 12 mol% is formed with a thickness of about 1.2 μm and is heat-treated to give fluidity to the high concentration phosphorus glass film and smooth the surface. (Figure 3). Note that instead of the high-concentration phosphorus glass film 10, a material such as a silica film or a resist that becomes fluid and has a smooth surface when heated can be used.

Next, at least part of the high-concentration phosphorus glass film 10 and the low-concentration phosphorus glass film 9 are removed from the entire surface, and the low-concentration phosphorus glass film 9 is exposed while keeping the surface smooth (Fig. 4). ). As a method for removing at least part of the high concentration phosphorus glass film 10 and the low concentration phosphorus glass film 9, anisotropic dry etching such as reactive sputter etching has good controllability and is often used. It will be done.

Next, a silicon oxide film 11 of approximately 0.8 μm is grown by vapor phase growth. The flatness remains intact (Figure 5). The silicon oxide film 11 has few defects, excellent density, and low hygroscopicity of 1 to 7 mol%.
A silicon oxide film containing phosphorus at a concentration of 1 is optimal, but other insulating films with good moisture resistance can also be used.

Next, contact holes 12, 13, and 14 are formed using photoetching technology (FIG. 6).

Next, approximately 1 μm of Al is vapor-deposited to selectively form Al wiring layers 15 and 16, and N-channel Si gate MOS
The semiconductor device is completed (Fig. 7).

According to the present invention, the interlayer insulating film has high density;
Since it is a low-concentration phosphorus glass film or other insulating film with few defects, it has a high interlayer dielectric strength voltage, and is able to prevent short circuits between the gate electrode, polycrystalline silicon wiring layer, and the Al wiring layer that crosses over it. It can be prevented.

Further, since the present invention does not use a highly hygroscopic and highly concentrated phosphorus glass film, it is strong against water intrusion, and the reliability of the device is extremely high.

As explained above, according to the manufacturing method of the present invention, yield and reliability can be greatly improved compared to conventional manufacturing methods.

Note that, as in the embodiment, the present invention is applicable to N-channel
Not limited to Si gate MOS semiconductor devices,
Needless to say, the present invention can be applied to other semiconductor devices having multilayer wiring.

[Brief explanation of the drawing]

1 to 7 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. 1...Silicon base, 2a, 2b...Field oxide film, 3...Gate oxide film, 4...Gate electrode, 5...Polycrystalline silicon wiring layer added with impurities, 6, 7...Source, drain area, 8b,
8b, 8c, 8d... thermal oxide film, 9... silicon oxide film containing low concentration of phosphorus 1, 10... silicon oxide film containing high concentration of phosphorus, 11... containing low concentration of phosphorus Silicon oxide film 2, 12, 13,
14...Contact hole, 15, 16...Aluminum wiring layer.

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor device having a multilayer wiring structure, a semiconductor element and a lower wiring are formed, and on a semiconductor substrate having processing steps, 1 to 7 mol%
After forming a first oxide film containing phosphorus at a higher concentration and forming a second oxide film containing phosphorus at a higher concentration than the first oxide film on the first oxide film, heat treatment is performed. and removing a portion of the second oxide film and the first oxide film by dry etching to a degree that the underlying wiring is not exposed while keeping the surface smooth. and forming a third oxide film containing phosphorus at a concentration of 1 to 7 mol% on the flat first oxide film. Method of manufacturing the device.