JPH0324100B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is a method for demodulating a digital signal that has been modulated according to a modulation method such as a signal that intermittently includes phase information of a bit clock signal. The present invention relates to a digital signal demodulation device for a signal, and particularly to a digital signal demodulation device that can perform smooth demodulation even in the case of an intermittent signal on the time axis.

(Prior Art) It is well known that when recording and transmitting digital signals, the digital signals are modulated using a modulation method selected from among various modulation methods.

A bit clock signal is required for demodulating the demodulated signal, but depending on the modulation method, the bit clock phase information may only be included in the demodulated signal intermittently.

By the way, when generating the bit clock signal required for demodulation from the demodulated signal of a digital signal which only intermittently contains the phase information of the bit clock signal as described above, a phase-locked loop with a normal configuration is used. The fact that the bit clock signal cannot be obtained even when using the demodulated signal is easily understood from the fact that the phase information of the bit clock signal exists only intermittently in the demodulated signal.

Conventionally, for example, in a compact disk playback device, in order to obtain a bit clock signal for demodulating an EFM signal, the pulse width of the longest period pulse in the EFM signal is 11T, and the pulse width of the shortest period pulse is 3T. is measured using a bit clock signal oscillated by a voltage controlled oscillator, and the oscillation frequency of the voltage controlled oscillator is automatically controlled according to the measurement result to automatically change the period of the bit clock signal. However, in this existing proposal, in order to create the control signal to be given to the voltage controlled oscillator, the pulse width of the longest period pulse in the EFM signal is measured at 11T, and the pulse width of the shortest period pulse is measured at 3T. However, there was a problem in that the configuration became complicated.

In order to solve the above-mentioned problems, the applicant company first filed Japanese Patent Application No. 59-62849 (Japanese Patent Application Laid-Open No.
206339), a digital signal modulated according to a modulation method such as a periodic signal that intermittently includes phase information of a bit clock signal is used as a demodulated signal, and the rise of the waveform in the demodulated signal is means for generating a detection window pulse having a predetermined pulse width shorter than the period of the bit clock signal from one or both of the time positions of the bit clock signal and the falling edge; The phase comparator consists of a phase comparator circuit and a voltage controlled oscillator.
A means for applying a comparison wave to the locked loop,
One pulse of both the bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop described above and the pulse generated by a separately provided pulse source is used as the reference pulse for measurement. When the period of the other pulse of both pulses is counted using the reference pulse described above and the measured value is N, then means for generating a first signal when a measured value N when counting the period of the pulse of is equal to or less than a minimum value N1 determined corresponding to an allowable variation range of the oscillation frequency in the voltage controlled oscillator; The measurement value N obtained by counting the period of the other of the two pulses described above using the standard pulse for measurement is determined in accordance with the permissible change range of the oscillation frequency in the voltage controlled oscillator. means for generating a second signal when the maximum value N2 or more; means for obtaining an error signal from the first signal and the second signal; We have proposed a bit clock signal generator for a digital signal demodulator comprising means for controlling the error signal of a phase comparison circuit in a locked loop, and have achieved some results by implementing it.

(Problem to be Solved by the Invention) However, in the previously proposed digital demodulator described above, when the signal to be demodulated has a relatively long no-signal period, the time axis is In the case of the above intermittent signal, when the phase locked loop loses its lock during the no signal period, the phase locked loop is unlocked by the signal that reappears after the said no signal period has elapsed. A problem was that it took a long time to achieve lock, which could cause disturbances in the demodulated signal.

Figure 2 shows an example of the arrangement of signals on the time axis that may cause the above-mentioned problems. As an example of a signal, as shown in the third diagram, a 180 degree symmetrical position around the rotating cylinder RD (a position where the center angle is 180 degrees)
The two magnetic heads Ha and Hb provided at (O indicates the radius at the boundary position of the range, and O indicates the center of the rotating cylinder RD). Each shows the signal obtained when playing back from the magnetic tape MT.

Now, as mentioned above, the wrapping angle of the magnetic tape MT wound around the rotating cylinder RD is smaller than the central angle of the two magnetic heads Ha and Hb attached around the rotating cylinder RD. in case of,
Since the length of the sliding contact section between the magnetic head and the magnetic tape MT is short, (a) wear on the magnetic head is reduced; (b)
Since the friction between the magnetic tape MT and the rotating cylinder surface can be reduced, there is an advantage that the magnetic tape MT can be run at high speed and cueing can be easily performed by high-speed reproduction of information signals, and the linearity of the recorded trace can be improved. Many advantages can be obtained, such as improved performance, the ability to reduce the diameter of the rotating cylinder, the ability to shorten the length of the rotating cylinder in the generatrix direction, and a simpler magnetic tape loading mechanism. , On the other hand, when the wrapping angle of the magnetic tape MT wound around the rotating cylinder RD is smaller than the central angle of the two magnetic heads Ha and Hb attached around the rotating cylinder RD as described above. The signal reproduced from the magnetic tape MT is, of course, a signal that is intermittent on the time axis, that is, a signal that is in a state where signal periods and no-signal periods are arranged alternately on the time axis. Even if such a signal is supplied to the previously proposed digital signal demodulator, the phase-locked loop loses its lock during the no-signal period and reappears after the no-signal period has elapsed. A problem can arise in that it takes a long time for the signal to lock the phased locked loop, thereby causing disturbances in the demodulated signal.

(Means for Solving the Problems) The present invention uses, as a demodulated signal, a digital signal that is modulated according to a modulation method that is composed of a signal that intermittently includes phase information of a bit clock signal. A detection window pulse having a predetermined pulse width shorter than the cycle of the bit clock signal is generated from one or both of the time positions of the rising and falling waves of the demodulated signal. means for applying the detection window pulse as a comparison wave to a phase locked loop comprising a phase comparator circuit and a voltage controlled oscillator; pulse source with period T
2 is a second pulse source that generates a second pulse having a relationship of T2<T1 with respect to the period T1 of the first pulse generated by the first pulse source;
The first pulse generator measures the period T1 of the first pulse generated by the first pulse source, using the bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop as a reference pulse for measurement. The bit clock signal obtained from the measuring means and the voltage controlled oscillator in the phase locked loop described above is used as a reference pulse for measurement.
A second measuring means for measuring the period T2 of the second pulse generated by the second pulse source described above, and a reference that measures the period T1 of the first pulse generated by the first pulse source described above. When the measured value when counting with the pulse of , and the measured value N1 is a maximum value N1l determined in correspondence with the first allowable variation range of the oscillation frequency.
In the above case, when the period T2 of the second pulse generated by the means for generating the second signal and the above-mentioned second pulse source is counted using the above-mentioned reference pulse, the measured value is set as N2. and a second permissible change in the oscillation frequency that is set to have a larger frequency change rate than the frequency change rate in the first permissible change range set for the oscillation frequency of the voltage controlled oscillator. A third signal is generated when the measured value N2 is smaller than a minimum value N2s determined corresponding to the range, and the measured value N2 is a second permissible change in the oscillation frequency in the voltage controlled oscillator. means for generating a fourth signal when it is greater than or equal to a maximum value N2l determined in correspondence with the range; means for obtaining a first error signal from the first signal and the third signal; Means for obtaining a second error signal using the second signal and fourth signal, and controlling the error signal of the phase comparison circuit in the phase locked loop using each of the error signals. a digital signal demodulator comprising a bit clock signal generator comprising means for Detection of a demodulated signal having a predetermined pulse width shorter than the cycle of the bit clock signal from one or both of the rising and falling points of the waveform of the demodulated signal. means for generating a window pulse; means for applying the detection window pulse as a comparison wave to a phase locked loop comprising a phase comparator circuit and a voltage controlled oscillator; and a first pulse having a period of T1. , and the period T2 is T2<
A second pulse source that generates a second pulse having a relationship of T1 and a bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop described above are used as reference pulses for measurement. A first measuring means for measuring the period T1 of the first pulse generated by the pulse source and a bit clock signal obtained from the voltage controlled oscillator in the phase locked loop described above are used as reference pulses for measurement. a second measuring means for measuring the period T2 of the second pulse generated by the second pulse source; and a second measuring means for measuring the period T2 of the second pulse generated by the second pulse source; When the measured value when counting with pulses is N1,
A first signal is generated when the measured value N1 is less than or equal to the minimum value N1s determined corresponding to the first allowable variation range of the oscillation frequency in the voltage controlled oscillator, and the measured value N1 causes the above-mentioned oscillation. means for generating a second signal when the frequency is equal to or greater than a maximum value N1l determined corresponding to the first permissible change range; and a period of the second pulse generated by the second pulse source. A frequency change that is larger than the frequency change rate in the first allowable change range set for the oscillation frequency of the voltage controlled oscillator, where N2 is the measured value when T2 is counted using the reference pulses described above. The third signal is generated when the measured value N2 is smaller than the minimum value N2s determined corresponding to the second permissible change range of the oscillation frequency, which is set to have a means for generating a fourth signal when the measured value N2 is equal to or greater than a maximum value N2l determined corresponding to a second allowable change range of the oscillation frequency in the voltage controlled oscillator; means for obtaining a first error signal by means of a third signal; means for obtaining a second error signal by means of the second signal and fourth signal; means for controlling the error signal of the phase comparison circuit in the phase-locked loop described above; and means for selectively disabling one or both of the first signal and the second signal. The present invention provides a digital signal demodulating device comprising a bit clock signal generating device comprising means for generating a bit clock signal.

(Example) Hereinafter, the specific contents of the digital signal demodulation device of the present invention will be explained in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram for explaining the configuration principle and operating principle of the digital signal demodulation device of the present invention. In FIG. This is an input terminal for a signal to be demodulated by a digital signal modulated according to a modulation method such as a signal that is intermittently included;
The demodulated signal supplied to the detection window pulse generator
Given to DWC.

In the following description, the demodulated signal is a digital signal modulated according to a modulation method such as a periodic signal that intermittently contains phase information of a bit clock signal. It is said that the demodulated signal is a digital signal that is modulated according to a modulation method in which the signal has a pulse width that is an integral multiple of the range.

In the above-mentioned detection window pulse generation circuit DWC, the time position of either the rising edge or the falling edge of the waveform in the demodulated signal input thereto, or
From both time positions, a detection window pulse Pw having a predetermined pulse width Tw shorter than the period T of the bit clock signal Pc described above is generated (in the embodiment described later, the detection window pulse
Pw is shown as having a pulse width of 1/2 of the period T of the bit clock signal Pc), and the detection window pulse Pw generated by the detection window pulse generation circuit DWC described above
The signal is applied as a comparison wave to a phase locked loop PLL that includes a VCO.

FCC is a frequency comparison circuit FCC, and this frequency comparison circuit FCC is composed of a first frequency comparison circuit FCCa and a second frequency comparison circuit FCCb. The second frequency comparison circuit FCCb is supplied with the bit clock signal Pc output from the voltage controlled oscillator VCO in the phased locked loop PLL described above.

A first frequency comparison circuit FCCa and a second frequency comparison circuit in the frequency comparison circuit FCC.
In the FCCb, the bit clock signal Pc obtained from the voltage controlled oscillator VCO in the phase locked loop PLL described above is used as a reference pulse for measurement, and separately provided first and second pulse sources are used.
SSGa, SSGb (not shown in Figure 1)
Measure the period of one particular pulse among the pulses generated.

That is, the first frequency comparison circuit FCCa
Now, let's consider the phase locked loop mentioned above.
Using the bit clock signal Pc obtained from the voltage controlled oscillator VCO in the PLL as a reference pulse for measurement, the period T1 of the pulse generated by the first pulse source SSGa is measured, and the second frequency comparison circuit In FCCb, the period T2 of the pulse generated by the second pulse source SSGb is measured using the bit clock signal Pc obtained from the voltage controlled oscillator VCO in the phase-locked loop PLL as the reference pulse for measurement. be. The pulse period T1 generated by the first pulse source SSGa described above and the second pulse source described above are
The period T2 of the pulse generated by SSGb is the fourth
As shown in figures a and b, T1>T2.

In the first frequency comparator circuit FCCa, the frequency of the bit clock signal Pc output from the voltage controlled oscillator VCO in the phase locked loop PLL is set to the lowest frequency in its first permissible frequency change range. The first signal Ssa is output when the bit clock signal Pc becomes lower than the frequency value, and the frequency of the bit clock signal Pc output from the voltage controlled oscillator VCO in the phase-locked loop PLL mentioned above is lower than its first tolerance value. The second signal Sla is output when the frequency becomes higher than the highest frequency value in the specified frequency change range. The frequency of the bit clock signal Pc is
A second permissible frequency of the oscillation frequency that is set to have a larger frequency change rate than the frequency change rate in the first permissible frequency change range set for the oscillation frequency of the voltage controlled oscillator. When the frequency value becomes lower than the lowest frequency value in the variation range, the third signal Ssb is output, and furthermore, the above-mentioned phase locked signal is output.
When the frequency of the bit clock signal Pc output from the voltage controlled oscillator VCO in the loop PLL becomes higher than the highest frequency value in the second allowable frequency change range, the fourth signal
It is designed to output Slb.

A first signal Ssa and a second signal Sla output from the first frequency comparison circuit FCCa, and a third signal Sla output from the second frequency comparison circuit FCCb.
The signal Ssb and the fourth signal Slb mean that in the error signal generation circuit ESG, the first error signal is generated by the first signal Ssa and the third signal Ssb, and the second error signal is generated by the first signal Ssa and the third signal Ssb. A second error signal is generated by the signal Sla and the fourth signal Slb, and said error signal is connected to the bit clock signal Pc supplied to the phase comparison circuit in the phase locked loop PLL.
used to control the frequency of

As described above, in the digital signal demodulation device of the present invention, the frequency comparison circuit FCC includes the first frequency comparison circuit FCCa and the second frequency comparison circuit FCCb. - Using the bit clock signal Pc output from the voltage controlled oscillator VCO in the locked loop PLL as a reference pulse for measurement, the period T1 of the pulse generated from the first pulse source SSGa is measured, and the period T1 of the pulse generated from the first pulse source SSGa is measured. comparison circuit
In FCCb, the period T2 of the pulse generated from the second pulse source SSGb is measured using the bit clock signal Pc output from the voltage controlled oscillator VCO in the phase locked loop PLL as a reference pulse for measurement. A signal is output when the frequency of the bit clock signal Pc output from the voltage controlled oscillator VCO in the phase-locked loop PLL falls outside the respective allowable frequency ranges due to the pulse periods T1 and T2. This signal is used to generate an error signal to control the period of the bit clock signal Pc output from the voltage controlled oscillator VCO in the phase locked loop PLL. FCCa
a first pulse source on which a frequency comparison is performed;
The period T1 of the pulses generated by SSGa and the period T2 of the pulses generated by the second pulse source SSGa have a relationship of T1>T2, as shown in a and b of FIG. Furthermore, the second frequency is higher than the frequency change rate within the permissible change range of the oscillation frequency of the voltage controlled oscillator VCO in the phase locked loop PLL, which is set by the first frequency comparison circuit FCCa. comparison circuit
For example, since the frequency change rate within the permissible change range of the oscillation frequency of the voltage controlled oscillator VCO in the phase locked loop PLL set by FCCb is larger, The input signal that was being used will be interrupted and the phase locked loop will occur.
Even if the frequency of the bit clock signal Pc output from the voltage controlled oscillator VCO changes significantly when the PLL changes from a locked state to an unlocked state, the phase locked loop PLL can be brought into a locked state in a short time. .

This point will be explained with reference to FIG. 4 as follows. That is, a in FIG. 4 shows the output pulse of the first pulse source SSGa, which is the target of frequency comparison in the first frequency comparison circuit FCCa, and b in FIG.
shows the output pulses of the second pulse source SSGb, which is the subject of frequency comparison, and furthermore,
4c is the reference pulse (voltage controlled oscillator in the phase locked loop PLL) used to measure the period of the output pulse from the first and second frequency comparator circuits FCCa and FCCb.
The bit clock signal Pc obtained as an output pulse from the VCO is shown.

The period T1 of the output pulse of the first pulse source SSGa, which is the target of frequency comparison in the first frequency comparison circuit FCCa, and the second frequency comparison circuit
The second frequency comparison target in FCCb
The period T2 of the output pulse of the pulse source SSGb is:
As is clear from a and b in Figure 4, T1>T2
Also, the first frequency comparison circuit
The first permissible change range α of the frequency of the bit clock signal Pc output from the voltage controlled oscillator VCO of the phase locked loop PLL, which is set in connection with the frequency comparison operation in FCCa, and the second frequency comparison circuit FCCb. The second permissible change range β of the frequency of the bit clock signal Pc output from the voltage controlled oscillator VCO of the phase locked loop PLL, which is set in connection with the frequency comparison operation in the phase locked loop PLL, is defined as
The rate of change in the frequency of the oscillation frequency of the voltage controlled oscillator VCO in the PLL in the first allowable change range α is higher than that of the phase-locked loop.
The rate of change in frequency in the second allowable change range β of the oscillation frequency of the voltage controlled oscillator VCO in the PLL is set to be larger.

Therefore, if the oscillation frequency of the voltage controlled oscillator VCO in the phase-locked loop PLL deviates significantly, the frequency comparison is performed using the output pulse with a short period T2 from the second pulse source SSGb used for frequency comparison. Frequency comparison is performed using the output signal from the second frequency comparison circuit FCCb generated by the frequency comparison and the output pulse with a long period T1 from the first pulse source SSGa used for frequency comparison. The phase-locked loop PLL can be brought into a locked state in a short time by the error signal generated by both the output signal from the first frequency comparator circuit FCCa and the output signal from the first frequency comparator circuit FCCa. Therefore, for a slight deviation in frequency, the first frequency comparison circuit
The error signal generated by the output signal from the FCCa allows the phase locked loop PLL to remain locked at all times.

Next, different embodiments of the digital signal demodulation device of the present invention will be described. 5 and 6 are block diagrams showing different embodiments of the digital signal demodulation device of the present invention, and in FIGS. 5 and 6, 1 is an input terminal for a demodulated signal;
In other words, it is an input terminal for a demodulated signal using a digital signal that is modulated according to a modulation method such as a signal that intermittently includes phase information of a bit clock signal. The demodulated signal is given to the detection window pulse generation circuit DWC.

The above-mentioned detection window pulse generation circuit DWC has a detection window which is shorter than the period T of the above-mentioned bit clock signal Pc from the time position of either the rising edge or the falling edge of the waveform of the signal input thereto, or from both time positions. A detection window pulse Pw having a predetermined pulse width Tw is generated. In the following embodiment, the detection window pulse Pw described above is shown to have a pulse width of 1/2 of the period T of the bit clock signal Pc.

The detection window pulse Pw generated by the detection window pulse generation circuit DWC described above is applied as a comparison wave to the input terminal 10 of a phase locked loop PLL that includes a phase comparison circuit PC and a voltage controlled oscillator VCO. It will be done.

5 and 6, FCC is a first frequency comparison circuit FCCa and a second frequency comparison circuit
Frequency comparison circuit configured with FCCb and
FCC, input terminal 2 of frequency comparison circuit FCC
The above-mentioned phase locked loop
A bit clock signal Pc as shown in FIG. 4c is provided from a voltage controlled oscillator VCO in the PLL. In the frequency comparator circuit FCC shown in FIGS. 5 and 6 above, SSGa
is a first pulse source, SSGb is a second pulse source, and the first pulse source SSGa and the second pulse source
SSGb is configured to include, for example, a crystal oscillator, and a constant period T is emitted from the first pulse source SSGa.
1 pulse and supplies it to the counter CTA, and the second pulse source SSGb outputs a pulse with a constant period T2 and supplies it to the counter CTB.
supply to.

The first frequency comparator circuit FCCa in the frequency comparator circuit FCC uses the bit clock signal Pc shown in FIG. As a reference pulse,
A reference pulse for measurement with the period T1 of the pulse generated by the first pulse source SSGa described above.
Let N1 be the measured value when counting at Pc, and the measured value N1 when counting the period T1 of the pulse generated by the first pulse source SSGa using the reference pulse Pc for measurement is , performs an operation to generate the first signal Ssa when the oscillation frequency of the voltage controlled oscillator is equal to or less than the minimum value N1s determined corresponding to the first allowable variation range α, and also performs the above-mentioned measurement Measured value N1 when counting the period T1 of the pulse generated by the first pulse source SSGa with the reference pulse Pc
is greater than or equal to the maximum value N1l determined in correspondence with the permissible variation range α of the oscillation frequency in the voltage controlled oscillator, the second signal Sla is generated.

The second frequency comparator circuit FCCb in the frequency comparator circuit FCC converts the bit clock signal Pc shown in FIG. As a reference pulse,
A reference pulse for measurement with the period T2 of the pulse generated by the second pulse source SSGb described above.
When the measured value when counting with Pc is N2, the measured value N2 when counting the period T2 of the pulse generated by the second pulse source SSGb mentioned above with the reference pulse Pc for measurement is , performs an operation to generate the third signal Ssb when the oscillation frequency of the voltage controlled oscillator is equal to or less than the minimum value N2a determined corresponding to the second allowable variation range β, and also performs the above-mentioned measurement Measured value N2 when counting the period T2 of the pulse generated by the second pulse source SSGb using the reference pulse Pc
is greater than the maximum value N2l determined in correspondence with the permissible variation range β of the oscillation frequency in the voltage controlled oscillator, the fourth signal Slb is generated.

In the counter CTA, the bit clock signal Pc generated by the voltage controlled oscillator VCO in the phase locked loop PLL is used as a reference pulse for measurement, and the period T of the pulse generated by the pulse source SSGa is used.
1, the measured value N1 corresponding to the pulse period T1 generated by the first pulse source SSGa is transmitted to the first numerical comparator COM1 and the second numerical comparator COM1 through the latch circuit LCA. numerical comparator
Give to COM2.

The counter CTB uses the bit clock signal Pc generated by the voltage controlled oscillator VCO in the phase locked loop PLL as a reference pulse for measurement, and measures the period T2 of the pulse generated by the second pulse source SSGb. The measured value N2 obtained in correspondence with the period T2 of the pulses generated by the pulse source SSGb is sent to the third numerical comparator COM3 and the fourth numerical comparator via the latch circuit LCB.
Give to COM4.

Then, the period T1 of the pulse output from the first pulse source SSGa is counted as the pulse to be counted.
To measure by the number of bit clock signals Pc applied to CTA, the first pulse source
The counter CTA may be cleared at every rising edge of the pulse output from SSGa.

As a result, the count value N1 of the counter CTA described above is equal to the count value N1 of the aforementioned bit clock signal Pc.
It corresponds to the period of
The count value N2 of the counter CTB mentioned above also corresponds to the period of the bit clock signal Pc mentioned above.

The latch circuit LCA described above is the same as the counter described above.
The rising edge of the pulse output from the first pulse source SSGa, which is given as a clear pulse to CTA, is supplied as a latch signal, so that the count value N1 at that time is set to the first
It is given to the second numerical comparators COM1 and COM2.

Furthermore, the latch circuit LCB is configured to operate at that point in time by being supplied as a latch signal with the rising edge of the pulse output from the second pulse source SSGb, which is given as a clear pulse to the counter CTB. The count value N2 is given to the third and fourth numerical comparators COM3 and COM4.

The first numerical comparator COM1 is provided with the count value N1 of the counter CTA corresponding to the cycle of the bit clock signal Pc, and is provided with a value N1s as a threshold value. The second numerical comparator COM2, which is supplied with N1, is supplied with a numerical value N1l as a threshold value.

Further, the third numerical comparator COM3, which is supplied with the count value N2 of the counter CTB corresponding to the period of the bit clock signal Pc described above, is supplied with a numerical value N2s as a threshold value, and the count value of the counter CTB described above is supplied with the value N2s as a threshold value. The fourth numerical comparator COM4, which is supplied with N2, is supplied with a numerical value N2l as a threshold value.

The numerical value N1s given as the threshold value is a count value corresponding to the longest period in the first permissible change range of the period of the bit clock signal Pc, and the numerical value N1l is a count value corresponding to the longest period of the bit clock signal Pc in the first permissible variation range.
This is the count value corresponding to the shortest cycle in the first allowable change range of the cycle.

Also, the numerical value N2s given as the threshold value
is the count value corresponding to the longest period in the second permissible change range of the period of the bit clock signal Pc, and the value N2l corresponds to the shortest period in the second permissible change range of the period of the bit clock signal Pc. It is a count value.

Now, the count value N in the counter CTA mentioned above
1 is N1<N1s, that is, when the period of the bit clock signal Pc becomes longer than the limit value of the first permissible variation range, the first numerical comparator COM1 outputs the first signal by a positive pulse. signal of
Ssa is output, and when the count value N1 of the counter CTA is N1l<N1, that is, when the period of the bit clock signal Pc becomes shorter than the limit value of the first allowable variation range, the second bit clock signal Pc is output. The second signal from the numerical comparator COM2 is a positive pulse.
Sla is output.

Further, when the count value N2 of the counter CTB is N2<N2s, that is, when the period of the bit clock signal Pc becomes longer than the limit value of the second allowable variation range, the third numerical comparator Third signal from COM3 with positive pulse
Ssb is output, and on the other hand, when the count value N2 of the counter CTB is N2l<N2, that is, when the period of the bit clock signal Pc becomes shorter than the limit value of the second allowable variation range, the fourth bit clock signal Pc is output. The fourth signal from the numerical comparator COM4 is a positive pulse.
Slb is output.

The first signal Ssa output from the first numerical comparator COM1 is applied to the fixed contact a of the changeover switch SW1, and
A low level L is applied to the fixed contact b of SW1 via a resistor. Therefore, when the movable contact c of the changeover switch SW1 is switched to the fixed contact a side, the first signal Ssa output from the first numerical comparison circuit COM1 is transferred to the changeover switch SW1.
A NOR circuit is formed through the fixed contact a and the movable contact c.
It is fed to NOR1 as one of its inputs.
The other input of the NOR circuit NOR1 mentioned above is:
A third signal Ssb output from a third numerical comparison circuit COM3 provided in the second frequency comparison circuit FCCb is provided.

In addition, the second signal Sla output from the second numerical comparison circuit COM2 described above is output from the changeover switch SW.
Furthermore, a low level L is applied to the fixed contact b of the changeover switch SW2 through a resistor. Therefore, when the movable contact c of the changeover switch SW2 is switched to the fixed contact a side, the second numerical comparison circuit COM
The second signal Sla output from 2 is the changeover switch
It is supplied as one input to the OR circuit OR1 via the fixed contact a and the movable contact c of SW2. The other input of the OR circuit OR1 is given the fourth signal Slb output from the fourth numerical comparison circuit COM4 provided in the second frequency comparison circuit FCCb.

In the frequency comparison circuit FCC shown in FIG. 5, the output signal S1 from the NOR circuit NOR1 is sent to the error signal generation circuit via the output terminal 3
The second signal S2, which is sent to the input terminal 5 of the ESG and also output from the above-mentioned OR circuit OR1, is sent to the input terminal 6 of the error signal generation circuit ESG via the output terminal 4. , on the other hand, the frequency comparison circuit shown in FIG.
In the FCC, the output signal from the NOR circuit NOR1 is sent to the first error signal generation circuit via the output terminal 3.
The output signal from the OR circuit OR1 is supplied to the input terminal 5 of the ESG1, and the output signal from the OR circuit OR1 is supplied via the output terminal 4 to the input terminal 6 of the second error signal generation circuit ESG2.

When the frequency of the bit clock signal Pc output from the voltage controlled oscillator VCO in the phase locked loop PLL is normal, the first frequency comparison circuit FCCa and the second frequency comparison circuit FCCb are provided. The frequency comparison circuit FCC operates as follows. That is, when the frequency of the bit clock signal Pc output from the voltage controlled oscillator VCO in the phase locked loop PLL is normal, the first to fourth numerical comparators COM1 to COM in the frequency comparison circuit FCC
The output from 4 is low level, the output from NOR circuit NOR1 is high level, and the output from OR circuit OR1 is low level.
The output terminal 3 of the frequency comparison circuit FCC is at a high level, and the output terminal 4 is at a low level.

In this state, the first high-level signal sent from the output terminal 3 of the frequency comparison circuit FCC is supplied to the input terminal 5, and the second low-level signal sent from the output terminal 4 of the frequency comparison circuit FCC is supplied to the input terminal 5. In the error signal generating circuit ESG in the embodiment shown in FIG. 5, the signal is supplied to the input terminal 6.
An analog adder circuit of a resistor network consisting of resistors 100, 101, 7, and 8 generates an intermediate level between the high-level first signal and the low-level second signal supplied to the input terminal. A signal is sent to its output terminal 9.

If the frequency of the bit clock signal Pc output from the voltage controlled oscillator VCO in the phase-locked loop PLL deviates outside the predetermined allowable variation range, the frequency comparison circuit FCC
The state of the level of the output signal from the first to fourth numerical comparators COM1 to COM4 in the first frequency comparison circuit FCCa and the second frequency comparison circuit FCCb at changes as described below,
Output terminals 3, 4 to 5 of the frequency comparison circuit FCC
The first and second signals supplied to the input terminals 5 and 6 of the error signal generation circuit ESG in the illustrated embodiment are outputted via an analog adder circuit of a resistor network consisting of resistors 100, 101, 7, and 8. The level of the signal output to terminal 9 is the bit clock signal.
The level of the bit clock signal Pc differs from the signal level when the frequency of the bit clock signal Pc is normal, depending on the mode of frequency deviation of the bit clock signal Pc.

Now, in the error signal generating circuit ESG shown in FIG. 5, the first signal S1 supplied to its input terminal 5 and its input terminal 6 are
As described above, the analog adder circuit of the resistor network consisting of the resistors 100, 101, 7, and 8 adds the second signal S2 supplied to The signal is supplied to the input terminal 12 of the phase comparator circuit PC in the phase locked loop PLL.

The error signal Se generated by the error signal generation circuit ESG is supplied to the input terminal 12 of the phase comparison circuit PC in the phase locked loop PLL.
This is when the frequency of the bit clock signal Pc generated from the voltage controlled oscillator VCO in the loop PLL is out of the first and second allowable frequency change ranges, and a phase locked loop occurs.
The phase comparator circuit PC in the PLL has its input terminal 1
2, the error signal in the phase comparator circuit PC is controlled by the error signal Se supplied to the phase comparator circuit PC, and the phase locked loop PLL is quickly brought into a state of phase locking.

That is, when the frequency of the bit clock signal Pc is normal, the first signal applied from the frequency comparison circuit FCC to the input terminal 5 of the error signal generation circuit ESG is at a high level, and the first signal applied from the frequency comparison circuit FCC to the input terminal 5 of the error signal generation circuit ESG is at high level. Error signal generation circuit
Since the second signal applied to the input terminal 6 of the ESG is at a low level, if the frequency of the bit clock signal Pc is normal, the error signal generation circuit
The ESG does not generate an error signal, and in this case, the signal sent to the output terminal 9 of the error signal generation circuit ESG is a signal at a level intermediate between the high level and the low level, as described above.

Therefore, when the frequency of the bit clock signal Pc is normal, the error signal of the phase comparison circuit PC is also changed by the signal supplied from the error signal generation circuit ESG to the input terminal 12 of the phase comparison circuit PC. There isn't.

Next, the frequency of bit clock signal Pc becomes higher than in the normal case (bit clock signal Pc
(the period of
When the second signal applied to the input terminal 6 of the frequency comparison circuit FCC becomes high level, even in this state, the first signal applied from the frequency comparison circuit FCC to the input terminal 5 of the error signal generation circuit ESG becomes high level. Since the level of the bit clock signal Pc is high, similar to the signal level when the frequency of the bit clock signal Pc is normal, when the frequency of the bit clock signal Pc exceeds the permissible frequency range mentioned above, the error signal Output terminal 9 of generation circuit ESG
The signal sent to is a high level signal, and in this case, the error signal of the phase comparison circuit PC is changed by the signal supplied from the error signal generation circuit ESG to the input terminal 12 of the phase comparison circuit PC. The frequency of the bit clock signal Pc generated from the voltage controlled oscillator VCO in the phase locked loop PLL is rapidly lowered to a frequency within the permissible frequency range described above.

Next, the frequency of the bit clock signal Pc becomes lower than in the normal case (bit clock signal
(The period of Pc becomes longer than in the normal case), and the error signal generation circuit changes from the frequency comparison circuit FCC described above.
When the first signal applied to the input terminal 5 of the ESG becomes low level, even in this state, the error signal generation circuit is transferred from the frequency comparison circuit FCC to the error signal generation circuit.
Since the level of the second signal applied to the input terminal 6 of the ESG is low, similar to the signal level when the frequency of the bit clock signal Pc is normal, the bit clock signal
When the frequency of Pc becomes lower than the above-mentioned allowable frequency range, the signal sent to the output terminal 9 of the error signal generation circuit ESG becomes a low level signal, and in this case, the error signal generation circuit ESG The error signal of the phase comparator PC is changed by the signal supplied to the input terminal 12 of the phase comparator circuit PC, and the frequency of the bit clock signal PC generated from the voltage controlled oscillator VCO in the phase locked loop PLL is changed. The frequency is rapidly raised to within the permissible frequency range mentioned above.

Next, in the first error signal generating circuit ESG1 shown in FIG. 6, the first signal S1 supplied to its input terminal 5 is applied to the first shift register SR1 via the inverter INV. In addition, the second error signal generating circuit ESG2 receives the second signal S2 supplied to its input terminal 6.
is applied to the second shift register SR2. The first and second shift registers SR1 and SR described above
2 is a clock signal that is the same pulse as the pulse given to the counters CTA, CTB and latch circuits LCA, LCB from the first and second pulse sources SSGA, SSGB provided in the frequency comparison circuit FCC described above. It is supplied as. Each of the first and second shift registers SR1 and SR2 takes in the information given to the data terminal D at the time the clock is supplied thereto and shifts it by one step.

Q1 to Q in the first shift register SR1
The three outputs of Q1 to Q3 in the second shift register SR1 are given to the NAND circuit NAND, and the three outputs of Q1 to Q3 in the second shift register SR1 are supplied to the AND circuit.
Since it is given to AND, the above-mentioned NAND circuit NAND in the first error signal generation circuit ESG1
A low level signal is output to the output side of the shift register SR1 only when all three outputs Q1 to Q3 of the first shift register SR1 become high level.
Further, a high level signal is sent to the output side of the AND circuit AND in the second error signal generating circuit ESG2 only when the three outputs Q1 to Q3 in the second shift register SR2 are all at high level. Output.

On the output side of the NAND circuit NAND provided in the first error signal generation circuit ESG1,
One end of each of resistors 43 and 44 is connected, and one end of each of resistors 45 and 46 is connected to the output side of the second error signal generation circuit ESG2. The high level voltage H in the logic circuit is connected to the other ends of the resistors 43 and 45 described above, and the other ends of the resistors 44 and 46 described above are connected to each other and the output terminal 9 is connected thereto. There is.

Therefore, in the first error signal generating circuit ESG1 having the above-described configuration, the first error is generated unless all three outputs Q1 to Q3 of the first shift register SR1 are at high level. Does not generate a signal. Further, a second error signal generation circuit ESG2 having the above-described configuration is provided.
In this case, the second error signal is not generated unless all three outputs of Q1 to Q3 in the second shift register SR2 are at a high level.

That is, the first and second error signal generating circuits ESG1, having the configuration shown in FIG.
From ESG2, when a signal occurs for a predetermined period or more (in the illustrated example, it is a period of three clocks applied to the shift register, but it goes without saying that the predetermined period can be set arbitrarily). Since the first and second error signals are generated for the first time, in the embodiment shown in FIG. 6, even if a dropout occurs in the demodulated signal supplied to the input terminal 1, In addition, the frequency comparison circuit FCC does not respond one by one,
Therefore, frequency skipping does not occur.

In the apparatus of the embodiment shown in FIG.
Voltage Controlled Oscillator VCO in Locked Loop PLL
When the frequency of the bit clock signal Pc output from the frequency comparison circuit FCC is normal, the output of the NOR circuit NOR1 in the frequency comparator circuit FCC is at a high level, and the output of the OR circuit OR1 is at a low level. The input to the first shift register SR1 to which the high level output from the circuit NOR1 is given via the inverter INV, and the input to the second shift register SR2 to which the low level output from the OR circuit OR1 is given. Both are at low level, and the first and second shift registers
The outputs of SR1 and SR2 are all low level, the output of the NAND circuit NAND is high level, the output of the AND circuit AND is low level, and the first,
The output terminals 9 of the second error signal generating circuits ESG1 and ESG2 have a voltage intermediate between the high level and the low level.

Next, in the apparatus shown in the embodiment of FIG. When the period of the bit clock signal Pc becomes longer than the allowable variation range), the output of the NOR circuit NOR1 in the frequency comparison circuit FCC becomes a low level, and the output of the OR circuit OR1 also becomes a low level.

Therefore, the first shift register SR1 to which the low level output from the NOR circuit NOR1 is made high level through the inverter INV is given as follows.
When the input signal thereto is held at high level for a predetermined period, all three outputs become high level.

On the other hand, in the state we are considering now, the OR circuit
Since the output from the second shift register SR2 to which the low level output from OR1 is given is low level, all outputs from the second shift register SR2 are low level.

Therefore, both the output of the NAND circuit NAND and the output of the AND circuit AND become low level.
First and second error signal generation circuits ESG1, ESG2
from the output terminal 9 of the phase comparison circuit PC to the input terminal 1 of the phase comparison circuit PC.
2, a low level error signal is sent to the first and second error signal generating circuits ESG1,
The phase comparison circuit is controlled by the signal supplied from the output terminal 9 of ESG2 to the input terminal 12 of the phase comparison circuit PC.
The PC error signal is changed and the frequency of the bit clock signal Pc generated from the voltage controlled oscillator VCO in the phase locked loop PLL is rapidly increased to the normal frequency.

Then, in the apparatus shown in the embodiment of FIG. (shorter than the change range of ), the output of the OR circuit OR1 in the frequency comparator circuit FCC becomes high level, and in the above state, the output of the NOR circuit NOR1 also becomes high level.

Therefore, the second shift register SR2 is supplied with a high level output from the OR circuit OR1.
The output from the
All outputs become high level.

On the other hand, in the state we are thinking about now, the Noah circuit
High level output from NOR1 is inverter
The output of the first shift register SR1, which is brought to a low level via INV, becomes a low level.

Therefore, the output of the NAND circuit NAND and the output of the AND circuit AND both become high level,
First and second error signal generation circuits ESG1, ESG2
from the output terminal 9 of the phase comparator circuit PC to the input terminal 1 of the phase comparison circuit PC.
2, a high level error signal is sent to the first and second error signal generating circuits ESG1,
The phase comparison circuit is controlled by the signal supplied from the output terminal 9 of ESG2 to the input terminal 12 of the phase comparison circuit PC.
The PC error signal is changed so that the frequency of the bit clock signal Pc generated from the voltage controlled oscillator VCO in the phase locked loop PLL is rapidly lowered to the normal frequency.

Now, the frequency comparison circuit calculates the period of the pulse with period T1 generated from the first pulse source SSGa.
The bit clock signal Pc output from the voltage controlled oscillator VCO in the phase locked loop PLL when the phase locked loop PLL is normally locked by the counter CTA of the first frequency comparison circuit FCCa in the FCC.
Let N1n be the count value N1 obtained by the counter CTA when measured using the first numerical comparator
The numerical value N1s set in COM1 (the numerical value set corresponding to the lower limit frequency in the first permissible change range of the frequency of the bit clock signal Pc...the first permissible change range of the cycle of the bit clock signal Pc) ) and the second numerical comparator COM2
The numerical value N1l set in (the numerical value set corresponding to the upper limit frequency in the first permissible change range of the frequency of the bit clock signal Pc...
(a value set corresponding to the shortest period in the first permissible variation range of the period of the bit clock signal Pc) is ±1% of the above-mentioned count value N1n.
, i.e. N1s=N1n×0.99, N1l
=N1n×1.01, and
Period T2 generated from second pulse source SSGb
(However, T1>T2) The period of the pulse is determined by the counter CTB of the frequency comparator circuit FCC as a phase locked loop when the phase locked loop PLL is normally locked.
When the count value N2 obtained by the counter CTB when measured using the bit clock signal Pc output from the voltage controlled oscillator VCO in the PLL is N2n, the value N2s set in the third numerical comparator COM3 (the bit clock signal A value set corresponding to the lower limit frequency in the second allowable change range of the PC frequency...Bit clock signal
(the value set corresponding to the longest period in the second allowable change range of the period of Pc) and the fourth
The numerical value N2 set in the numerical comparator COM4 of
l (a numerical value set corresponding to the upper limit frequency in the second permissible change range of the frequency of the bit clock signal Pc... corresponds to the shortest period in the second permissible change range of the period of the bit clock signal Pc) (the numerical value set by
Taking the case where N2n×0.95 and N2l=N2n×1.05 are respectively set as an example, when an intermittent demodulated signal is demodulated by the digital signal demodulation device of the present invention, the demodulated signal becomes blank. The phase changes from the signal period to the period in which the signal exists.
The operating state when the locked loop PLL transitions from the unlocked state to the locked state is as follows.

In other words, if the demodulated signal to be demodulated by the digital signal demodulator has a signal period and a no-signal period aligned on the time axis as shown in FIG. Phase Locked Loop PLL Voltage Controlled Oscillator
The frequency (period) of the bit clock signal output from the VCO may deviate greatly from the normal value, but as mentioned above, the voltage controlled oscillator of the phase locked loop PLL
When the frequency (period) of the bit clock signal output from the VCO deviates significantly from the normal value, the second frequency comparison circuit FCCb in the frequency comparison circuit FCC detects the bit clock signal Pc.
deviates from the normal value by ±5% or more from the second pulse source SSGb, which has a period T1>T2 with respect to the period T1 of the pulse generated by the first pulse source SSGa. The error signal generated by the error signal generation circuit ESG is generated by the voltage controlled oscillator VCO in the phase-locked loop PLL. It operates to quickly bring the frequency of the bit clock signal Pc close to the normal frequency,
Further, the first frequency comparison circuit FCCa in the frequency comparison circuit FCC receives the above-mentioned bit clock signal.
The frequency comparator circuit FCC operates to bring the frequency of the bit clock signal Pc within ±1% of the normal value within a short period of time. I will do it.

As is clear from the above, the frequency comparison operation performed by the frequency comparison circuit FCC described above is based on the period generated by the first pulse source SSGa. During the pulse period of T1, the phase
Voltage Controlled Oscillator VCO in Locked Loop PLL
The number of bit clock signals N1 generated from
By determining whether the number is within the allowable range, is smaller than the minimum number N1s of the number within the allowable range, or is greater than the maximum number N1l of the number within the allowable range. Furthermore, the frequency comparison operation in the second frequency comparison circuit FCCb is performed with a period T2 having a relationship of T1>T2 with respect to the period T1 of the pulse generated by the first pulse source SSGa. a second pulse source having
Is the number N2 of bit clock signals generated from the voltage controlled oscillator VCO in the phase locked loop PLL during the period of the pulse of period T2 generated by SSGb within the allowable range? The number N is smaller than the minimum number N2s, or the maximum number N2s is within the allowable range.
The first pulse source used for the frequency comparison operation in the first frequency comparison circuit FCCa.
If the period T1 of the pulses generated by SSGa is too short, the phase locked loop PLL
When the bit clock signal is locked in, or when the frequency of the bit clock signal fluctuates due to noise, etc., the frequency change may exceed the first allowable frequency range, and the signal is output from the first frequency comparison circuit FCC. Therefore, the period T1 of the pulses generated by the first pulse source SSGa used for the frequency comparison operation in the first frequency comparison circuit FCCa is set to be long. , a judgment is made as to whether the count value over that long period exceeds the above-mentioned ±1% on average.

Now, in order to adjust the device by changing the gain of the control loop in the bit clock signal generator of the digital signal demodulator, for example, in the embodiment shown in FIG. Resistor 7 of the resistor network that constitutes the analog adder circuit in ESG,
This can be carried out by changing the resistance values of 8, 100, and 101, but other adjustment means include changing the first and second frequencies in the frequency comparison circuit FCC as shown in FIG. This can be implemented by changing the pulse width of the output signals from the comparison circuits FCC1 and FCC2 using the monostable multivibrators MM1 and MM2. NOR circuit NOR1 shown in FIG.
The OR circuit OR1 indicates the NOR circuit NOR1 and the OR circuit OR1 shown in FIG. 5, respectively.

FIG. 13 shows the output signal from the NAND circuit NAND and the AND circuit in the first and second error signal generation circuits ESG1 and ESG2 in the embodiment shown in FIG.
This is a configuration example in which the gain of one control loop is changed by changing the pulse width of the output signal from the AND circuit using monostable multivibrators MM1 and MM2, thereby adjusting the device. , NAND circuit NAND, AND circuit AND, and resistors 43 to 46 shown in FIG.
etc., are the NOR circuit shown in Figure 6.
1. OR circuit OR1 and resistors 43 to 46 are shown.

Next, the changeover switch provided in the frequency comparator circuit FCC shown in Figs. 5 and 6 will be explained.
SW1 and SW2 will be explained. If the demodulated signal to be demodulated in the digital signal demodulation circuit of the present invention is, for example, a reproduced signal from a magnetic recording/reproducing device, the magnetic tape may be rapidly running by fast forwarding or rewinding. When this happens, the frequency of the demodulated signal deviates from the normal frequency by a wide range.

Even if the demodulated signal is not a reproduced signal from a magnetic recording/reproducing device, if the frequency of the demodulated signal deviates significantly from the normal frequency, the frequency comparison circuit
In the first frequency comparison circuit FCC1 and the second frequency comparison circuit FCC2 in the FCC, effective operation cannot be expected for the first frequency comparison circuit FCC1, which has a narrow allowable frequency change range. is easy to understand.

Therefore, if the frequency of the demodulated signal deviates significantly from the normal frequency as described above, the movable contacts c of the changeover switches SW1 and SW2 are switched to the fixed contacts b side, and the permissible frequency change is made. The frequency comparison operation of the first frequency comparison circuit FCC1, which has a narrow range, is made to be unrelated to the operation of the frequency comparison circuit FCC, and the frequency comparison operation of the frequency comparison circuit FCC is made to have a wide frequency change range. If the frequency comparison circuit FCC2 is configured to perform this operation exclusively, when the frequency of the bit clock signal falls within the permissible frequency change range of the second frequency comparison circuit FCC2, the second bit clock signal is
The frequency comparison operation in the frequency comparison circuit FCC2 can be performed stably without being disturbed by the meaningless frequency comparison operation by the first frequency comparison circuit FCC1, which has a narrow allowable frequency change range. In addition, the aforementioned changeover switch SW
1, one or both of the movable contacts c of SW2 may be switched to the fixed contact b side.

In addition, in implementation, a third frequency comparison circuit FCCc having a wider allowable frequency change range than the above-mentioned second frequency comparison circuit FCCb is constructed as shown in FIG. In addition, if the frequency of the bit clock signal deviates by a wider range, the third frequency comparator circuit FCCc
The frequency comparison operation may be performed only by In FIG. 14, Ssc, Slc, etc. are signals similar to the previously described signals Ssa, Ssb, Slb, etc.

FIG. 15 shows another configuration example of the configuration example shown in FIG. 12 already described in which the device is adjusted by changing the gain of the control loop of the bit clock signal generator of the digital signal demodulator. In this configuration example, MM1, MM2, MM
3, MM4 is monostable multivibrator, SW
3. SW4 is a changeover switch, and the first
frequency comparison circuit FCCa, second frequency comparison circuit
FCCb, NOR circuit NOR1, OR circuit OR1, etc. correspond to the first frequency comparison circuit FCCa, second frequency comparison circuit FCCb, NOR circuit NOR1, and OR circuit OR1 in FIG. 5, respectively. Also, the 16th
Figures a and b show examples of the configuration of the changeover switches SW3 and SW4 used in the fifteenth embodiment.

Next, the phase comparator circuit in the phase locked loop PLL shown in FIGS. 5 and 6.
The configuration and operation of the PC will be explained. The phase locked phase shown in Figures 5 and 6
In the phase comparator circuit PC in the loop PLL, the detection window pulse generated by the detection window pulse generation circuit DWC as shown in a in FIG. Pw is supplied to the input terminal 11.
Voltage Controlled Oscillator VCO in Locked Loop PLL
A bit clock signal Pc, for example as shown in FIG. 7b, generated at
(Pc exemplifies the case where the voltage controlled oscillator VCO in the phase locked loop PLL generates a bit clock signal Pc having a regular period).

The detection window pulse Pw supplied to the input terminal 10 described above is supplied to the NAND circuit 14 as one input thereof, and is also supplied to the exclusive OR circuit 1.
5 is also given as one of its inputs. Further, the bit clock signal Pc supplied to the input terminal 11 described above is supplied to the NAND circuit 14 as its other input.

The detection window pulse Pw shown in FIG. 7a,
The bit clock signal shown in FIG.
The above-mentioned NAND circuit 14 is given Pc.
, the pulse as shown in Fig. 7c
Pn is output, and this pulse Pn is supplied to the aforementioned exclusive OR circuit 15 as its other input, and is also supplied to the exclusive OR circuit 16 as its one input.

The pulse Pn shown at c in FIG. 7 outputted from the NAND circuit 14 is the bit clock signal Pc.
The rising edge of the waveform of the detection window pulse Pw, in which the rising edge of the waveform is ahead of the falling edge of the waveform of This is the pulse that forms the edge.

The above pulse Pn is given to the exclusive OR circuit 16 as one input thereof, and the high level voltage H in the logic circuit is supplied to the other input of the exclusive OR circuit 16. The output side of the exclusive OR circuit 16 is
A pulse Pnr (d in FIG. 7) having a polarity opposite to that of the pulse Pn shown in FIG. 7 is output.

As mentioned above, the detection window pulse Pw supplied to the input terminal 10 and the pulse Pn outputted from the NAND circuit 14 are supplied from the exclusive OR circuit 15 as two inputs. The pulse Px as shown in FIG.
The falling edge of the bit clock signal Pc as shown in FIG. A pulse Px whose falling edge is the falling edge and whose rising edge is the falling edge of the detection window pulse Pw described above is output. A resistor 1 is connected to the output side of the exclusive OR circuit 15 described above.
One end of each of resistors 9 and 21 is connected to the output side of the exclusive OR circuit 16, and one end of each of resistors 20 and 22 is connected to the output side of the exclusive OR circuit 16. A high level voltage H in the logic circuit is connected to the other ends of the resistors 19 and 20, and the other ends of the resistors 21 and 22 are connected to each other at a connection point A. ing.

The connection point A is connected to one end of a noise reduction circuit 29 consisting of diodes 27 and 28 that are connected in parallel with opposite connection polarities, and the other end of the noise reduction circuit 29 is connected to the connection point A. is operational amplifier 3
It is connected to the inverting input terminal of 0.

Therefore, the pulse Px as shown in e of FIG. 7 outputted from the exclusive OR circuit 15 described above is
The pulse Pnr as shown in e in FIG. 7 outputted from the exclusive OR circuit 16 described above is
The seventh
An addition signal Pa as shown in f in the figure is output.

The addition signal Pa appearing at point A as described above is
It is connected to the operational amplifier 30 via the noise reduction circuit 29.
Since only the signals exceeding the threshold voltages of the diodes 27 and 28 in the noise reduction circuit 29 are supplied to the inverting input terminal of the operational amplifier 30 when applied to the inverting input terminal of the noise reduction circuit 29 described above. This allows the noise component of the control signal supplied to the voltage controlled oscillator VCO to be reduced.

The signal supplied to the inverting input terminal of the operational amplifier 30 is integrated by the operational amplifier 30 and supplied from the output terminal 13 to the voltage controlled oscillator VCO as an oscillation frequency control voltage. The non-inverting input terminal of the operational amplifier 30 described above is supplied with the voltage at point C obtained by adding the output voltages of the exclusive OR circuits 17 and 18 by the analog adding circuit, and The operational amplifier 30 performs an integration operation on the signal supplied to the inverting input terminal of the operational amplifier 30, using the voltage appearing at the point C as a threshold value.

That is, the exclusive OR circuit 17 has two input signals to the terminal 3.
The exclusive OR circuit 18 is supplied with the voltage from the terminal 32 and the low level voltage in the logic circuit as two input signals thereto. A high level voltage is given. The voltage applied to the terminal 32 described above may be a high level voltage in the logic circuit, a low level voltage in the logic circuit, or the output voltage of the NAND circuit 14 described above.

The output side of the exclusive OR circuit 17 is connected to the high level voltage H in the logic circuit via a resistor 23 and to point C via a resistor 25. The output side of the summation circuit 18 is connected to the high level voltage H in the logic circuit via the resistor 24 and to point C via the resistor 26, so that the exclusive OR is performed as described above. circuit 17,1
The voltage at point C obtained by adding the output voltages of 8 and 8 by the analog adder circuit is applied to the non-inverting input terminal of the operational amplifier 30, and the operational amplifier 30 described above Using the voltage at the point as a threshold, an integration operation is performed on the signal supplied to the inverting input terminal of the operational amplifier 30.

In FIG. 7, H indicates a high level voltage in the logic circuit, L indicates a low level voltage in the logic circuit, and M indicates a high level voltage in the logic circuit and a low level voltage in the logic circuit. This is the voltage obtained as a result of being added in an analog manner.

As can be seen by referring to the waveform diagrams shown in FIGS. 7a to 7f, the exclusive OR circuit 1
5 and the pulse width Pnr output from the exclusive OR circuit 16.
As shown in d and e of the figure, when both pulses have the same pulse width, the result of the integral operation in the operational amplifier 30 that includes a resistor 34 and a capacitor 33 is 0, and the signal level of the output signal from the phase comparator circuit PC in this case maintains the previous voltage, so the output signal from the phase comparator circuit PC does not charge or discharge the voltage controlled oscillator VCO. do not have.

However, the relative phase relationship between the detection window pulse Pw shown in FIG. 7a and the bit clock signal Pc shown in FIG. 7b is not shown in FIGS. If you deviate from the current state,
Since the pulse width of the pulse Pnr shown in d of FIG. 7 and the pulse width of the bit clock signal Px shown in e of FIG. 7 are different from each other,
As a result of the integral operation performed in the operational amplifier 30, an error signal of positive polarity or negative polarity is generated;
Accordingly, the voltage controlled oscillator VCO oscillates the detection window pulse Pw so that the relative phase relationship between the detection window pulse Pw and the bit clock signal Pc is restored to the normal state shown in FIG. 7a and b. Frequency is automatically controlled.

Note that a noise reduction circuit 37 consisting of two diodes 35 and 36 connected with opposite polarities is connected between the point B and the input terminal 12. The input terminal 12 is supplied with first and second error signals S1e and S2e from the first and second error signal generation circuits ESG1 and ESG2, which have already been described.

FIG. 8 is a block diagram showing another example of the configuration of the phase comparison circuit PC. In this FIG. The same drawing symbols as those used in the figures are given. Also, the 9th
Figures a to e are waveform diagrams of the operation explanatory diagram of the phase comparison circuit PC shown in Figure 8 when the voltage controlled oscillator VCO is generating a bit clock signal with a regular cycle, and a to e of Figure 10 is a voltage controlled oscillator
11 is a waveform diagram for explaining the operation of the phase comparator circuit PC shown in FIG. 8 in a state where the VCO is generating a bit clock signal with a cycle shorter than the normal cycle, and a to e in FIG. 11 are voltage controlled oscillator
8A and 8B are waveform diagrams for explaining the operation of the phase comparator circuit PC shown in FIG. 8 in a state where the VCO is generating a bit clock signal having a longer period than the normal period.

In FIG. 8, the detection window pulse Pw supplied to the input terminal 10 is supplied to the inverter 39 and also to the clear terminal of the D-type flip-flop 41. Further, the bit clock signal Pc supplied to the input terminal 11 is supplied to the inverter 38 and also to the clock terminal of the D-type flip-flop 41.

The output signal of the inverter 39 described above is supplied to the clock terminal of a D-type flip-flop 42.
Further, the output signal of the inverter 38 described above is D
The clear terminal and the data terminal of the type flip-flop 42 are provided. Furthermore, the data terminal of the D-type flip-flop 41 is supplied with a high-level voltage H in the logic circuit.
A resistor 2 is connected to the Q terminal of the type flip-flop 41.
0 and 22 are connected to the Q-bar terminal of the D-type flip-flop 42, and resistors 19 and 22 are connected to each other.
1 is connected at one end.

Furthermore, the low level voltage L in the logic circuit is supplied to the clock terminal, data terminal, clear terminal, etc. of the D-type flip-flop 40, and one end of each of the resistors 24 and 26 is connected to the Q terminal of the D-type flip-flop 40. The Q-bar terminal of the D-type flip-flop 40 is connected to one end of each of the resistors 23 and 25.

The other ends of the resistors 19, 20, 23, and 24 are connected to the high-level voltage H in the logic circuit, and the other ends of the resistors 21 and 22 are connected to point A, and the resistors 25 , 26 is C
Connected to the dots.

The point A mentioned above is connected to two diodes 2
It is connected to the inverting input terminal of the operational amplifier 30 via the noise reduction circuit 29 consisting of 7 and 28 and the point B.
Further, the above-mentioned point C is connected to the non-inverting input terminal of the operational amplifier 30. A noise reduction circuit 37 consisting of two diodes 35 and 36 is connected between the above-mentioned point B and the input terminal 12. A series connection circuit including a resistor 34 and a capacitor 33 is connected between the output side and the inverting input terminal of the operational amplifier 30 described above.

When the bit clock signal Pc generated by the voltage controlled oscillator VCO has a regular period, the phase comparator circuit PC shown in FIG. Perform an action that results in something like the one shown below.

That is, in the waveform diagram shown in FIG. 9, a in FIG. 9 is the detection window pulse Pw supplied to the input terminal 10 in the phase comparison circuit PC shown in FIG.
In addition, b in Fig. 9 is the phase comparator circuit PC shown in Fig. 8.
The bit clock signal Pc supplied to the input terminal 11 of FIG. Furthermore, d in FIG. 9 shows an output signal that is always at a high level and appears at the Q-bar terminal of the D-type flip-flop 42 in the phase comparison circuit PC shown in FIG. 8, and e in FIG. are the always low level output signal appearing at the Q terminal of the D type flip-flop 41 and the always high level output signal appearing at the Q bar terminal of the D type flip flop 42 in the phase comparator circuit PC shown in FIG. is the resistance 21,2
This shows the state of the output signal that appears at point A after being added by the analog adder circuit consisting of two circuits. In the phase comparator circuit PC shown in FIG. 8 in the state where No error signal is generated.

Next, in a state where the voltage controlled oscillator VCO is generating a bit clock signal Pc having a cycle shorter than the normal cycle as shown in FIG. 10b, the phase comparator circuit PC shown in FIG. At the Q terminal of the type flip-flop 41, as shown in FIG. 10c, a pulse appears that rises at the rising edge of the bit clock signal Pc and falls at the falling edge of the detection window pulse Pw. At point A in the phase comparator circuit PC shown in FIG. 8 when the controlled oscillator VCO is generating a bit clock signal Pc with a cycle shorter than the normal cycle,
The pulse shown at c in FIG. 10 appearing at the Q terminal of the D-type flip-flop 41 and the
A pulse shown at e in FIG. 10 appears at point A, which is obtained by adding the always high level H signal shown at d in the figure by an analog addition circuit consisting of resistors 21 and 22.

Then, the pulse shown in e of FIG.
is supplied to the inverting input terminal of Furthermore, the non-inverting input terminal of the operational amplifier 30 is supplied with a voltage (logic circuit Since the operational amplifier 30 uses the voltage applied to the non-inverting input terminal as a threshold value, the operational amplifier 30 applies the voltage to the inverting input terminal using the voltage applied to the non-inverting input terminal as a threshold. It integrates the supplied voltage to generate an error signal and sends it to output terminal 1.
3 to the voltage controlled oscillator VCO. The voltage controlled oscillator VCO is automatically controlled to lower its oscillation frequency by the above error signal, and the bit clock signal generated by the voltage controlled oscillator VCO is returned to its normal cycle.

Now, in a state where the voltage controlled oscillator VCO is generating a bit clock signal Pc with a period longer than the normal period as shown in FIG. 11b, the D-type phase comparator circuit PC shown in FIG. At the Q-bar terminal of the flip-flop 42, a pulse appears which falls at the falling edge of the detection window pulse Pw and rises at the rising edge of the bit clock signal Pc, as shown in d of FIG. When the voltage controlled oscillator VCO is generating a bit clock signal Pc with a period longer than the normal period, the phase comparator PC shown in FIG. The pulse shown in d in Figure 11,
The signal shown at the Q terminal of the D-type flip-flop 41 and always at the same signal level shown at c in FIG. A pulse appears at point A.

Then, the pulse shown in e of FIG.
is supplied to the inverting input terminal of Furthermore, the non-inverting input terminal of the operational amplifier 30 is supplied with a voltage (logic circuit Since the operational amplifier 30 uses the voltage applied to the non-inverting input terminal as a threshold value, the operational amplifier 30 applies the voltage to the inverting input terminal using the voltage applied to the non-inverting input terminal as a threshold. It integrates the supplied voltage to generate an error signal and sends it to output terminal 1.
3 to the voltage controlled oscillator VCO. The voltage controlled oscillator VCO is automatically controlled to increase its oscillation frequency by the error signal described above, and the bit clock signal generated by the voltage controlled oscillator VCO is returned to its normal cycle.

As mentioned above, phase locked loop
If the period of the bit clock signal Pc generated by the voltage controlled oscillator VCO of the PLL is normal, the error signal generation circuit (the error signal generation circuit in Figure 5)
The output signals of ESG (first and second error signal generating circuits ESG1 and ESG2 in Fig. 6) do not become frequency error signals, and in this case, the input signal from the frequency comparison circuit FCC to the phase comparison circuit PC is The error signal of the phase comparison circuit PC is not changed by the signal supplied to the terminal 12 either.

Next, when the period of the bit clock signal Pc generated by the voltage controlled oscillator VCO of the phase-locked loop PLL becomes shorter than in the normal case, the output signal of the error signal generation circuit described above is The high level signal is used as a frequency error signal for the phase comparison circuit.
By being supplied to the input terminal 12 of the PC, the voltage at point B in the phase comparison circuit PC is held at a high level in the logic circuit, so the error signal of the phase comparison circuit PC is changed, and the voltage at the point B in the phase comparison circuit PC is changed.
A control signal is given to the voltage controlled oscillator VCO to rapidly lower its oscillation frequency, so that the oscillation frequency of the voltage controlled oscillator VCO is rapidly lowered and the period of the bit clock signal is brought to a normal value. It is.

Contrary to the above, phase locked loop
If the period of the bit clock signal Pc generated by the voltage controlled oscillator VCO of the PLL is longer than normal, the error signal generation circuit described above
The signals applied to the input terminals 5 and 6 of the ESG are both low level signals.

Therefore, the phase locked loop
When the period of the bit clock signal Pc generated by the voltage controlled oscillator VCO of the PLL becomes longer than the normal case, the output signal from the error signal generation circuit described above is made a low level signal in the logic circuit, By supplying it as a frequency error signal to the input terminal 12 of the phase comparison circuit PC, the voltage at point B in the phase comparison circuit PC is held at a low level in the logic circuit, so that the error signal of the phase comparison circuit PC is changed, and a control signal is given from the phase comparator circuit PC to the voltage controlled oscillator VCO to rapidly increase its oscillation frequency.
The oscillation frequency of the VCO is rapidly increased and the period of the bit clock signal is brought to a normal value.

(Effects) As is clear from the detailed explanation above, the digital signal demodulator of the present invention is capable of modulating bit clock signals according to a modulation method that includes signals that intermittently include phase information. The digital signal to be demodulated is a digital signal to be demodulated, and from the time position of either the rising edge or the falling edge of the waveform in the demodulated signal, or both time positions, a predetermined period shorter than the period of the bit clock signal mentioned above is set. means for generating a detection window pulse having a pulse width; means for applying the detection window pulse as a comparison wave to a phase locked loop comprising a phase comparator circuit and a voltage controlled oscillator; a first pulse that generates a first pulse of
and a second pulse source that generates a second pulse whose period T2 is in the relationship T2<T1 with respect to the period T1 of the first pulse generated by the first pulse source. , a first pulse generator for measuring the period T1 of the first pulse generated by the first pulse source, using the bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop as a reference pulse for measurement. a measuring means, and
The second pulse generator measures the period T2 of the second pulse generated by the second pulse source, using the bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop as a reference pulse for measurement. When the measurement means and the measurement value obtained by counting the period T1 of the first pulse generated by the above-mentioned first pulse source using the above-mentioned reference pulse are set as N1, the measurement value N1 is the voltage controlled oscillator. A first signal is generated when the first tolerance of the oscillation frequency is equal to or less than a minimum value N1s determined in correspondence with a change range, and the measured value N1 is a change in the first tolerance of the oscillation frequency. means for generating a second signal when the value is equal to or greater than a maximum value N1l determined corresponding to the range; and a means for generating a second signal when the period T2 of the second pulse generated by the second pulse source is set to the reference pulse as described above. The measured value when counting is N2
When the oscillation frequency of the voltage controlled oscillator is set to have a second rate of change in frequency that is larger than the rate of change in the first allowable change range set for the oscillation frequency of the voltage controlled oscillator. A third signal is generated when the measured value N2 is smaller than the minimum value N2s determined corresponding to the allowable variation range, and the measured value N2 is the second signal of the oscillation frequency in the voltage controlled oscillator. A first error signal is obtained by means of generating a fourth signal when the value is equal to or greater than a maximum value N2l determined corresponding to an allowable variation range, and the first signal and third signal described above. means for obtaining a second error signal using the second signal and fourth signal; and means for obtaining a second error signal using the second signal and the fourth signal; A digital signal demodulator comprising a bit clock signal generator comprising means for controlling the signal, and a digital signal modulated according to a modulation method such as a signal comprising a bit clock signal intermittently containing phase information of the bit clock signal. The signal is a demodulated signal, and a predetermined pulse width shorter than the cycle of the bit clock signal is determined from one or both of the rising and falling points of the waveform of the demodulated signal. means for generating a detection window pulse having a period of T1; a first pulse source that generates a pulse of
The bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop is used as a reference pulse for measurement, and The first measuring means for measuring the period T1 of one pulse, and the second pulse source described above, using the bit clock signal obtained from the voltage controlled oscillator in the phase locked loop as a reference pulse for measurement. a second measuring means for measuring the period T2 of the generated second pulse;
The period T1 of the first pulse generated by the pulse source of
When N1 is the measured value when counted using the above-mentioned reference pulse, the measured value N1 is equal to or less than the minimum value N1s determined in correspondence with the first allowable range of oscillation frequency in the voltage controlled oscillator. generate a first signal when the measured value N1 is equal to or greater than a maximum value N1l determined in correspondence with the first allowable variation range of the oscillation frequency; and a period T of a second pulse generated by the second pulse source mentioned above.
2 is counted using the reference pulse described above and the measured value is N2, the frequency change is larger than the frequency change rate in the first allowable change range set for the oscillation frequency of the voltage controlled oscillator. The third signal is generated when the measured value N2 is smaller than the minimum value N2s determined corresponding to the second permissible change range of the oscillation frequency, which is set to have a means for generating a fourth signal when the measured value N2 is equal to or greater than a maximum value N2l determined corresponding to a second allowable change range of the oscillation frequency in the voltage controlled oscillator; means for obtaining a first error signal by means of a third signal; means for obtaining a second error signal by means of the second signal and fourth signal; means for controlling the error signal of the phase comparator circuit in the phase locked loop described above;
Since this digital signal demodulation device is equipped with a bit clock signal generating device comprising means for selectively disabling one or both of the signals and the second signal, the digital signal of the present invention According to the signal demodulator, the signal to be demodulated is intermittent on the time axis with relatively long no-signal periods, and phase-locked signals occur during the no-signal periods. - Even when the loop is unlocked, the phase-locked loop is quickly locked within a short time by the signal that appears again after the above-mentioned no-signal period has elapsed, and the present invention According to the digital signal demodulation device, the problems in the conventional digital signal demodulation devices described above can be satisfactorily solved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the configuration principle and operating principle of the digital signal demodulation device of the present invention.
Figure 2 is an example of a signal that is intermittent on the time axis with relatively long non-signal periods, and Figure 3 is an example of a magnetic head portion of a rotating magnetic head type magnetic recording/reproducing device. 4 and 7, and FIGS. 9 to 11 are explanatory waveform diagrams. FIGS. 5 and 6 are block diagrams of different embodiments of the digital signal demodulation device of the present invention, and FIGS. 8 and 12 to 16 are block diagrams of some components of the digital signal demodulation apparatus of the present invention. DWC...detection window pulse generation circuit, PLL...phase locked loop, PC...phase comparison circuit, VCO...voltage controlled oscillator, FCC...frequency comparison circuit, FCCa...first frequency comparison circuit,
FCCb...Second frequency comparison circuit, ESG...Error voltage generation circuit, ESG1...First error voltage generation circuit, ESG2...Second error voltage generation circuit,
SSGa...first pulse source, SSGb...second pulse source, SW1, SW2...first and second changeover switches.

Claims (1)

[Claims] 1. A demodulated signal is a digital signal modulated according to a modulation method such as a signal that intermittently includes phase information of a bit clock signal;
A detection window pulse having a predetermined pulse width shorter than the cycle of the bit clock signal is generated from one or both of the time positions of the rising and falling waves of the demodulated signal. means for applying the detection window pulse as a comparison wave to a phase locked loop comprising a phase comparator circuit and a voltage controlled oscillator; and a second pulse source that generates a second pulse whose period T2 is in the relationship T2<T with respect to the period T1 of the first pulse generated by the first pulse source. , a first pulse generator for measuring the period T1 of the first pulse generated by the first pulse source, using the bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop as a reference pulse for measurement. The period T2 of the second pulse generated by the second pulse source is determined by using the bit clock signal obtained from the voltage controlled oscillator in the phase locked loop as a reference pulse for measurement. When the second measuring means for measuring and the measured value when counting the period T1 of the first pulse generated by the above-described first pulse source with the above-mentioned reference pulse are set as N1, the measured value N1 is the first allowable oscillation frequency in the voltage controlled oscillator when it is less than the minimum value N1s determined in correspondence with the variation range.
The signal N1 is generated, and the measured value N1 is
means for generating a second signal when the oscillation frequency is equal to or greater than a maximum value N1l determined corresponding to the first permissible variation range of the oscillation frequency; and a second signal generated by the second pulse source described above; The frequency change rate in the first allowable change range set for the oscillation frequency of the voltage controlled oscillator is given by N2, which is the measured value when the period T2 of the pulse is counted using the reference pulse described above. The third signal is transmitted when the measured value N2 is smaller than the minimum value N2s determined corresponding to the second allowable change range of the oscillation frequency, which is set to have a large frequency change rate compared to the second allowable change range of the oscillation frequency. and means for generating a fourth signal when the measured value N2 is equal to or greater than a maximum value N2l determined corresponding to a second permissible change range of the oscillation frequency in the voltage controlled oscillator; means for obtaining a first error signal from the first signal and the third signal; means for obtaining the second error signal from the second signal and the fourth signal; A digital signal demodulator comprising a bit clock signal generator comprising means for controlling the error signal of the phase comparison circuit in the phase locked loop described above by each error signal. 2. A demodulated signal is a digital signal that is modulated according to a modulation method that is composed of a signal that intermittently contains phase information of a bit clock signal;
A detection window pulse having a predetermined pulse width shorter than the cycle of the bit clock signal is generated from one or both of the time positions of the rising and falling waves of the demodulated signal. means for applying the detection window pulse as a comparison wave to a phase locked loop comprising a phase comparator circuit and a voltage controlled oscillator; and a second pulse source that generates a second pulse whose period T2 is in the relationship T2<T1 with respect to the period T1 of the first pulse generated by the first pulse source. , a first pulse generator for measuring the period T1 of the first pulse generated by the first pulse source, using the bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop as a reference pulse for measurement. and the bit clock signal obtained from the voltage controlled oscillator in the phase locked loop described above as a reference pulse for measurement.
The period T2 of the second pulse generated by the pulse source of
and a second measuring means for measuring the period T1 of the first pulse generated by the first pulse source described above, when the measured value when counting with the reference pulse described above is N1, the measured value When N1 is less than or equal to the minimum value N1s determined in correspondence with the first permissible change range of the oscillation frequency in the voltage controlled oscillator, the first signal is generated, and the measured value N
means for generating a second signal when 1 is equal to or greater than a maximum value N1l determined corresponding to the first permissible variation range of the oscillation frequency; and a second signal generated by the second pulse source described above; The frequency change rate in the first allowable change range set for the oscillation frequency of the voltage controlled oscillator is given by N2, which is the measured value when the period T2 of the second pulse is counted using the reference pulse described above. The third signal is transmitted when the measured value N2 is smaller than the minimum value N2s determined corresponding to the second allowable change range of the oscillation frequency, which is set to have a large frequency change rate compared to the second allowable change range of the oscillation frequency. and means for generating a fourth signal when the measured value N2 is equal to or greater than a maximum value N2l determined corresponding to a second permissible change range of the oscillation frequency in the voltage controlled oscillator; means for obtaining a first error signal from the first signal and the third signal;
means for obtaining a second error signal using the signal and the fourth signal; means for controlling the error signal of the phase comparator circuit in the phase locked loop according to each of the error signals; A digital signal demodulator comprising a bit clock signal generator comprising means for selectively invalidating either or both of the first signal and the second signal.