JPH0324102B2 - - Google Patents

Abstract

PURPOSE:To obtain simultaneously an optimum output vector and an amplitude factor without approximation by a simple arithmetic by applying inner product operation in the form of product sum after an inter-block means value is separated in a mean value separation circuit so as to detect a maximum value. CONSTITUTION:The mean value separation circuit 12 applies the arithmetic of equation to an inter-frame difference vector 113 being an input signal to obtain an input vector X*115. The set of an output vector yi optimized by using the normalized vector subjected to mean value separation and normalization is written in a code book ROM 16 by a conventional method. The inner product between the output vector 116 and the input vector X*115 is obtained by an inner product operation circuit 14 and a maximum inner product among obtained N sets is detected by a maximum inner product detection circuit 15. Simultaneously, the maximum inner product is outputted to a movement detection circuit 13 as an amplitude factor sigma*.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides an inter-frame adaptive vector that performs high-efficiency encoding of an image signal using a vector quantization method by utilizing the correlation between consecutive screens. The present invention relates to a quantization encoding device. [Prior Art] FIG. 2 is a block diagram showing an example of the configuration of an encoding section of a conventional interframe adaptive vector quantization device. In the figure, 1 is an A/D converter, and 2 is an A/D converter.
A raster 1-block scanning conversion circuit converts the converted raster-format digital image signal into blocks of m pixels x n lines (m and n are integers), and 3 converts the block data into high-efficiency codes by vector quantization. A vector quantization encoder 4 stores highly efficiently encoded data and sends it out to the transmission path at a constant speed. motion detection control circuit for controlling motion detection threshold in the encoder, 6
A vector quantization decoder decodes encoded data supplied from the vector quantization encoder and reproduces block data, 7 is a variable delay circuit, and 8 is a frame memory. Further, FIG. 3 is a block diagram showing an example of the configuration of a decoding section of a conventional interframe adaptive vector quantization encoding device. A receiving data buffer outputs encoded data at a speed corresponding to the operation; 10 is a block/raster scanning conversion circuit that converts decoded and reproduced block data into raster format data; and 11 is a D/A converter. Next, the encoding/decoding operation will be explained using FIGS. 2 and 3. The input image signal 10 is an analog signal that is raster scanned from left to right and from top to bottom of the screen. This raster format analog signal is A/D
After being converted into a digital signal 10 by the converter 1, the raster format digital signal is converted into a block by m pixels x n lines (m and n are integers) in the raster/block scanning conversion circuit 2, and further the pixel samples within the block are Vector data S103 is obtained by arranging them in a one-dimensional array. Previous frame vector data P 1 based on the vector data S 103 and blocks at the same position in the frame memory 8
04 is the inter-frame difference vector ε 1
05 to the vector quantization encoder 3. The vector quantization encoder 3 performs mean value separation normalization processing on the interframe difference vector ε 105, and performs motion estimation using the obtained mean value, amplitude coefficient, and threshold value 106. After vector quantizing only the vectors of effective blocks based on motion, the valid/invalid block information, average value, amplitude coefficient, and vector quantization index information are each encoded using variable length encoding, etc., and encoded data 107 is generated. Output. Transmission data buffer 4
stores encoded data 107 and sends it out to the transmission path at a constant speed according to a predetermined transmission speed, calculates the amount of accumulated data 108, and supplies it to the motion detection control circuit 5. The motion detection control circuit 5 controls a motion detection threshold 106 in accordance with an increase or decrease in the data storage amount 108. Further, the encoded data output from the vector quantization encoder 3 is decoded by the vector quantization decoder 6 according to the inverse encoding process, and an inter-frame difference reproduction vector ε^ 109 is reproduced. The obtained inter-frame difference reproduction vector ε^ 109,
Adding the previous frame vector data P104 delayed by a predetermined time by the variable delay circuit 7,
The reproduced vector data S110 is restored and the block data at the corresponding position in the frame memory is updated.
The above process is shown in the following equation. ε = S − P ε^ = ε +〓^ (〓^ represents the calculation error in vector quantization encoding) S^ = P + ε^ P = S^・Z ^-f (Z ^-f is one frame delay On the other hand, the encoded data 107 received and speed-converted by the reception data buffer 9 is decoded by the vector quantization decoder 6, and an inter-frame difference reproduction vector ε 109 is reproduced. The inter-frame difference reproduced vector ε 109 and the previous frame vector data P 104 passed through the variable delay circuit 7 are added together to restore the generated vector data S 110 in the same manner as the processing of the encoder. That is, S^ =P+ ε^ =S+〓^ is executed as a vector operation. The reproduced vector data S 110 is converted into raster format data 111 in the block/raster scan conversion circuit 10, and D/A converted by the D/A converter 11 to obtain an analog reproduced image signal 112. Next, the configuration and operation of the vector quantization encoder and vector quantization decoder will be explained in detail. FIG. 5 shows an example of the configuration of a conventional vector quantization encoder. In the figure, 19 is an average value separation normalization circuit, 13 is a motion detection circuit, 23 is a distortion calculation circuit,
20 is the minimum distortion detection circuit, 16 is the code rack
ROM, 17 is an address counter, and 18 is an index latch. The operation of the vector quantization encoder will be explained. Inter-frame difference vector ε 11 which is the input signal
3, the following calculations are performed in the mean value separation and normalization circuit 19 to convert it into a normalized vector x . That is, ε = [ε ₁ , ε ₂ , ..., ε _K ] (k = m×
Let m be the intra-block average value of n) and σ be the amplitude coefficient, then m=1/k _k 〓 ^j=1 εj (j=1, 2,...,k) σ=[ _k 〓 ^j=1 (εj− m) ² ] ^1/2 As an approximate expression for σ, σ= _k 〓 ^j=1 |εj−m|, σ=max _j εj−min _j εj, etc. can also be used. xj = (εj - m)/σ x = [x ₁ , x ₂ , ..., xk] where average value m, amplitude coefficient σ, and normalized vector x
get. Obtained average value m114 and amplitude coefficient σ11
8 is input to the motion detection circuit 13, and the threshold value T ₀ ,
By comparison with T ₁ 106, valid/invalid block determination, ie, motion detection processing, is performed according to the following conditions, and block identification information ν121 is output. {m<T ₀ and σ<T ₁ ; ν=0 (invalid block) {m>T ₀ or σ>T ₁ ; ν=1 (valid block) Block identification information ν is transmitted for each block. The following processing is performed only when ν is 1. The normalized vector x 122 is sent to the distortion calculation circuit 14 and subjected to the following vector quantization process. First, a set of a plurality of output vectors yi 116 (i=1, 2, . . . , N) generated using a clustering method based on the statistical properties of the normalized vector x is written into the codebook ROM 16. At the time when the normalized vector x 115 is input to the distortion calculation circuit 14, the address counter 17 is
1 , 2, _.
Read out in the order of y ₂ , ..., y _N. Next , the distortion calculation circuit 23 sequentially calculates distortions d( x , y ₁ ) 117 between the normalized vector x and the N output vectors yi that are sequentially read out. The distortion calculation is performed according to the following equation. d( x , yi )=[ _k 〓 ^j=1 (xj− yi j) ² ] ^1/2 (j=1, 2,...k) or as an approximate expression d( x , yi )= _k 〓 ^j=1 |xj− yi j| d( x , yi )=max _j |xj−yij| can also be used. The minimum distortion detection circuit 20 detects the minimum distortion among the N distortions obtained by the above calculation, and at that time detects the codebook indicated by the address counter.
Output vector address information i in the ROM is taken in by the index latch 18 and sent out as an output vector index i120. Intra-block average value m11 obtained in the above process
4, amplitude coefficient 122, block identification information ν12
1. The output vector index i 120 is converted into an appropriate code word as vector quantization encoded information 107 and output. At this time, if ν is 0, no code word of other information is output. Next, the vector quantization decoder shown in FIG. 4 will be explained. In the figure, 21 is an amplitude coefficient multiplier, and 22 is an average value adder. Of the vector quantization encoded information 107 sent from the reception data buffer 9, the block identification information ν121 is first decoded. When ν is 1, that is, a valid block, the decoded output vector index i 120 is applied to the index latch 19.
be taken in. Then, the output vector yi 119 at the address indicated by the index i 120 is read out from the codebook ROM 20 in which the same contents as the codebook ROM of the vector quantization encoder are written. This output vector
By multiplying yi by an amplitude coefficient σ118 in an amplitude coefficient multiplier 21 and adding an average value m114 in an average value adder 22, an inter-frame difference reproduction vector ε 109 is decoded. That is, the following process is executed. ε = [ε ₁ , ε ₂ , ..., εk] εj = σ・yij + m (j = 1, 2, ..., k) At this time, for ν = 0, that is, for an invalid block, m = 0, σ = 0 ε is decoded and reproduced as ε. ε^ = [0, 0,..., 0] [Problem to be solved by the invention] Since the conventional inter-frame adaptive vector quantization coding device is configured as described above, σ for normalization It is necessary to perform the calculation of the sum of squares (Σ(ab) ² ) many times in the calculation and the vector quantization distortion calculation, which increases the circuit scale of the device. Furthermore, when these calculations are performed using approximate expressions, there are problems such as deterioration of image quality due to calculation errors. This invention was made to solve the above-mentioned problems, and the calculation of σ for normalization and the vector quantization distortion calculation are performed in one product-sum calculation circuit (Σ,
It is an object of the present invention to provide an inter-frame adaptive vector quantization coding device that can perform the processing using only the ab) and improve image quality deterioration caused by approximation calculation errors since it does not use approximation formulas. [Means for Solving the Problems] The inter-frame adaptive vector quantization coding device according to the present invention includes an average value separation circuit that separates intra-block average values, a product-sum calculation circuit that performs distortion calculations, and a minimum distortion detection circuit. The calculation is simplified by providing a minimum distortion detection circuit that simultaneously determines the output vector and amplitude coefficient that result in the minimum distortion. [Operation] After the intra-block average values are separated in the average value separation circuit, the inner product calculation is performed in the form of a sum of products, and the maximum value thereof is detected, thereby obtaining the optimum output vector and the amplitude coefficient at the same time. [Embodiment of the Invention] FIG. 1 is a block diagram of a vector quantization encoder showing an embodiment of the present invention. 13,1
6, 17, and 18 are exactly the same as the conventional ones. Further, the configuration of the interframe adaptive vector quantization encoding/decoding device and the configuration of the vector quantization decoder for achieving the effects of the present invention may be the same as those of the conventional ones. In FIG. 1, numeral 12 is an average value separation circuit that calculates the intra-block average value of the inter-frame difference vector and separates the average value, and 14 is an inner product of the average value-separated input vector and the output vector read from the codebook ROM. The inner product calculation circuit 15 detects the optimal output vector by finding the maximum value of the inner product between input and output vectors obtained for a plurality of output vectors, and determines the amplitude coefficient during vector quantization and decoding. A maximum inner product calculation circuit 13 is a motion detection circuit that performs motion detection using the obtained average value, amplitude coefficient, and threshold value and outputs valid and invalid block identification information. Next, the operation will be explained. The inter-frame difference vector ε 113, which is an input signal, is subjected to the following calculations by the average value separation circuit 12 and converted into an input vector x ^* . If the intra-block average value of ε = [ε ₁ , ε ₂ ,..., εk] is m, then m=1/k _k 〓 ^j=1 εj (j=1, 2,..., k) x ^* j= Execute εj−m x ^* = [x ^* ₁ , x ^* ₂ , ..., x ^* k] to obtain the average value m and the input vector x ^* . Output vector yi 1 optimized by clustering etc. using the obtained input vector x ^* and the normalized vector normalized by mean value separation using the conventional method
Inner product calculation circuit 14 calculates the inner product with the output vector in codebook ROM 16 in which the set of 16 (i=1, 2, . . . , N) is written.
The inner product F(x, yi) is obtained according to the following equation. F( x , yi )= _k 〓 ^j=1 (xj, yij) (j=1, 2,...,k) Among the N inner products obtained, the maximum inner product is detected by the maximum inner product detection circuit 15. At the same time, the motion detection circuit 1 uses the maximum inner product at that time as the amplitude coefficient σ ^* .
Output to 3. Here, when the output vector index giving the maximum inner product is 0 and the input/output vector is a two-dimensional vector (k = 2), y ₀ becomes the optimal output vector and the maximum inner product can be obtained as the amplitude coefficient. This will be explained using figures. First, since y i has been normalized by mean value separation, | y i |=1. Then, when the angle between x and y i is θ, F ( x , y i) = _k 〓 ^j=1 xj・yij = | x | | y i | cosθ | x |
Since it is expressed as cos θ, when θ=0, x and y i become vectors in the same direction, and the distance within the two-dimensional plane becomes the minimum. Since the condition for cosθ is -1cos1, when θ=0, cosθ=1 and F( x , y
i) takes the maximum value. Therefore (F( x , yi )
The optimal output vector is y ₀ for which y is the maximum. Further, since F( x , y ₀ )=|x|| y ₀ |cosθ=σ ^* |y ₀ |=σ ^* , maxF( x , y ₀ ) can be used as the amplitude coefficient σ ^* . The obtained amplitude coefficient σ ^* is calculated by the motion detection circuit in the vector quantization encoder as in the conventional method,
Used in the amplitude coefficient multiplier in the vector quantization decoder. In addition, in the above embodiment, a case is shown in which a full search method is used in which the inner product between input and output vectors is found for all N items in the inner product calculation circuit and the maximum one is detected. However, the output vectors may be arranged in a tree structure. Then, we use a tree search method that calculates the inner product with the two output vectors at each branch and selects the larger vector of the two inner products from the upper layer to the lower layer. Good too. [Effects of the Invention] As described above, according to the present invention, after the average value within a block is separated in the average value separation circuit, the inner product operation is performed in the form of sum of products, and the maximum value is detected to obtain the optimal output vector. Since the structure is configured to calculate the amplitude coefficient and amplitude coefficient simultaneously, calculations can be simplified and the circuit scale of the device can be reduced.Also, since there is no need to use an approximation formula for inner product calculation, the accuracy of motion detection and optimal output vector detection can be improved. get high,
This has the effect of improving playback image quality.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a vector quantization encoder according to an embodiment of the present invention, and FIG. 2 is an encoding section of an embodiment of the present invention or a conventional interframe adaptive vector quantization encoder. FIG. 3 is a block diagram showing the configuration of a decoding section of an embodiment of the present invention or a conventional interframe adaptive vector quantization coding device, and FIG. 4 is an embodiment of the present invention. 5 is a block diagram showing the configuration of a conventional vector quantization encoder, and FIG. 6 is a vector quantization code according to an embodiment of the present invention. FIG. 2 is an explanatory diagram for explaining the operation of the converter. In the figure, 1 is an A/D converter, 2 is a raster/block scan conversion circuit, 3 is a vector quantization encoder, 4 is a transmission data buffer, 5 is a motion detection control circuit, 6 is a vector quantization decoder, 7 is a variable delay circuit, 8 is a frame memory, 9 is a received data buffer, 10 is a raster/block scan conversion circuit, 11 is a D/A converter, 12 is an average value separation circuit, 13 is a motion detection circuit, and 14 is an inner product calculation. circuit,
15 is the maximum inner product detection circuit, 16 is the codebook
ROM, 17 is an address counter, 18 is an index latch, 19 is an average value separation normalization circuit, 2
0 is the minimum distortion detection circuit, 21 is the amplitude coefficient multiplier, 2
2 is an average value adder, and 23 is a distortion calculation circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A frame memory that always stores at least one frame of image signals, and when the latest image signal sequence obtained by grouping the input signal sequence into K blocks (K is an integer) is input. a subtracter that reads from the frame memory a predicted signal sequence that has been turned into a block at a position corresponding to the same position as the block on a screen at least one frame before, and calculates an interframe difference signal sequence; and the interframe difference signal. A mean value separation circuit calculates the intra-block average value of a series and converts it into an input vector by performing mean value separation, and a A vector that encodes an input vector into the identification code of the output vector that has the maximum sum of the products of each element of the input and output vectors, that is, the inner product, from among a plurality of output vector sets optimized by a clustering method in a dimensional space, etc. A process in which a block in which the amplitude coefficient, which is the sum of the products, and the intra-block average value are equal to or less than a predetermined threshold value is regarded as an invalid block, and all pixel values in the block of the inter-frame difference signal sequence are set to zero. A motion detection circuit that executes a motion detection circuit selects a corresponding output vector from the output vector identification code for valid blocks other than the invalid block, multiplies it by the amplitude coefficient, and adds the average value, thereby generating an inter-frame difference signal. a vector quantization decoding unit that reproduces the sequence and makes the interframe difference signal sequence zero for the invalid block, and adds the interframe difference signal sequence reproduced after the vector quantization and the predicted signal sequence. an adder for reproducing the image signal and writing it into the frame memory; and variable length encoding of the valid/invalid block identification code, output vector identification code, block average value, and amplitude coefficient while keeping the amount of information generated constant. An inter-frame adaptive vector quantization and encoding device, comprising a transmission data buffer for controlling the threshold value. 2 In the vector quantization encoding section, in searching for the output vector that maximizes the sum of the products of each element of the input and output vectors, the output vector set is arranged in a tree structure, and the two output vectors and the input vector at each branch are Claims characterized in that a tree search method is used in which the sum of the products of each element is calculated, and the vector with the larger sum of the products is sequentially selected from the upper layer to the lower layer of the tree structure. 1st
The inter-frame adaptive vector quantization encoding device as described in 2.