JPH03244282A - video superimposition device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a video superimport device for displaying moving images on a CRT of a computer.

(Prior Art) Computers are used for various calculations, controls, information processing, etc. Therefore, conventional computer CRTs display still images of human output data, charts, various messages, etc. for calculations. It was the Lord.

(Invention or problem to be solved) By the way, when trying to display a moving image on the above CRT,
It was necessary to develop a dedicated graphics board and use it. For this reason, photo development could not be easily carried out unless the internal interface and display method of the relevant computer system were made public. In addition, the developed board can only be used for the relevant model, and if you want to make other models perform the same operation and display moving images on a CRT, it is necessary to develop another board.

The present invention has been made in view of the above points, and its purpose is to realize a video superimpose device that can display a moving image superimposed on a still image on a computer CRT without using a dedicated board. It is in.

(Means for Solving the Problems) The present invention solves the above problems by using a red signal processing system green having the same configuration that processes the three primary color signals of the video input signal and switches between the green and three primary color signals of the still image input signal. It is composed of circuits for a signal processing system and a blue signal processing system, and a control system that controls the operation of the processing system, and each signal processing system includes an AD converter that converts an analog video input signal into a digital signal, and an AD converter that converts an analog video input signal into a digital signal. Each system has at least two outputs written alternately.
a first switch that is switched to alternately write the output of the AD converter to the memory; and a first switch that is switched to alternately read data stored in the memory. 2 switch, a DA converter that reads the data stored in the memory and converts it into an analog signal, and the analog signal from each DA converter is input to the A terminal, and the still image signal from the computer graphics board is input. A multiplexer that is input to the B terminal and outputs the moving image signal and the still image signal by switching in order to display them at necessary times, and a synchronization signal in the moving image signal as the control system, The timing of switching the second switch and the timing of writing to the memory are determined, the timing of switching the second switch is determined by the synchronization signal in the video signal and the synchronization signal in the still image signal, and the timing of reading the memory is determined. and controlling switching timing of the multiplexer.
The present invention is characterized in that it includes two timing generation circuits.

(Function) The three color signals of the image signals are each converted into digital signals by an AD converter and then written into a memory selected by a switch. Data read from the memory on the side to which writing is not currently being performed is converted into an analog signal by the DA converter and input to the multiplexer. The multiplexer selectively outputs a still image signal and a moving image signal under the control of the timing generation circuit, and displays a moving image among the still images as necessary.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, ADI is an AD converter that receives the red signal Rv of the video input color signal and converts it into a digital signal, and AD2 is an AD converter that also receives the video input green signal Gv and converts it into a digital signal. , AD3 is an AD converter which receives the blue signal Bv of the video input and converts it into a digital signal. 5WO1 is AD converter ADI
5W02 switch for writing the red signal output Rv from the memory to either memory MIO or memory Mll
Similarly, 5WO3 is a switch for writing the green signal Gv into either memory M20 or memory M21, and 5WO3 is a switch for writing green signal Bv into either memory M30 or M31. Memory M10.

Memory M20. M21 and memory M30. M31 is M*0. M*1. M*0... FIFO (First
In First Out) memory. SWI 1 switches between the red light data stored in memory M10 and memory Mll and outputs it to DA converter D.
Switch for input to AI, 5W12 is memory M2
0 and a switch for switching and inputting the green signal stored in the memory M21 to the DA converter DA2, SWI 3
is a switch for switching and inputting the blue signal stored in the memory M30 and the memory M31 to the DA converter DA3. MPX1, MPX2. MPX3 is each DA
Converter DA1, DA converter DA2. The output of the DA converter DA3 is input to the A terminal, and the red signal R6゜green signal GC1 blue signal B of the output of the computer graphic board
C is a multiplexer whose B terminal is input, and its outputs are sent to the CRT as three electric signals R8, Go, and Bo, respectively. Therefore, AD converter AD1, switch 5WO
1, memory M10, switch SWI 1, DA converter D
A red light processing system is configured with AI and multiplexer MPXI, AD converter AD2, switch 5WO2, memory M2
0. M21, switch 5WI2, DA converter DA2 and multiplexer MPX2 constitute a green signal processing system, and AD
Converter AD3, switch 5WO3, memory M30. M3
1, a switch 5W1B, a DA converter DA3, and a multiplexer MPX3 constitute a green signal processing system. TMG
The synchronization signal S Y N Cv is input from the video input,
Synchronous signal 5YNC from computer graphics board
c is input, and a control signal for switching the switches 5WO1 to 5WO3 and the switches SW11 to 5WI3;
Generation of operation timing for each memory and multiplexer M
This is a timing generation circuit that outputs control signals for the operations of PXI to MPX3.

Next, the operation of the embodiment configured as described above will be explained with reference to the time chart of FIG. In the figure, (a)
(b) shows the operation of memory M*0, and (c) shows the operation of memory M*1. The memory is a FIFO in which data can be written and read in the order of M*Q, M*1, M*0, and so on. Therefore, a write request is generated to the memory every time the video frames FO, F1, . . . are updated. At this time, if the memory that is in the order to be written to is not busy, the data will be written to the memory. In the figure, switches 5WO1, 5WO2, SW
O3 is on the M*O side, and frame FO is on the memory M
*Written to 0. When writing is finished, switch S
WO1 to 5WO3 enter the memory M*1 side and are stored in frame F.
1 is written to memory M*1. During this time, SWI
1 to 5W13 enter the memory M*0 side, and the video of the previously written frame FD is transferred to the D via switch SW*1.
It is read out to A converters DAI to DA3. Therefore, frame FO is output as the output frame (d).

When frame F2 is input, switch 5WO1~0
3 is in the memory M*1 to M*3 side, and the memory M*
Since frame F1 has been written in frames 1 to M*3, frame F2 is not taken into memory M*0°M*1. Next, frame F3 is input, and switch 5W0
1 to 5 WO3 enter the M*0 side and frame F3 is written to the memory M*0. Frame F1 is in memory M*1
is written and read out to DAI-DA3 via switches SW11-3W13, and frame F1 is output. When only reading from memory M*1 is completed, memory M*0
Since writing is being performed on , switches 5W11~
5W13 is stored in the memory M*1 side as it is, and reading of the frame F1 continues, and the frame F1 is continuously outputted as it is. In this way, memory M
*0 to frame FO, F3. F7 is written, and frames F1, F5 . F9 is written.

The output frame is M*0. M*1. In principle, they are read in the order in which they were written, such as M*O, but if the memory to be read next is capturing a video frame, the previous display screen is sent to the output frame again. In this way, within the video frame,
Although some images do not appear in the output frame, moving images that maintain their temporal order appear in the output frame as shown in FIG. 2. This degree of frame skipping poses no problem when observed by the human eye.

Multiplexer F, IPX1 to MPX3 has the first
As shown in the figure, an output frame of a moving image is input to the A terminal, and an image signal from a computer graphics board is input to the B terminal, and this image signal is switched and output. Figure 3 shows image display and multiplexer MP
FIG. 3 is a diagram showing the relationship between the operations of XI to MPX3. Figure (A) is a diagram of the display screen 1, and Figure (B) is a diagram of the operation timing of the multiplexer. (b) When displaying an image from a computer in area C in the figure and a video in area (■), (
b) As shown in the figure, when displaying an image from a computer in area C, use multiplexers MPXI to MP.
A signal to switch to the B terminal on the output side from the computer graphics board is input to X3, and when displaying a video in the ■ area, multiplexers MPXI to MPX3
A switching signal is input to the A terminal on the output side of the DA converters DAI to DA3. Above switch SWO1~5W
03, memory M*0-M*1. Switch SW1]~S
WI 3. The operations of the multiplexers MPXI to MPX3 are controlled by a timing generation circuit TMG to which a synchronization signal S Y N Cv from the video input and a synchronization signal 5YNCc from the computer graphics board are input.

Note that the present invention is not limited to the above embodiments. FIG. 4 is a block diagram of another embodiment.

In the figure, parts equivalent to those in FIG. 1 are given the same reference numerals. In the figure, TMG1, TM01, and 7MG3 are timing generation circuits that are connected to three types of computers from different manufacturers, respectively, and the timing generation circuits TMG1, TM01, and 7MG3 are switched by the connected computers by a signal from the timing generation circuit select. . The operation is performed by switching the timing generation circuits TMG1 to TMG3 for each connected computer.

Other operations are the same as those in the embodiment shown in FIG. 1, so explanations will be omitted.

In the embodiments shown in FIGS. 1 and 4, two memories are used for each signal, but three or more memories may be provided so that no video input is missed.

An interface circuit with a computer may be added to turn on/off the video display (the position of the window can also be changed).

As explained above, according to the device of this embodiment, a window is provided on the CRT to display a moving image without using the internal bus of the computer, so once the specifications of the CRT's synchronization signal are known, the timing generation circuit can be installed. By making changes accordingly, a video superimposing device can be realized. Further, in the embodiment shown in FIG. 4, one video superimposing device can support a plurality of computers.

(Effects of the Invention) As described in detail above, according to the present invention, it becomes possible to display a moving image on a computer CRT without using a dedicated board, and the practical effects are great.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a time chart of the operation of the embodiment, Fig. 3 is a diagram of the operational relationship between image display and multiplexer, and Fig. 4 is another embodiment of the invention. FIG. AD1, AD2. AD3...AD converter M10, M2
0, M21. M20, M31... Memories DA1, DA2. DA3...DA converter MPX1. M
PX2. MPX3...Multiplexer 5WO1, 5WO2, SWO3, SWI1, 5
W12, SW13...Switch TMG, TMG1, TMG2. TMG3...timing generation circuit

Claims (1)

[Claims] The three primary color signals of the video input signal are processed, and the three primary color signals of the still image input signal are processed.
A red signal processing system with the same configuration that switches between the primary color signal and
It is composed of circuits for a green signal processing system and a blue signal processing system, and a control system that controls the operation of the processing system. Each signal processing system includes an AD converter (AD1, AD2) that converts an analog video input signal into a digital signal. , AD3) and at least two FIFOs in each system, into which the outputs of the AD converters (AD1, AD2, AD3) are alternately written.
Configuration memory (M10, M11; M20, M21; M3
0, M31) and the output of the AD converter (AD1, AD2, AD3) to the memory (M10, M11; M20, M21; M30,
first switches (SW01, SW02, SW03) that are switched to alternately write data into the memories (M10, M11; M20, M21; M30);
, M31) which are switched to alternately read data stored in the memory cells (SW11, SW12,
SW13) and the memory (M10, M11; M20, M21; M30
, M31) and converts it into an analog signal.
), the analog signal from each DA converter (DA1, DA2, DA3) is input to the A terminal, the still image signal from the computer graphics board is input to the B terminal, and the moving image signal and the still image signal are input. Multiplexer (MPX1, MP
X2, MPX3), and the first switches (SW01, SW02, SW02,
SW03) switching timing and memory (M10
, M11; M20, M21; M30, M31), and the switching of the second switches (SW11, SW12, SW13) is determined by the synchronization signal in the video signal and the synchronization signal in the still image signal. The timing is determined and the memory (M10, M11; M20, M
21; M30, M31), and determine the read timing of the multiplexers (MPX1, MPX2,
A video superimposing apparatus comprising at least one timing generation circuit (TMG) for controlling switching timing of an MPX (MPX3).