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JPH0324817B2 - - Google Patents
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JPH0324817B2 - - Google Patents

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Publication number
JPH0324817B2
JPH0324817B2 JP58030769A JP3076983A JPH0324817B2 JP H0324817 B2 JPH0324817 B2 JP H0324817B2 JP 58030769 A JP58030769 A JP 58030769A JP 3076983 A JP3076983 A JP 3076983A JP H0324817 B2 JPH0324817 B2 JP H0324817B2
Authority
JP
Japan
Prior art keywords
gate
thyristor
resistor
transistor
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58030769A
Other languages
Japanese (ja)
Other versions
JPS59158127A (en
Inventor
Katsuji Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Electric Manufacturing Ltd
Original Assignee
Toyo Electric Manufacturing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Electric Manufacturing Ltd filed Critical Toyo Electric Manufacturing Ltd
Priority to JP58030769A priority Critical patent/JPS59158127A/en
Publication of JPS59158127A publication Critical patent/JPS59158127A/en
Publication of JPH0324817B2 publication Critical patent/JPH0324817B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
    • H03K17/73Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region for DC voltages or currents
    • H03K17/732Measures for enabling turn-off

Landscapes

  • Protection Of Static Devices (AREA)
  • Power Conversion In General (AREA)
  • Thyristor Switches And Gates (AREA)

Description

【発明の詳細な説明】 本発明はゲート電流によつてオン、オフ動作す
るゲートターンオフサイリスタのゲート駆動回路
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate drive circuit for a gate turn-off thyristor that is turned on and off by gate current.

ゲートターンオフサイリスタ(以下GTOと略
称する)は自己消弧能力が有り、機能的に優れた
電力用半導体素子である。しかし、サイリスタに
比較しターンオンゲインは低く、ターンオン時に
はオーバードライブが必要となる。また保持電流
が大きく、オン期間中、サイリスタに比較しかな
り大きなゲート電流を流さなければならない。さ
らにターンオフ時には、ゲートに非常に大きなオ
フ電流を流さねばならず、1000Aの主電流をしや
断するには200A以上のオフ電流となる。このた
め、ゲート回路が複雑で、かなり高価になる傾向
がある。これは電車用インバータのように主回路
電圧が高く、半導体素子数が多い用途において
は、ゲート制御回路との絶縁の問題もあり顕著と
なる。
A gate turn-off thyristor (hereinafter abbreviated as GTO) has a self-extinguishing ability and is a highly functional power semiconductor device. However, the turn-on gain is lower than that of a thyristor, and overdrive is required when turning on. In addition, the holding current is large, and during the on period, a considerably larger gate current must flow than in a thyristor. Furthermore, at turn-off, a very large off-state current must flow through the gate, resulting in an off-state current of over 200A to cut off the main current of 1000A. As a result, gate circuits tend to be complex and quite expensive. This becomes noticeable in applications where the main circuit voltage is high and the number of semiconductor elements is large, such as inverters for trains, due to the problem of insulation from the gate control circuit.

第1図は従来のGTOのゲート駆動回路例を示
す図で、第2図はその動作説明図である。第1図
においてPは直流電源正極端子、Nは直流電源負
極端子、TONはオン用トランジスタ、SONはオ
ン/オフ干渉防止用サイリスタ、R1,R2は抵抗、
PTONはオン用絶縁パルストランス(以下オン用
ゲートトランスと称す)で、幅狭のオンゲート回
路を構成する。
FIG. 1 is a diagram showing an example of a conventional GTO gate drive circuit, and FIG. 2 is an explanatory diagram of its operation. In Figure 1, P is the positive terminal of the DC power supply, N is the negative terminal of the DC power supply, T ON is a transistor for ON, S ON is a thyristor for preventing ON/OFF interference, R 1 and R 2 are resistors,
PT ON is an insulating pulse transformer for ON (hereinafter referred to as ON gate transformer), which constitutes a narrow ON gate circuit.

TOFFはオフ用トランジスタ、DFはオンゲート
電流のオフ回路への流を阻止するダイオード、
PTOFFはオフ用絶縁パルストランス(以下オフ用
ゲートトランスと称す)で、オフ回路を構成す
る。
T OFF is an OFF transistor, D F is a diode that blocks the on-gate current from flowing to the OFF circuit,
PT OFF is an insulating pulse transformer for OFF (hereinafter referred to as OFF gate transformer), which constitutes an OFF circuit.

TW1,TW2は高周波で交互にオン、オフする幅
広ゲートパルス発生用トランジスタ、PTWは幅
広用絶縁パルストランス(以下幅広用ゲートトラ
ンスと称す)、DW1,DW2はこの幅広用ゲートトラ
ンスPTWの2次電圧を全波整流するためのダイオ
ード、R3は抵抗で、幅広オンゲート回路を構成
する。
T W1 and T W2 are transistors for generating wide gate pulses that are turned on and off alternately at high frequencies, PT W is a wide insulating pulse transformer (hereinafter referred to as wide gate transformer), and D W1 and D W2 are wide gate transformers. P TW is a diode for full-wave rectification of the secondary voltage, and R 3 is a resistor, forming a wide on-gate circuit.

各々のトランジスタの制御信号は第2図a〜c
に示すように与えられ、GTOのゲート電流は第
2図dに示すように時間t1でオーバードライブ電
流が流れ始め、時間t2でオーバードライブ電流が
なくなり、幅広ゲート電流として図示のように高
周波を全波整流した電流となる。さらに時間t3
オフゲート電流が流れGTOをターンオフさせ、
時間t4でオフ電流が零となる。
The control signals for each transistor are shown in Figure 2 a to c.
The gate current of the GTO is given as shown in Fig. 2d, and the overdrive current starts to flow at time t 1 , the overdrive current stops flowing at time t 2 , and the gate current starts flowing at high frequency as shown in the figure as a wide gate current. The current is full-wave rectified. Furthermore, at time t3 , an off-gate current flows and turns off the GTO,
The off-state current becomes zero at time t4 .

この従来例では制御信号が3種類必要となり、
回路が非常に複雑となる。さらに具合が悪いの
は、第1図に示すようにオフ回路電流として実線
に示すGTOカソードからゲートに流れるオフ電
流の外に、点線で示すように幅広オンゲート回路
にも分流する。特にGTOの主電流がしや断され
カソード、ゲート間に電圧を持つようになると、
第1図の点線のみの電流となる。この電流は、抵
抗R3がサイリスタの場合に比較しかなり低抵抗
(幅広オン電流として2〜3A以上必要とするのが
普通である)であるため、無視できない値とな
る。この電流はオフ電流の利用率が低下するばか
りではなく、オフゲートパルスが消滅する時に、
幅広オンゲート回路に流れる電流も消滅しようと
するが、幅広用ゲートトランスPTWの巻線のイ
ンダクタンスおよび回路の配線インダクタンスに
より継続して第1図点線に示す電流を流そうとす
る。
This conventional example requires three types of control signals,
The circuit becomes very complex. What is even worse is that, as shown in Figure 1, in addition to the off-circuit current that flows from the GTO cathode to the gate, shown by the solid line, it also flows into the wide on-gate circuit, as shown by the dotted line. Especially when the main current of the GTO is suddenly cut off and there is a voltage between the cathode and gate,
The current is only shown by the dotted line in FIG. This current is a value that cannot be ignored because the resistance is considerably lower than that in the case where the resistor R 3 is a thyristor (usually 2 to 3 A or more is required as a wide on-current). This current not only reduces the off-current utilization rate, but also when the off-gate pulse disappears,
The current flowing through the wide on-gate circuit also tends to disappear, but the current shown by the dotted line in Figure 1 continues to flow due to the inductance of the winding of the wide gate transformer PT W and the wiring inductance of the circuit.

一方、オフ用ゲートトランスPTOFFはオフ用ト
ランジスタTOFFのしや断により逆誘起電圧を発生
し、2次巻線電流を阻止するように動作する。こ
のため上述した幅広オンゲート回路の電流は、第
2図dのゲート電流波形に時間t4で点線で示すよ
うにGTOのゲート、カソードに流れ、GTOをタ
ーンオンするおそれがある。
On the other hand, the OFF gate transformer PT OFF generates a reverse induced voltage by cutting off the OFF transistor T OFF , and operates to block the secondary winding current. Therefore, the current in the wide on-gate circuit described above flows to the gate and cathode of the GTO, as shown by the dotted line at time t4 in the gate current waveform of FIG. 2d, and may turn on the GTO.

したがつて幅広オンゲート回路に必ずスイツチ
素子が必要となり、このスイツチ素子を制御する
絶縁された制御信号を発生する回路を併せて考え
ると非常に複雑な回路となる。
Therefore, a switch element is always required in a wide on-gate circuit, and when a circuit for generating an isolated control signal for controlling this switch element is also considered, the circuit becomes extremely complicated.

さらに幅広オンゲート信号として第2図dのゲ
ート電流に示すように、高周波を全波しているこ
とに起因するゲート電流の不連続が必ず発生し、
GTOの動作に極めて悪い影響を与える。
Furthermore, as shown in the gate current in Figure 2d, as a wide on-gate signal, discontinuity in the gate current due to the full high frequency is always generated.
This has a very negative effect on the operation of GTO.

本発明は上述したような従来の欠点に鑑みなさ
れたもので、以下本発明を実施例図面にもとづい
て説明する。第3図は本発明の一実施例を示す
GTOのゲート駆動回路図で、第1図と同一機能
をするものについては同一符号を付して示してあ
る。Eは幅広オンゲート電源で、これは絶縁され
た直流電源であればどのようなものでもよい(以
下直流電源Eという)。SWは幅広オンゲート電流
をオン・オフする制御用サイリスタ、R4は制御
用サイリスタSWのゲート電流を制限する抵抗、
SOFFは制御用サイリスタSWをオフするためのSW
オフ用トランジスタ、R5はこのスイツチ素子
(SOFF)をオン・オフする電流を制限する抵抗で
ある。
The present invention has been made in view of the above-mentioned drawbacks of the conventional art, and the present invention will be explained below based on the drawings of the embodiments. FIG. 3 shows an embodiment of the present invention.
In the GTO gate drive circuit diagram, parts having the same functions as those in FIG. 1 are designated with the same reference numerals. E is a wide on-gate power supply, which may be any insulated DC power supply (hereinafter referred to as DC power supply E). S W is a control thyristor that turns on and off the wide on-gate current, R4 is a resistor that limits the gate current of the control thyristor S W ,
S OFF is the SW for turning off the control thyristor SW .
The off transistor R5 is a resistor that limits the current that turns on and off this switch element (S OFF ).

第3図において、オン制御信号が与えられる幅
狭のオンゲート回路と、オフ制御信号が与えられ
るオフ回路の構成は第1図と同様であるが、本考
案においては図示のように前記直流電源Eの正極
に抵抗R3の一端を接続し、この抵抗R3の他端と
GTOのゲートとの間に制御用サイリスタSWをカ
ソードがGTOのゲート側となるよう接続し、直
流電源Eの負極をGTOのカソードに接続した幅
広オンゲート回路を備え、この幅広オンゲート回
路の制御用サイリスタSWの点弧をオン用ゲート
トランスPTONの2次電圧で行い、オフ用ゲート
トランスPTOFFの2次巻線の・印を付していない
端子側にカソードを、GTOのゲートにアノード
が接続されたダイオードDFのカソードと制御用
サイリスタSWのアノード間に、SWオフ用トラン
ジスタSOFFを接続し、そのSWオフ用トランジスタ
SOFFの導通によつて制御用サイリスタSWを短絡す
るように構成し、このSWオフ用トランジスタSOFF
をオフ用ゲートトランスPTOFFの2次電圧で導通
させ、制御用サイリスタSWの消弧を行うように
する。
In FIG. 3, the configurations of the narrow ON gate circuit to which the ON control signal is applied and the OFF circuit to which the OFF control signal is applied are the same as in FIG. Connect one end of resistor R 3 to the positive terminal of , and connect the other end of this resistor R 3 with
A control thyristor SW is connected between the gate of the GTO and the cathode facing the gate of the GTO, and a wide on-gate circuit is provided in which the negative electrode of the DC power supply E is connected to the cathode of the GTO. The thyristor S W is ignited using the secondary voltage of the ON gate transformer PT ON , and the cathode is connected to the terminal side not marked with the terminal of the secondary winding of the OFF gate transformer PT OFF , and the anode is connected to the gate of the GTO. A SW- off transistor S OFF is connected between the cathode of the diode D F connected to the anode of the control thyristor SW, and the SW - off transistor
The control thyristor SW is short-circuited by conduction of S OFF , and this SW OFF transistor S OFF
is made conductive by the secondary voltage of the off gate transformer PT OFF , and the control thyristor SW is turned off.

次に、本発明による第3図実施例回路の動作説
明を第4図を用いて説明する。時間t1において第
4図aに示すオン制御信号がオン用トランジスタ
TONに印加され、オン用トランジスタTONをオン
させる。これによりオン用ゲートトランスPTON
に電圧が加わり、オン/オフ干渉防止用サイリス
タSONがオンすることによつて、PTON2次巻線→
抵抗R2→GTOゲート→GTOカソード→SON
PTON2次巻線の経路で電流が流れ、GTOをオン
させる。この時、抵抗R2の並列回路である抵抗
R4→SWゲート→SWカソードの経路にも電流が流
れ、制御用サイリスタSWをオンさせる。したが
つて直流電源Eからも抵抗R3→SW→GTOゲート
→GTOカソード→直流電源Eの経路で電流が流
れ、幅広オンゲート電流(第4図b)となる。
Next, the operation of the circuit according to the embodiment shown in FIG. 3 according to the present invention will be explained with reference to FIG. At time t1 , the on control signal shown in Figure 4a is applied to the on transistor.
Applied to T ON , turning on the on transistor T ON . This will turn on the gate transformer PT ON.
When voltage is applied to PT ON and the thyristor S ON for preventing on/off interference turns on, the PT ON secondary winding
Resistor R 2 → GTO gate → GTO cathode → S ON
PT ON Current flows through the secondary winding path, turning on the GTO. At this time, a resistor which is a parallel circuit of resistor R 2
Current also flows through the path R 4SW gate → SW cathode, turning on the control thyristor SW . Therefore, current also flows from the DC power supply E through the path of resistor R 3 →S W →GTO gate → GTO cathode → DC power supply E, resulting in a wide on-gate current (Figure 4b).

第4図aに示すように時間t2でオン制御信号が
なくなり、オン/オフ干渉防止用サイリスタSON
がオフするが、制御用サイリスタSWは引続きオ
ンして直流電源Eから幅広オンゲート電流を流し
続ける(第4図b)。
As shown in Figure 4a, the on control signal disappears at time t2 , and the thyristor S for preventing on/off interference turns on.
is turned off, but the control thyristor SW continues to be turned on and a wide on-gate current continues to flow from the DC power supply E (Fig. 4b).

時間t3において第4図cに示すようにオフ制御
信号がオフ用トランジスタTOFFに印加され、オフ
用トランジスタTOFFをオンする。これによりオフ
用ゲートトランスPTOFFに電圧が加わり、第3図
に実線で示した経路にオフ電流が流れ、GTOを
オフさせる(第4図d)。GTOがしや断するとオ
フ用ゲートトランスPTOFFの2次電圧により、SW
オフ用トランジスタSOFFに第3図に点線で示す経
路に電流が流れ、SWオフ用トランジスタSOFFをオ
ンさせる。SW用トランジスタSOFFがオンすること
により、制御用サイリスタSWに流れていた電流
がSWオフ用トランジスタSOFFに転流し、直流電源
E→抵抗R3→SOFF→PTOFF2次巻線→直流電源E
の経路に電流が流れるようになる。この動作によ
り制御用サイリスタSWがオフし、幅広オンゲー
ト電流が流れなくなる(第4図b)。時間t4でオ
フ電流は零となる。
At time t3 , an off control signal is applied to the off transistor TOFF , turning on the off transistor TOFF , as shown in FIG. 4c. As a result, a voltage is applied to the off gate transformer PT OFF , and an off current flows through the path shown by the solid line in Figure 3, turning off the GTO (Figure 4 d). When the GTO is suddenly disconnected, the secondary voltage of the OFF gate transformer PT OFF causes S W
Current flows through the off transistor S OFF through the path shown by the dotted line in Figure 3, turning on the SW off transistor S OFF . When the S W transistor S OFF turns on, the current flowing through the control thyristor S W is commutated to the S W off transistor S OFF , and the DC power supply E → resistor R 3 → S OFF → PT OFF Secondary winding Line → DC power supply E
Current begins to flow through the path. This operation turns off the control thyristor SW , and the wide on-gate current no longer flows (Figure 4b). The off-state current becomes zero at time t4 .

以上述べたように本発明によれば、比較的に簡
単な回路構成で、オン用、オフ用の2つの幅狭の
信号でGTOのオーバードライブ、幅広オンゲー
ト、オフゲートを可能とするばかりでなく、各々
の回路間の干渉を全くなくし、さらに幅広オンゲ
ート電流は完全な直流電流とすることができるよ
うになり、GTOの確実な動作をさせることが可
能となる。
As described above, according to the present invention, with a relatively simple circuit configuration, it is possible not only to overdrive the GTO and perform wide on-gate and off-gate using two narrow-width signals for on and off; Interference between each circuit is completely eliminated, and the wide on-gate current can be made into a complete direct current, making it possible to operate the GTO reliably.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のゲートターンオフサイリスタの
ゲート駆動回路図、第2図は第1図回路の動作説
明図、第3図は本発明の一実施例を示すゲートタ
ーンオフサイリスタのゲート駆動回路図、第4図
は第3図回路の動作説明図である。 TON…オン用トランジスタ、TOFF…オフ用トラ
ンジスタ、TW1,TW2…幅広ゲートパルス発生用
トランジスタ、PTON…オン用絶縁パルストラン
ス、PTOFF…オフ用絶縁パルストランス、PTW
幅広用絶縁パルストランス、DW1,DW2,DF…ダ
イオード、SON…オン/オフ干渉防止用サイリス
タ、SW…制御用サイリスタ、SOFF…SWオフ用ト
ランジスタ、GTO…ゲートターンオフサイリス
タ、R1〜R5…抵抗。
FIG. 1 is a gate drive circuit diagram of a conventional gate turn-off thyristor, FIG. 2 is an explanatory diagram of the operation of the circuit shown in FIG. 1, and FIG. 3 is a gate drive circuit diagram of a gate turn-off thyristor showing an embodiment of the present invention. FIG. 4 is an explanatory diagram of the operation of the circuit shown in FIG. T ON ...Transistor for ON, T OFF ...Transistor for OFF, T W1 , T W2 ...Transistor for wide gate pulse generation, PT ON ...Isolated pulse transformer for ON, PT OFF ...Isolated pulse transformer for OFF, PT W ...
Wide isolation pulse transformer, D W1 , D W2 , D F ... diode, S ON ... thyristor for preventing on/off interference, S W ... control thyristor, S OFF ... transistor for SW OFF, GTO ... gate turn-off thyristor, R1 to R5 ...Resistance.

Claims (1)

【特許請求の範囲】[Claims] 1 低圧側直流電源の正極および負極の間に、オ
ン用ゲートトランスの1次巻線とオン用トランジ
スタの直列回路を接続しかつオフ用ゲートトラン
スの1次巻線とオフ用トランジスタの直列回路を
接続し、前記オン用ゲートトランスの2次巻線の
正端子と被制御ゲートターンオフサイリスタのゲ
ート間に第2の抵抗R2を接続し、かつオン用ゲ
ートトランスの2次巻線の負端子と被制御ゲート
ターンオフサイリスタのカソード間にオン/オフ
干渉防止用サイリスタをアノードが被制御ゲート
ターンオフサイリスタのカソード側となるように
接続するとともに、オン用ゲートトランスの2次
巻線の正端子とオン/オフ干渉防止用サイリスタ
のゲートの間に第1の抵抗R1を接続したオーバ
ードライブ回路、前記オフ用ゲートトランスの2
次巻線の正端子と被制御ゲートターンオフサイリ
スタのカソードを接続しかつ負端子と被制御ゲー
トターンオフサイリスタのゲートとの間にアノー
ドが被制御ゲートターンオフサイリスタのゲート
側となるようにダイオードを接続したオフゲート
回路、高圧側直流電源の正極に第3の抵抗R3
一端を接続しかつ抵抗R3の他端を制御用サイリ
スタのアノードに接続するとともに、該制御用サ
イリスタのカソードを被制御ゲートターンオフサ
イリスタのゲートに接続し、前記高圧側直流電源
の負極と被制御ゲートターンオフサイリスタのカ
ソードを、制御用サイリスタのゲートと前記オン
用ゲートトランスの正端子との間に第4の抵抗
(R4)を接続した幅広オンゲート回路を備えると
ともに、前記制御用サイリスタのアノードにコレ
クタがかつ前記ダイオードのカソードにエミツタ
が接続するように制御用サイリスタオフ用トラン
ジスタを設け、該制御用サイリスタオフ用トラン
ジスタのベースと前記オフ用ゲートトランスの正
端子の間に第5の抵抗(R5)を接続したことを
特徴とするゲートターンオフサイリスタのゲート
駆動回路。
1 Connect the primary winding of the on-gate transformer and the series circuit of the on-transistor between the positive and negative poles of the low-voltage side DC power supply, and connect the primary winding of the off-gate transformer and the series circuit of the off-transistor. A second resistor R 2 is connected between the positive terminal of the secondary winding of the ON gate transformer and the gate of the controlled gate turn-off thyristor, and a second resistor R 2 is connected between the negative terminal of the secondary winding of the ON gate transformer and the gate of the controlled gate turn-off thyristor. An on/off interference prevention thyristor is connected between the cathode of the controlled gate turn-off thyristor so that the anode is on the cathode side of the controlled gate turn-off thyristor, and the positive terminal of the secondary winding of the on gate transformer is connected to the on/off interference prevention thyristor. an overdrive circuit in which a first resistor R1 is connected between the gates of the thyristor for preventing off interference;
The positive terminal of the next winding was connected to the cathode of the controlled gate turn-off thyristor, and a diode was connected between the negative terminal and the gate of the controlled gate turn-off thyristor so that the anode was on the gate side of the controlled gate turn-off thyristor. In the off-gate circuit, one end of the third resistor R 3 is connected to the positive electrode of the high voltage side DC power supply, the other end of the resistor R 3 is connected to the anode of the control thyristor, and the cathode of the control thyristor is connected to the controlled gate turn-off. A fourth resistor (R 4 ) is connected to the gate of the thyristor, and connects the negative terminal of the high-voltage side DC power supply and the cathode of the controlled gate turn-off thyristor, and between the gate of the control thyristor and the positive terminal of the on-gate gate transformer. a wide on-gate circuit connected to the control thyristor, and a control thyristor off transistor so that the collector is connected to the anode of the control thyristor and the emitter is connected to the cathode of the diode, and the base of the control thyristor off transistor is connected to the control thyristor off transistor. A gate drive circuit for a gate turn-off thyristor, characterized in that a fifth resistor (R 5 ) is connected between the positive terminal of the gate transformer for turning off.
JP58030769A 1983-02-28 1983-02-28 Gate driving circuit of gate turn-off thyristor Granted JPS59158127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58030769A JPS59158127A (en) 1983-02-28 1983-02-28 Gate driving circuit of gate turn-off thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58030769A JPS59158127A (en) 1983-02-28 1983-02-28 Gate driving circuit of gate turn-off thyristor

Publications (2)

Publication Number Publication Date
JPS59158127A JPS59158127A (en) 1984-09-07
JPH0324817B2 true JPH0324817B2 (en) 1991-04-04

Family

ID=12312883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58030769A Granted JPS59158127A (en) 1983-02-28 1983-02-28 Gate driving circuit of gate turn-off thyristor

Country Status (1)

Country Link
JP (1) JPS59158127A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6673801B2 (en) * 2016-10-24 2020-03-25 ニチコン株式会社 Gate pulse generation circuit and pulse power supply device

Also Published As

Publication number Publication date
JPS59158127A (en) 1984-09-07

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