JPH0325756B2 - - Google Patents
Info
- Publication number
- JPH0325756B2 JPH0325756B2 JP56113829A JP11382981A JPH0325756B2 JP H0325756 B2 JPH0325756 B2 JP H0325756B2 JP 56113829 A JP56113829 A JP 56113829A JP 11382981 A JP11382981 A JP 11382981A JP H0325756 B2 JPH0325756 B2 JP H0325756B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- oscillation
- heavy load
- power
- timer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G3/00—Producing timing pulses
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Electric Clocks (AREA)
- Electromechanical Clocks (AREA)
Description
【発明の詳細な説明】
本発明は、重負荷装置を有する電子時計に関
し、特に該電子時計の時間標準となる信号を発生
する発振回路の発振開始時の重負荷コントロール
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece having a heavy load device, and more particularly to heavy load control at the time of starting oscillation of an oscillation circuit that generates a signal serving as a time standard for the electronic timepiece.
本発明の目的は、発振回路の発振を確実に起動
させるための重負荷コントロール方式を得ること
である。 An object of the present invention is to obtain a heavy load control method for reliably starting oscillation of an oscillation circuit.
従来、重負荷装置を有する電子時計において
は、電源投入等による発振開始時に重負荷の制御
は行なわれていなかつた。従つて、発振が安定す
る以前に、重負荷装置が駆動を始めることがあつ
た。最近では、電子時計の小型、薄型化が進めら
れ、それに共なつて電源として使用する電池も小
型、薄型化されたものが使用されており、特に電
子腕時計においてはこの傾向が強くなつている。
このような電池は内部インピーダンスが高く、重
負荷装置を駆動する様な大きな電流を流すと電圧
降下を生じてしまう。このため、発振が安定する
以前に、重負荷装置が駆動を始め電源電圧降下が
起こると、発振が不安定になつたり、停止してし
まうことがある。特に低温では、電池の内部イン
ピーダンスが増大するので、この危険性が増して
くる。 Conventionally, in an electronic timepiece having a heavy load device, heavy load control has not been performed when oscillation is started by turning on the power or the like. Therefore, the heavy load device may start driving before the oscillation has stabilized. Recently, electronic watches have become smaller and thinner, and along with this, batteries used as power sources have also become smaller and thinner, and this trend has become particularly strong in electronic wristwatches.
Such a battery has a high internal impedance, and when a large current such as that used to drive a heavy load device is passed through the battery, a voltage drop occurs. Therefore, if a heavy load device starts driving and a power supply voltage drop occurs before the oscillation is stabilized, the oscillation may become unstable or stop. This risk increases, especially at low temperatures, as the battery's internal impedance increases.
本発明は、斯かる問題を排除し安定した発振を
起動させる方式を与えるものであり、以下図面に
より詳細な説明を加える。 The present invention eliminates such problems and provides a method for starting stable oscillation, and will be described in more detail below with reference to the drawings.
第1図は、本発明による電子時計の電子回路の
構成例である。 FIG. 1 shows an example of the configuration of an electronic circuit of an electronic timepiece according to the present invention.
第1図において、1は時間標準となる信号を発
生する発振回路であり、2は分周回路で時間標準
信号を分周し1秒周期の信号CLを作り出す。3
は時刻カウンタ群であり、1秒周期の信号を用い
て時刻を計測する。4は機能制御回路であり、電
子時計が有する、照明装置、音響発生装置等の重
負荷装置も含む各機能制御を司り、各重負荷装置
の駆動信号5も作り出す。6は重負荷装置であ
り、入力が論理「1」である時、動作する。7は
電源の投入を検出するパワー、オン検出回路乃至
発振の停止を検出する発振停止検出回路であり、
それぞれの状態を検出している時は「0」を出力
する。8及び9はそれぞれ、Dタイプ−フリツ
プ・フロツプ8(以下、F/Fと略す)、マスタ
ータイプ・ラツチ9であり、両者で分周回路2よ
り得られる1秒周期信号CLを基準信号として時
間を計測するタイマー回路を構成し、さらに
NANDゲート10,11と共に重負荷駆動禁止
回路を構成している。 In FIG. 1, 1 is an oscillation circuit that generates a signal serving as a time standard, and 2 is a frequency dividing circuit that divides the frequency of the time standard signal to produce a signal CL with a period of 1 second. 3
is a group of time counters, which measures time using a signal with a period of 1 second. Reference numeral 4 denotes a function control circuit, which controls various functions of the electronic watch, including heavy load devices such as lighting devices and sound generators, and also generates drive signals 5 for each heavy load device. 6 is a heavy load device, which operates when the input is logic "1". 7 is a power on detection circuit that detects when the power is turned on or an oscillation stop detection circuit that detects the stop of oscillation;
When each state is detected, "0" is output. 8 and 9 are a D-type flip-flop 8 (hereinafter abbreviated as F/F) and a master-type latch 9, respectively, and both of them measure time using the 1-second periodic signal CL obtained from the frequency divider circuit 2 as a reference signal. Configure a timer circuit to measure the
Together with NAND gates 10 and 11, it constitutes a heavy load drive prohibition circuit.
第2図は、第1図の回路のタイミング・チヤー
トである。 FIG. 2 is a timing chart for the circuit of FIG.
第2図において、CLは分周回路2より得られ
る1秒周期信号、は検出回路7の出力で、8の
F/F、9のラツチのリセツト信号となつてお
り、論理「0」でそれぞれにリセツトをかける。
Qは8のF/Fの出力であり、Mは9のラツチの
出力である。リセツト信号が「0」のときは、
Mも「0」であり、又が「1」になつてからは
8,9から構成されるタイマー回路の働きで、少
なくともt秒(t<1)以上、Mは「0」のまま
固定される。Mが「0」である期間は、重負荷駆
動信号5は10,11のNANDゲートで禁止さ
れるので、重負荷装置6の入力は「0」となり重
負荷は駆動しない。 In Fig. 2, CL is a 1-second periodic signal obtained from the frequency divider circuit 2, and CL is the output of the detection circuit 7, which serves as a reset signal for the F/F at 8 and the latch at 9, and is set to logic "0". Apply a reset.
Q is the output of 8 F/Fs, and M is the output of 9 latches. When the reset signal is “0”,
M is also "0", and once it becomes "1", M remains fixed at "0" for at least t seconds (t<1) due to the action of the timer circuit composed of 8 and 9. Ru. During the period when M is "0", the heavy load drive signal 5 is inhibited by the NAND gates 10 and 11, so the input of the heavy load device 6 becomes "0" and the heavy load is not driven.
以上の様に、本発明によれば発振開始時に一定
時間重負荷駆動を禁止し電源電圧降下を防ぐこと
ができるため、安定した発振を起動させることが
可能となる。また、発振回路の特性等により、重
負荷駆動禁止時間を変更するとしても、タイマー
回路の僅かな変更で容易に適用可能である。さら
に、使用するタイマー回路は本実施例に限定され
るものではなく、本発明の実施には種々のタイマ
ー回路を用いることが可能である。 As described above, according to the present invention, heavy load driving can be prohibited for a certain period of time at the start of oscillation to prevent a drop in the power supply voltage, thereby making it possible to start stable oscillation. Furthermore, even if the heavy load drive prohibition time is changed depending on the characteristics of the oscillation circuit, this can be easily applied by making slight changes to the timer circuit. Furthermore, the timer circuit used is not limited to this embodiment, and various timer circuits can be used to implement the present invention.
第1図……本発明による電子時計の電子回路構
成例、第2図……第1図の回路のタイミング・チ
ヤート。
FIG. 1 shows an example of the electronic circuit configuration of an electronic timepiece according to the present invention, and FIG. 2 shows a timing chart of the circuit shown in FIG.
Claims (1)
なくとも1つ以上を有する電子時計において、電
源投入を検出するパワーオン検出回路、前記電源
の投入により発振を開始する発振回路、該発振回
路の出力信号を分周する分周回路、該パワーオン
検出回路の出力信号によりリセツトされるととも
に該出力信号が反転したときに前記分周回路から
の出力パルスの計数を開始するタイマー回路と、
該タイマー回路の出力信号により制御され該タイ
マー回路が所定パルス数計数するまで前記重負荷
の駆動を禁止する重負荷駆動禁止回路を有し、且
つ前記タイマー回路が前記所定パルス数計数する
時間は前記発振回路が安定した発振をするのに十
分な時間に設定されてなることを特徴とする電子
時計。1. In an electronic watch that has at least one of the heavy loads of a lighting device and a sound generating device, a power-on detection circuit that detects power-on, an oscillation circuit that starts oscillation when the power is turned on, and an output of the oscillation circuit a frequency divider circuit that divides the frequency of a signal; a timer circuit that is reset by the output signal of the power-on detection circuit and starts counting output pulses from the frequency divider circuit when the output signal is inverted;
A heavy load drive inhibiting circuit is controlled by an output signal of the timer circuit and prohibits driving of the heavy load until the timer circuit counts a predetermined number of pulses, and the time period for the timer circuit to count the predetermined number of pulses is within the range of the timer circuit. An electronic clock characterized in that the oscillation circuit is set at a time sufficient for stable oscillation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113829A JPS5815187A (en) | 1981-07-20 | 1981-07-20 | Multi-function electronic clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113829A JPS5815187A (en) | 1981-07-20 | 1981-07-20 | Multi-function electronic clock |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5815187A JPS5815187A (en) | 1983-01-28 |
| JPH0325756B2 true JPH0325756B2 (en) | 1991-04-08 |
Family
ID=14622081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56113829A Granted JPS5815187A (en) | 1981-07-20 | 1981-07-20 | Multi-function electronic clock |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5815187A (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5168159A (en) * | 1974-12-11 | 1976-06-12 | Citizen Watch Co Ltd | SUISHOHATSUSHINKAIRO |
| JPS5483475A (en) * | 1977-12-15 | 1979-07-03 | Matsushita Electric Works Ltd | Electronic time striking circuit |
| JPS5517246A (en) * | 1978-07-19 | 1980-02-06 | Matsushita Electric Ind Co Ltd | Manufacturing method of conical motor core |
| JPS5660381A (en) * | 1979-10-23 | 1981-05-25 | Sanyo Electric Co Ltd | Electronic timepiece with cell life display |
-
1981
- 1981-07-20 JP JP56113829A patent/JPS5815187A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5815187A (en) | 1983-01-28 |
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