JPH0325796B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a modulation effect device used in electronic musical instruments and other musical sound generating devices, and particularly to a device that applies a modulation effect to a digital musical sound signal.

BACKGROUND TECHNOLOGY A known digital musical tone modulator that can digitally apply delay modulation while keeping the sampling clock frequency constant is the one disclosed in Japanese Patent Application Laid-open No. 83894/1983. Teru. In this type of digital tone modulation device,
As shown in Figure 1 of the same publication, an input signal (digital musical tone signal) is input to the read/write memory, a write address and a read address of the memory are designated by the address calculation circuit, and the write address is input to the read/write memory. The read addresses are specified in order at regular intervals in synchronization with the signal sampling period, but the read addresses are modulated according to the output of the modulation signal generator. By modulating the read address in this manner, it is possible to delay-modulate the digital musical tone signal while keeping the sampling clock frequency constant, thereby obtaining a phase modulation effect.

Problems to be Solved by the Invention However, in the prior art as described above, when a periodic modulation signal is used, depending on the degree of modulation, components exceeding the sampling frequency may be included in the modulated musical tone signal. This was the cause of unpleasant periodic noise.

This invention was made in view of the above points,
It is an object of the present invention to provide a modulation effect device capable of removing or reducing the above-mentioned unpleasant periodic noise.

Means for Solving the Problems In order to achieve the above-mentioned object, the present invention includes a noise signal generating means and a noise modulating means for modulating a modulation signal with a noise signal, and the noise modulating means The present invention is characterized in that the read address signal of the memory is modulated in accordance with the modulated signal.

Effect When the modulation signal is modulated by the noise signal, a noise component is added to the modulation signal, and noise components that may be included in the musical tone signal modulated by this modulation signal are removed. Periodicity disappears (or becomes less noticeable).

In order to make periodic noise less noticeable and also not to impair the periodicity of the modulated signal, when changing the modulated signal using the noise signal in the noise modulation means, the value of the modulated signal should not be changed too much. It is better to do so. For example, when a modulated signal is considered divided into an integer part and a decimal part, it is preferable to change the weight of the decimal part by a noise signal.

Embodiments Hereinafter, some embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment in which the present invention is applied to a modulation effect device using an interpolation circuit 6 to improve modulation resolution. The modulation signal generating means 1 digitally generates a modulation signal, and for example, the modulation signal has periodicity. The noise signal generator 7 digitally generates a noise signal, for example, one bit of data "1" or "0" is generated randomly.
The adder 8, which corresponds to noise modulation means, modulates the modulation signal generated by the modulation signal generation means 1 with the noise signal generated by the noise signal generator 7, and adds noise to the lower bits of the modulation signal. By adding the signals, the value of the modulation signal is randomly changed within a small range. Therefore, the overall periodicity of the modulated signal is not impaired, but it is modulated so that a random noise component is superimposed thereon with a fine amplitude. The modulated signal is input to the address control means 2.

The address control means 2 generates a write address signal according to a predetermined sampling period corresponding to the sampling period of the digital musical tone signal to be modulated, and also generates a write address signal which is modulated according to the modulation signal modulated by noise in the adder 8. It generates a read address signal depending on the state. read/write memory 3
inputs the digital musical tone signal to be modulated into the data input, writes the sample point amplitude value data of the musical tone signal according to the write address signal, and reads the stored sample point amplitude value data according to the read address signal. put out. The generation timing of the write address signal and the read address signal is synchronized with the sampling period.

Writing is always carried out regularly using a write address signal, and each sample point amplitude value data of the input digital musical tone signal is stored in each address of the memory 3 one after another. On the other hand, since the read address signal is modulated by the modulation signal, the sample point amplitude value data stored in the memory 3 is not read out at equally spaced addresses, but is read out in a phase modulated state. However, only by modulating the read address, it is possible to modulate the phase amount corresponding to one sampling period only to the minimum level (minimum resolution), and therefore not very good resolution can be obtained.

Therefore, an interpolation circuit 6 is provided to improve the resolution of phase modulation. The interpolation circuit 6 includes a latch circuit 61 that latches the amplitude value data S _j of a certain sample point, and a latch circuit 61 that latches the amplitude value data S j of a certain sample point, and a latch circuit 61 that latches the amplitude value data S j of a certain sample point.
A latch circuit 62 that latches S _j+1 , a subtracter 63 that calculates the difference S _j+1 −S _j between the latched adjacent sample point amplitude value data, and an output of the subtracter 63 using interpolation coefficient data. It includes a multiplier 64 for weighting, and an adder 65 for adding the output of the multiplier 64 and the amplitude value data S _j of the current sample point output from the latch circuit 61. As interpolation coefficient data,
The modulated signal output from the adder (modulating means) 8 is used. The modulated signal is now divided into an integer part and a decimal part, and the integer part data
IS is applied to the address control means 2 for modulating the read address, and its fractional part data FR is applied to the multiplier 64 of the interpolation circuit 6 as interpolation coefficient data. In this case, the adder 8 may add the noise signal to the weight of the fractional part of the modulated signal. For example, a 1-bit noise signal is added to the weight of the least significant bit of the decimal part data or an appropriate bit above it. In the example shown, interpolation circuit 6
The interpolation in is linear interpolation, but since the interpolation coefficient data is modulated by a noise signal, interpolation including random noise components is performed.

Note that latching the amplitude value data of two adjacent sample points in the latch circuits 61 and 62 within the same sampling time is performed by controlling the readout of the memory 3 in a time-division manner by the address control means 2. That is, at the beginning of one sample time, the amplitude value data of the current sample point is read out from the memory 3 according to the read address signal, and in synchronization with this, the output of the memory 3 is latched in the latch circuit 61, and then at the same sample time. This can easily be done by reading out the amplitude value data of the next sample point from the memory 3 a little later than that, and latching the output of the memory 3 in the latch circuit 62 in synchronization with this.

2 to 4 show another embodiment of the present invention, in which the readout output of the memory 3 is delayed without using the interpolation circuit 6 as shown in FIG. 1 in order to improve the resolution of phase modulation. Each delay means is used to In the examples shown in FIGS. 2 and 3, the sample point amplitude value data once read out from the memory 3 is subjected to variable delay control according to the fractional part data FR of the modulation signal, and the delay means 4 is used for this purpose. , a latch circuit 41 and a down counter 42 are used in FIG. 2, and a shift register 4 is used in FIG.
3 and a latch circuit 44 are used. In the example shown in FIG. 4, the read timing of the memory 3 itself is controlled with variable delay according to the fractional part data FR of the modulation signal, and the delay means 5 is used for this purpose.
A latch circuit 51 and a down counter 52 are used as the latch circuit 51 and the down counter 52.

First, referring to FIG. 2, the modulation signal generating means 1 includes a modulation signal generator 11 and a modulation signal generator 1
a multiplier 12 for multiplying the digital modulation signal generated in step 1 by a modulation depth coefficient;
The digital modulation signal output from the noise signal generator 7 is applied to the adder 8 as a noise modulation means in the same manner as described above, and the noise signal from the noise signal generator 7 is added to the fractional part of the modulation signal. Address control means 2
consists of a modulo N counter 21 that sequentially counts clock pulses φ ₁ corresponding to the sampling period of the input digital musical tone signal;
a gate 22 that gates the count output of 1 and outputs it as a write address signal; an arithmetic unit 23 that modulates the count output of the counter 21 with the integer part data IS of the modulation signal output from the adder 8; It includes a gate 24 which gates the output of the arithmetic unit 23 and outputs it as a read address signal. The modulus number N of the counter 21 corresponds to the total number of addresses in the memory 3. The computing unit 23 is
An example of this is an adder/subtractor, in which the integer part data of a modulated signal is distinguished by sign bits.
IS is input, and the data IS is added to or subtracted from the output of the counter 21 (ie, the write address signal), and a predetermined offset value OFS is subtracted from (or added to). In this way, the read address signal is obtained by modulating the write address signal according to the integer part of the modulation signal and offset it by a predetermined value. The offset is a control for providing an appropriate shift between the read address and the write address in order to prevent reading and writing of the memory 3 performed within the same sampling period from interfering with each other.

The outputs of both gates 22 and 24 are wired-OR connected and applied to the address input ADRS of the memory 3. The data input DI of the memory 3 is supplied with a digital tone signal to be modulated, as described above.

The delay means 4 includes a latch circuit 41 to which the read output of the memory 3 is input, and a down counter 42. Fractional part data FR of the modulation signal outputted from the adder 8 is given to an inversion control circuit 13, and each bit of the data FR is controlled to be inverted or non-inverted depending on its sign. For example, if the sign bit of the modulation signal output from the adder 8 is
When this sign bit is "positive", the inversion control circuit 13 inverts the fractional part data FR and outputs it as data, and when the sign bit is "negative", it inverts the fractional part data FR. Output as is without inverting. down counter 4
2 is the decimal part data FR output from the inversion control circuit 13 or its inverted data which is input to the preset data input PD, and the data FR or which is preset input when the clock pulse φ ₂ applied to the preset control input PS is "1". The master clock pulse φ _M is then counted down until the count becomes zero.
The zero detection pulse _Z0 output from the counter 42 is applied to the latch control input of the latch circuit 41, and when the count content of the counter 42 becomes zero, the pulse _Z0 rises to "1". Latch the read output of memory 3. Latch circuit 4
The signal latched at 1 is output as an output signal of this modulation effect device and is applied to, for example, a D/A converter.

An example of the sampling clock pulse φ ₀ is shown in FIG. 5, and has a pulse width equal to one period of the master clock pulse φ _M and a period synchronized with one sampling period T of the digital musical tone signal. . This sampling clock pulse φ ₀ is applied to the modulation signal generator 11 and used as a clock signal for controlling modulation signal generation. The sampling clock pulse φ ₀ is also used as an operation enable signal for the multiplier 12. Multiplier 1
2 multiplies the modulation depth coefficient and the modulation signal at the beginning of the sampling period by this pulse φ ₀ ,
Thereafter, the multiplication result is held and output during the sampling period.

Immediately after the sampling clock pulse φ ₀ , the fifth
Same pulse width and same period T as shown in the figure.
A clock pulse _φ1 is generated. This sampling clock pulse _φ1 is applied to the noise signal generator 7 and is used as a clock signal for noise signal generation control. Therefore, the noise signal randomly changes to "1" or "0" using the sampling period T as the minimum unit. Further, the clock pulse φ ₁ is used not only as a count clock for the counter 21 as described above, but also as an operation enable signal for the adder 8. Adder 8
uses this pulse φ ₁ to add the noise signal and the modulation signal at the beginning of the sampling period, and thereafter holds and outputs the addition result (modulation signal modified by the noise signal) during the sampling period.

A clock pulse φ ₂ having the same pulse width and the same period is generated a little later than the clock pulse φ ₁ as shown in FIG. The arithmetic unit 23 is enabled by this clock pulse φ ₂ and performs the address modulation and offset calculation described above, and thereafter holds and outputs the calculation results until the next pulse φ ₂ is generated. This clock pulse φ ₂ is also applied to gate 22. As shown in FIG. 5, a signal obtained by inverting this clock pulse φ ₂ is a clock pulse φ ₃ which is applied to the gate 24 and also to the read/line input R/ of the memory 3.

Memory 3 stores the pulse φ ₃ applied to input R/
When is "0", the write mode is set. At this time, the gate 22 is opened by the pulse φ ₂ of "1", and the count content of the counter 21 is
2 to memory 3 as a write address signal.
is given to the address input ADRS. counter 2
1 is counted up by one every sampling period by clock pulse _φ1 . Therefore, amplitude value data for each sample point of the input digital musical tone signal is stored in sequential addresses in the memory 3.

Memory 3 stores the pulse φ ₃ applied to input R/
When is "1", the read mode is set. At this time, the gate 24 is open, and the output of the arithmetic unit 23 is used as the read address signal for the address input ADRS.
given to. Here, if the output of the counter 21, that is, the write address signal, was not modulated by the modulation signal, the read address signal would simply be the write address signal offset by a constant value, and the progress of the read address would be completely different. An unmodulated and therefore completely unmodulated digital musical tone signal is read out from the memory 3. However, by modulating the count output of the counter 21 by the integer part IS of the modulation signal, the progress of the read address is modulated, and as a result, a phase-modulated digital musical tone signal is read out from the memory 3. For example, when the modulation signal has a positive sign, the phase advances (in the direction of compressing the waveform on the time axis).
When the waveform is modulated and has a negative sign, it is modulated in the slow phase direction (in the direction of stretching the waveform on the time axis).

The down counter 42 outputs decimal part data FR or its inverted data at the timing of clock pulse _φ2 .
Since the configuration is such that FR is preset and then the master clock pulse φ _M is counted down until the count becomes zero, the falling edge of the clock pulse φ ₂ (that is, the rising edge of the clock pulse φ ₃ ), a zero detection pulse Z ₀ is generated when a number of master clock pulses φ _M corresponding to the value of the decimal part data FR or inverted data is counted. At the timing of this zero detection pulse Z ₀ , the readout output of the memory 3 is activated by the latch circuit 41.
The signal is latched and output from the latch circuit 41. Therefore, the read output of the memory 3 is not output immediately when reading is started at the rising timing of the clock pulse φ ₂ , but is delayed by a minute amount of time corresponding to the value of the fractional part data FR. . The maximum value of this delay time is one sampling period T, and time axis modulation (phase modulation) of less than one sampling period is applied by the delay means 4 according to the fractional part data FR of the modulation signal. As is clear, modulation exceeding one sampling period T causes the integer part data IS of the modulated signal to
This is realized by modulating the read address of the memory 3 according to the .

The inversion control circuit 13 is for switching the delay control according to the decimal part data FR to advance phase control or slow phase control according to the positive or negative of the modulation signal. For example, when it is positive, it changes the delay control according to the decimal part data FR. The modulation function is to make the modulation in the leading phase direction, and when it is negative, make it the modulation in the slow phase direction. In the above, the inversion control circuit 1
In 3, when the sign bit is positive, the decimal part data FR is inverted, and when it is negative, it is not inverted. On the contrary, it may be non-inverted when it is positive and inverted when it is negative.

Next, to explain the embodiment shown in FIG.
The only difference from the figure is the delay means 4, and the rest is the same. In the embodiment shown in FIG. 3, the readout output from the memory 3 is input to a multistage shift register 43, so that the read sample point amplitude value data itself is delayed by a desired time. Fractional part data FR of the modulation signal output from the inversion control circuit 13
Or its inverted data is input to the latch circuit 44 and latched at the timing of clock pulse _φ2 . The shift register 43 has a latch circuit 44.
The configuration is such that the number of signal delay stages can be variably controlled according to the value of the fractional part data RF or . The shift register 43 is shift-controlled in accordance with the master clock pulse φ _M , and transfers the sample point amplitude value data read from the memory 3 to the master by the number of stages corresponding to the fractional part data FR of the modulation signal. It is delayed and output according to clock pulse φ _M. Thus, the second
Delay control similar to that shown in the figure is performed.

Next, the embodiment shown in FIG. 4 will be explained.
The only difference from the figure is the read timing delay means 5, and the rest is the same. The read timing delay means 5 includes a latch circuit 51 for latching the read output of the memory 3 and a down counter 52. The down counter 52 is the same as the down counter 42 in _FIG .
Output a zero detection pulse Z ₀ after a time corresponding to or. This zero detection pulse _Z0 is applied to the read control input R of the memory 3 and the latch circuit 5
1 latch control input. A clock pulse φ ₂ is applied to the write control input W of the memory 3. Therefore, memory 3 receives clock pulse φ ₃
A read address signal is applied via the gate 24 in response to the rising edge of , but it is not read out immediately, but becomes readable after a delay of a time corresponding to the value of the fractional part data FR of the modulation signal, and the read address signal is then read out. Ru. The read sample point amplitude value data is simultaneously latched by the latch circuit 51 and output.

In each of the embodiments described above, the adder 8 serving as the noise modulation means may be a subtractor or other arithmetic unit. Furthermore, the noise signal generated by the noise signal generator 7 is not limited to one bit, but may be random digital data of multiple bits. Also, in the above, the minimum change time unit of the noise signal is 1
Although the sampling period is set to T, it may be longer (for example, it may be a relatively long time such as one period, 1/2 period, or 1/4 period of the modulation signal).

A circuit for obtaining fractional part data FR which is controlled to be inverted or non-inverted depending on the positive/negative of the modulation signal is an inversion control circuit 1 as shown in FIGS. 2 to 4.
It is not limited to 3, and can be changed arbitrarily in terms of design. It is also possible to use up counters in place of the down counters 42 and 52 in Figures 2 and 4, and to use a predetermined count value detection pulse in place of the zero detection pulse _Z0 . In this case, the inversion/non-inversion control of the fractional part data FR according to the positive/negative of the modulation signal is opposite to that when a down counter is used.

In each of the above embodiments, a case has been described in which one channel's worth of digital musical tone signals is modulated, but it is of course possible to modulate a plurality of channels' worth of digital musical tone signals by time-division processing or parallel processing. .

Further, in the above embodiment, the case where one series of modulation (modulation based on one modulation signal) is performed on the input digital musical tone signal has been explained, but as shown in the above-mentioned Japanese Patent Application Laid-Open No. 83894/1983, Furthermore, the input digital musical tone signal may be subjected to a plurality of series of modulations (modulation based on a plurality of mutually different modulation signals) by time-division processing or parallel processing.

Furthermore, the read/write control of the memory 3 is not limited to the control by the dedicated circuit as described above, but may be controlled by a computer program. For example, it is known to use control by a computer program in a modulation effect device, as shown in Japanese Patent Application Laid-open No. 58-14191 or Japanese Patent Application Laid-open No. 58-50595. Further, the modulation signal generator 11 may adopt any configuration, for example, a memory read method as shown in Japanese Patent Laid-Open No. 57-14894, an arithmetic method, or a method of A/D converting an analog modulation signal. Any one can be used.

Effects of the Invention As described above, according to the present invention, since the modulation signal is changed by a random noise signal, the periodic noise component is canceled out in the musical tone signal modulated by the modulation signal. become,
Harsh periodic noise can be removed or reduced.

[Brief explanation of the drawing]

FIG. 1 is an electrical block diagram showing one embodiment of the modulation effect device according to the present invention, FIG. 2 is an electrical block diagram showing another embodiment of the same, and FIG. 3 is a still another embodiment of the same. FIG. 4 is an electrical block diagram showing still another embodiment, and FIG. 5 is a timing chart showing an example of clock pulses and output pulses used in FIGS. 2 to 4. 1...Modulation signal generation means, 2...Address control means, 3...Readable/writable memory, 4, 5...
Delay means, 6... interpolation circuit, 7... noise signal generation means, 8... adder as noise modulation means.

Claims (1)

[Claims] 1. a modulation signal generating means, an address control means for generating a write address signal according to a predetermined sampling period, and a read address signal modulated in accordance with the modulation signal; A modulation effect device comprising: a readable/writable memory for writing a digital musical tone signal to be output according to the write address signal and reading the digital musical tone signal according to the read address signal, comprising: noise signal generating means; and the modulation effect device. noise modulation means for modulating the modulation signal generated by the signal generation means with the noise signal generated by the noise signal generation means and providing the modulated modulation signal to the address control means; Characteristic modulation effect device. 2. The modulation effect device according to claim 1, wherein the noise modulation means adds or subtracts the noise signal with a relatively small weight to the modulation signal generated by the modulation signal generation means. 3. modulation signal generation means for generating a modulation signal consisting of an integer part and a decimal part; noise signal generation means; converting the modulation signal generated by the modulation signal generation means into a noise signal generated by the noise signal generation means; noise modulation means for generating a write address signal according to a predetermined sampling period, and generating a read address signal modulated according to an integer part of the modulation signal modulated by the noise modulation means; address control means; a readable/writable memory for writing a digital musical tone signal to be modulated according to the write address signal and reading the digital musical tone signal according to the read address signal; modulating the digital musical tone signal by the noise modulating means; a modulation effect device comprising: interpolation means for performing an interpolation calculation on the digital musical tone signal read from the memory according to the decimal part of the modulated signal. 4. The modulation effect device according to claim 3, wherein the noise modulation means adds or subtracts the noise signal in accordance with the weight of the decimal part of the modulation signal. 5. Modulation signal generation means for generating a modulation signal consisting of an integer part and a decimal part; noise signal generation means; and converting the modulation signal generated by the modulation signal generation means into a noise signal generated by the noise signal generation means. noise modulation means for generating a write address signal according to a predetermined sampling period, and generating a read address signal modulated according to an integer part of the modulation signal modulated by the noise modulation means; address control means; a readable/writable memory for writing a digital musical tone signal to be modulated according to the write address signal and reading the digital musical tone signal according to the read address signal; modulating the digital musical tone signal by the noise modulating means; A modulation effect device comprising: delay means for delaying the readout output of the memory according to the fractional part of the modulated signal. 6. The modulation effect device according to claim 5, wherein the noise modulation means adds or subtracts the noise signal in accordance with the weight of the decimal part of the modulation signal.