JPH0325970B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit composed of MOS transistors, and more particularly to a logic circuit that prevents malfunctions that occur in ratioless circuits and increases the speed of operation.

2. Description of the Related Art In recent years, as semiconductor integrated circuits have become more highly integrated, ratioless circuits have been increasingly adopted to construct logic circuits in terms of integration and low power consumption. Figure 1 is
This shows an example of the simplest ratioless circuit in CMOS circuits, which has the following advantages: no steady current flows, the load and driver MOS have the same size, can be designed small, and can increase the degree of integration. Due to its advantages, it is used in logic circuits for driving various electronic devices as described above. However, in the ratioless circuit described above, if an asynchronous input signal iNa is applied to the clock φ, which will be described next, there is a risk that a signal at an intermediate level of the power supply voltage will be derived as the output signal outa. installed on the next level
If it is applied to a CMOS circuit, it can cause malfunction, and it also has the disadvantage that current flows through circuits that normally do not allow steady current to flow, increasing power consumption.

That is, the third clock is connected to the input terminal of the ratioless circuit driven by the one-phase clock
Consider the operation when an asynchronous input signal is applied to the clock φ, as shown by the input signal iNa in the figure. While the clock φ is at the "high" level, the output terminal is precharged to the power supply -V, and an output signal outa at the -V level is formed. When the input signal iNa is applied after being precharged and changes from "high" to "low" level within the period when clock φ is "low" level, the input signal iNa changes from "high" to "low" level.
The P-channel MOS transistor to which iNa is applied turns on, and the ground side P, which is already in the on state,
The precharged charges are discharged to the output terminal via the channel MOS transistor. At this time, the level of input signal iNa becomes “low” in the middle of clock φ.
As the level changes, the period during which the precharged charges can be discharged becomes shorter, and the discharge ends insufficiently.Also, the input signal iNa is discharged through the P-channel MOS transistor, that is, the logic circuit part, so that it becomes stable. Output signal that takes time to reach the level and is derived to the output terminal
The power supply as shown in Figure 3 as outa.
A signal having an intermediate level between V and ground level is output. If such an intermediate level signal outa is applied to an inverter or the like in the next stage, it may cause malfunction.

In addition, the logic circuit provided in the ratioless circuit is
Unlike the circuit made up of one P-channel MOS transistor shown in Fig. 1, when the circuit is made up of logic blocks with a large number of vertically stacked stages as shown in Fig. 2, an intermediate level signal is output. Not only is it not possible to obtain accurate signals, but there are also problems in terms of operating speed. It is difficult to process asynchronous input signals with a ratioless circuit, and the number of vertically stacked logic circuits is limited, which limits the freedom of logic configuration. The degree decreases,
The drawback was that the circuit configuration was difficult.

The present invention eliminates the drawbacks of the conventional circuit described above and provides a logic circuit which is capable of amplifying the level of an output signal to become constant by adding a simple structure. Next, the present invention will be explained in detail with reference to Examples.

FIG. 4 is a one-phase ratioless circuit diagram showing an example of the basic circuit of the present invention. N-channel MOS with clock φ applied to the gate between power supply -V and ground potential
A ratioless circuit is constructed by providing a transistor _T1 and a P-channel MOS transistor _T2 , and further providing a logic section L in which a P-channel MOS transistor is appropriately connected between both transistors. In the logic circuit according to the present invention, a P-channel MOS transistor _T3 that bypasses the logic section L is provided in the ratioless circuit, and an inverted signal obtained by inverting the output signal of the ratioless circuit by an inverter I is supplied to the gate of the transistor _T3 . It is given. FIG. 5 shows the logic part L of the basic circuit example described above, which is connected to P to which the input signal iNc is applied.
A specific example of a ratioless circuit composed of one channel MOS transistor _T4 is shown, and the input terminal A of the inverter I or the output terminal B of the inverter I is connected to the bypass P channel MOS transistor _T3 .
An output signal is derived from . In this circuit, an input signal iNc asynchronous to clock φ is applied to the gate of transistor _T4 as shown in the signal waveform diagram of FIG. is precharged to the -V level, and then even if the clock φ transitions to the "low" level, the precharged state at point A is maintained unless the transistor _T4 is turned on. Clock φ “low”
When the input signal iNc changes from "high" to "low" level in the middle of the level period, the precharged charges at point A are discharged and the level changes from "low" to "high". As point A changes to "high" level, point B via inverter I changes from "high" to "low" level, turning on transistor _T3 , accelerating precharging at point A, and lowering the level. Amplify steady state. In other words, by feeding back the obtained inverted signal to point B and bypassing the discharge of the precharge charge at point A, a situation occurs in which the level at point A reaches a steady level in a short period of time and an intermediate level is output. It is possible to prevent this and form a stable ratioless circuit output.

Figure 6 shows a ratioless circuit in which the logic section L is composed of a plurality of P-channel MOS transistors connected in series.
T ₃ is provided, and the inverted signal D of the output signal C of the ratioless circuit is applied to the gate of the transistor. As the output point C of the ratioless circuit changes from "low" to "high" level during the evaluation period, point D changes from "high" to "low" level and turns on transistor _T3 . The charge precharged at point C is also discharged through transistor _T3 , and the transition time from "low" to "high" level is significantly shortened, speeding up the operation and stabilizing the level.

The present invention is not limited to the above embodiments,
If it is a CMOS structure, the P channel shown in Figure 4
It is also possible to use a MOS transistor and an N-channel MOS transistor that are reversed.
A similar configuration can be achieved with a single channel LSI of a MOS transistor LSI.

As described above, according to the present invention, it is possible to quickly stabilize the level of the output signal of a ratioless circuit to a "low" or "high" level, and it is possible to process asynchronous input signals, which has been difficult with conventional circuits. As a result, the range of use of ratioless circuits can be further expanded.

[Brief explanation of drawings]

1 and 2 are electric circuit diagrams showing a conventional ratioless circuit, FIG. 3 is a signal waveform diagram for explaining the operation of the same electric circuit, and FIG. 4 is a circuit block diagram showing the basic configuration according to the present invention. , FIG. 5 and FIG. 6 are electric circuit diagrams showing an embodiment of the present invention, and FIG. 7 is a signal waveform diagram for explaining the operation of the electric circuit. T ₁ , T ₂ , T ₃ ... MOS transistor, L ... logic section, A, C ... ratioless circuit output terminal,
B, D...Inverted signal output terminal of ratioless circuit output signal, I...Inverter.

Claims (1)

[Claims] 1. A first transistor that is turned on during a first period and charges an output point to a first potential, a logic section whose one end is connected to the output point, and the other end of the logic section. A ratioless circuit is connected in parallel with the logic section and is connected to the potential of the output point, and a second transistor is connected to the second potential and is turned on during the second period following the first period. Therefore, the transistor is controlled to be turned on and off, and turns on in response to the transition of the logic section to the on state during the second period, which is the output determination period, and forms a discharge path parallel to the logic section. A logic circuit characterized in that a logic section bypass transistor is provided.