JPH03263330A - Semiconductor device - Google Patents

Abstract

PURPOSE:To easily form a contact part even when the interval between gate electrodes is small, by forming a first conducting layer, via a second insulating film, on the side wall part and the upper part of the gate electrode and forming at least the end portion of a second conducting layer, via a third insulating film, on the first conducting layer. CONSTITUTION:Gate electrodes 3a, 3b, 3c are formed, via a first insulating film 14, on element isolation regions 2a, 2b and between impurity regions 5a, 7a and impurity regions 5b, 7b on a semiconductor substrate 1. A first conducting layer 8c is connected with the one side impurity regions 5a, 7a of a second conductivity type formed between the element isolation regions 2a, 2b on a semiconductor substrate 1 of a first conductivity type, and formed, via second insulating films 6a, 6b, 4a, 4b, on the side wall part and the upper part of the gate electrodes 3a, 3b. A second conduction layer 11 is connected with the other side impurity regions 5a, 7b, and the end portion of the layer 11 is formed on the first conducting layer 8c, via third insulating films 9, 10b. A second wiring layer 13b is connected with the second conducting layer 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and in particular, at least two second conductive devices separated by a predetermined distance between element isolation regions on a semiconductor substrate of a first conductive type. The present invention relates to a semiconductor device in which a type impurity region is formed.

[Prior Art] Conventionally, a semiconductor device is known in which two impurity regions are formed at a predetermined distance between element isolation regions on a semiconductor substrate. A wiring layer is connected to the impurity region. As a structure of a contact portion where the wiring layer and the impurity region are in contact, a structure in which a conductive layer is formed between the wiring layer and the impurity region is known.

FIG. 2 is a sectional view showing a contact structure of a conventional semiconductor device. Referring to FIG. 2, the semiconductor device includes a semiconductor substrate 1 and an element isolation 2.2 for isolating elements formed on the semiconductor substrate 1. impurity injection layers 5a, 7a and 5b, 7b formed directly on the element isolations 2a and 2b and formed at predetermined intervals in a region surrounded by the element isolations 2a and 2b. Injection layer 5a,
Gate electrodes 3a, 3b, 3c formed between gate insulating film 14 between 7a, 5b, 7b, and sidewalls 6a, 6b, 5c formed on sidewalls of gate electrodes 3a, 3b, 3c, An insulating film 4a formed on gate electrodes 3a, 3b, and 3c.

4b, 4c, and a polysilicon pad 8a made of an electrode material connected to the impurity injection layers 5a, 7a and formed on the side walls and upper part of the gate electrodes 3a, 3b via sidewalls 6a, 6b and insulating films 4a, 4b. and polysilicon pads 8b connected to the impurity injection layers 5b, 7b and formed on the sidewalls and upper portions of the gate electrodes 3b, 3c via sidewalls 6b, 6c and insulating films 4b, 4C.
Contact holes 15a and 15 are formed on the entire surface of the semiconductor substrate 1, and are formed on the polysilicon pads 8a and 8b.
A polysilicon pad 8 is formed on the interlayer insulating film 12 on which b is formed, and on the interlayer insulating film 12 and in the contact hole 15a.
The upper layer wiring 13a is formed to be in contact with the polysilicon pad 8b, and the upper layer wiring 13b is formed on the interlayer insulating film 12 and in the contact hole 15b so as to be in contact with the polysilicon pad 8b.

In this way, conventionally, upper layer wiring 1:3a, 13b,
Polysilicon pads 8a, 8b were formed between impurity implantation layers 5a, 7a, 5b, 7b. By forming these polysilicon pads 8a and 8b, the upper layer wiring 1
The process of forming 3a and 13b was simplified, and the difficulties in the manufacturing process were solved.

Next, a method for manufacturing the semiconductor device shown in FIG. 2 will be explained. First, the element isolation 2a is selectively placed on the semiconductor substrate 1.
2b is formed. Then, a gate insulating film 14 is formed by thermal oxidation.

An electrode material such as polysilicon doped with impurities is deposited on the gate insulating film 14 . Furthermore, an insulating film such as a silicon oxide film is deposited thereon. Among the electrode materials and insulating film, the gate electrode 3a.

Portions other than those where 3b and 3c are formed are removed using photolithography and etching. Ions having a conductivity type opposite to that of the semiconductor substrate 1 are implanted into the semiconductor substrate 1. As a result, impurity injection layer 5a5b is first formed. and,
A sidewall 6a is formed by depositing an insulating film such as a silicon oxide film on the entire surface of the semiconductor substrate 1 and performing etchback.

6b and 6c are formed. Thereafter, ions of a conductivity type opposite to that of the semiconductor substrate 1 are implanted between adjacent gate electrodes on the semiconductor substrate 1. As a result, impurity injection layers 7a and 7b are formed. Impurity implantation layers 5a, 7a and 5b, 7b
A conductive material is formed thereon and polysilicon pads 8a, 8b are patterned. An interlayer insulating film 12 is deposited over the entire surface to form contact holes 15a and 15b.

On the interlayer insulating film 12 and the contact hole 15a.

Upper layer interconnections 13a and 13b are formed in 15b, respectively.

[Problems to be Solved by the Invention] As described above, conventionally, polysilicon pads 8a and 8b are interposed between upper layer wirings 13a and 13b and impurity injection layers 5a, 7a, 5b, and 7b, respectively. Therefore, the upper layer wiring 13a.

This facilitated the formation of 13b. However, as semiconductor devices become more integrated and the elements become smaller, the length of the gate electrode itself becomes shorter and the distance between adjacent gate electrodes becomes smaller. Under such circumstances, a disadvantage arises in that it becomes difficult to photolithographically etch the polysilicon pads 8a, 8b on the gate electrode 3b as in the conventional method. Therefore, there is a problem in that it becomes difficult to form polysilicon pads as devices become smaller. Furthermore, even if it is possible to form a polysilicon pad when the device is miniaturized, it is difficult to accurately form the upper layer wiring on the polysilicon pad, and some of the upper layer wiring may In some cases, the gate electrode is formed directly on the gate electrode, resulting in a short circuit between the upper layer wiring and the gate electrode. Furthermore, if a silicon pad cannot be formed, it is necessary to reduce the contact diameter of the contact hole itself, which poses the problem of making it difficult to perform photolithography and etching to form the contact hole. .

In other words, in the past, when elements became smaller with the integration of semiconductor devices and the distance between adjacent gate electrodes became smaller, polysilicon pads were used as a conductive layer between the wiring layer and the impurity region. There was a problem in that it was difficult to form a contact portion, and as a result, it was difficult to form a contact portion.

This invention was made to solve the above-mentioned problems, and even when the distance between adjacent gate electrodes becomes smaller due to the integration of semiconductor devices, the connection between the impurity region and the wiring layer can be improved. An object of the present invention is to provide a semiconductor device in which a contact portion can be easily formed by forming a conductive layer therebetween.

[Means for Solving the Problems] A semiconductor device according to the present invention includes a plurality of gate electrodes formed on an element isolation region and between impurity regions on a semiconductor substrate with a first insulating film interposed therebetween; Connected to one impurity region of at least two second conductivity type impurity regions formed at a predetermined interval between element isolation regions of a first conductivity type semiconductor substrate; A first conductive layer formed through a second insulating film is connected to the other impurity region of at least two second conductivity type impurity regions, and at least an end thereof is on the first conductive layer. A second insulating film formed through a third insulating film.
, a first wiring layer connected to the first conductive layer, and a second wiring layer connected to the second conductive layer.

[Function] In the semiconductor device according to the present invention, a plurality of gate electrodes are formed on the element isolation region and between impurity regions on the semiconductor substrate with the first insulating film interposed therebetween. is connected to one impurity region of at least two second conductivity type impurity regions and is formed on the sidewalls and upper part of the gate electrode via a second insulating film, and the second conductive layer is connected to at least one impurity region of the second conductivity type. The first wiring layer is connected to the other impurity region of the two second conductivity type impurity regions, and at least its end portion is formed on the first conductive layer via a third insulating film, and the first wiring layer is connected to the other impurity region of the second conductivity type. A second wiring layer is connected to the second conductive layer.

That is, the first conductive layer is formed on the sidewalls and upper part of the gate electrode with the second insulating film interposed therebetween, and at least the end portion of the second conductive layer is formed with the third insulating film on the first conductive layer. Since the conductive layer is formed through the impurity region and the wiring layer, even if the distance between adjacent gate electrodes becomes small, a conductive layer can be formed between the impurity region and the wiring layer.

[Embodiment of the Invention] FIG. 1 is a cross-sectional view for explaining a contact structure of a semiconductor device showing an embodiment of the invention.

Referring to FIG. 1, the semiconductor device includes a semiconductor substrate 1, element isolations 2a and 2b for isolating elements formed on the semiconductor substrate 1, and element isolations 2a and 2b on the semiconductor substrate 1.
impurity implantation layers 5a, 7a and 5b, 7b formed at predetermined intervals in a region surrounded by A gate electrode 3 formed between 5b and 7b with a gate insulating film 14 interposed therebetween.
a, 3b, 3c, and sidewalls 6a, 6b, 6 formed on the sidewalls of the gate electrodes 3a, 3b, 3c, respectively.
c, insulating films 4a, 4b, 4c formed on gate electrodes 3a, 3b, 3c, respectively, and impurity implantation layers 5a, 7.
a and a polysilicon pad 8c formed on the sidewalls 6a and 6b of the gate electrodes 3a and 3b and the insulating films 4a and 4b, and sidewalls 10a and 10b formed on the sidewalls of the polysilicon pad 8c. , connected to the insulating film formed on the polysilicon pad 8c and the impurity injection layers 5b, 7b, formed on the sidewalls 6b, 6c of the gate electrodes 3b, 3c and the insulating films 4b, 4c, and connected to the polysilicon pad 8c. A polysilicon pad 11 formed on the insulating film 9 and a sidewall 10b, and an insulating film 9 on the polysilicon pad 8C.
and a contact hole 15a provided in the insulating film 12, a contact hole 15b provided in the insulating film 12 on the polysilicon pad 11, and a contact hole 15b provided in the insulating film 12 on the contact hole 15a and the insulating film 12 so as to be in contact with the polysilicon pad 8c. Upper layer wiring 13 formed in
a, and a contact hole 15b and an upper layer wiring 13b formed on the insulating film 12 so as to be in contact with the polysilicon pad 11.

In this embodiment, the structure in which the polysilicon pads 8C and the polysilicon pads 11 are stacked allows the gate electrode length and the gate electrode spacing to be reduced due to the miniaturization of elements as semiconductor devices become more integrated. Even if the impurity implantation layer 5a is shortened, the impurity implantation layer 5a can be formed without any difficulty in manufacturing.
, 7a and 5b, 7b and upper wiring layers 13a and 13
Polysilicon pads 8c and 11 can be formed between the wafers 8c and 11b, respectively. As a result, the upper layer wiring 13a.

Contact hole 15a for forming contact hole 13b.

15b becomes easier to form. That is, even if the element is miniaturized, the contact hole 15a.

The dimensional accuracy of the contact holes 1.5a and 15b is not strictly required, and the inner diameters of the contact holes 1.5a and 15b themselves can be increased. Therefore, it is possible to solve the difficulties in manufacturing methods associated with miniaturization of elements in the contact portion, and it is possible to increase the yield during manufacturing.

Next, a manufacturing process for forming the contact structure of the semiconductor device shown in FIG. 1 will be described. First, element isolations 2a and 2b are selectively formed on a semiconductor substrate 1. Then, by performing thermal oxidation, the gate insulating film 14 is
An electrode material such as impurity-doped polysilicon is then deposited thereon. An insulating film such as a silicon oxide film is deposited on the electrode material. Finally, regions other than those where gate electrodes 3a, 3b, and 3c will be formed are patterned and removed by photolithography and etching. Next, ions of a conductivity type opposite to that of the semiconductor substrate 1 are implanted onto the semiconductor substrate 1 . As a result, first, the impurity implantation layer 5
a, 5b are formed.

An insulating film such as a silicon oxide film is deposited over the entire surface of the semiconductor substrate 1. Sidewalls 6a, 6b, and 6C are formed by etching back the deposited insulating film. Then, ions of a conductivity type opposite to that of the semiconductor substrate 1 are implanted onto the semiconductor substrate 1 . As a result, the impurity implanted layer 7.
11, 7b are formed.

After depositing a conductive material such as polysilicon over the entire surface, an insulating film such as a silicon oxide film is deposited. Then, using photolithography and etching techniques, polysilicon pads 8c are formed connected to impurity injection layers 5a and 7a and riding on gate electrodes 3a and 3b. Then, an insulating film such as a silicon oxide film is deposited on the entire surface and etched back to form sidewalls 10a and 10b on the sidewalls of the polysilicon pad 8C. A conductive material such as polysilicon is then deposited over the entire surface. Using photolithography and etching techniques, a polysilicon pad 11 is connected to the impurity injection layers 5b and 7b and placed on the gate electrodes 3b and 3c, and is formed on the polysilicon pad 8C with an insulating film 9 interposed therebetween. Form.

3. Thereafter, interlayer insulating film 12 is deposited to form contact holes 15a and 15b on polysilicon pads 8C and 11. Contact hole 15a.

Upper layer wirings 13a and 13b are formed on 1.5b, respectively. As a result, the impurity implantation layers 5a and 7a and the upper layer wiring 13
a is connected by a polysilicon pad 8C, and the impurity injection layers 5b, 7b and upper layer wiring 13b are connected by a polysilicon pad 11. In this embodiment, a polysilicon pad is formed as a contact method between the impurity implantation layer and the upper wiring, but the present invention is not limited to this. It is also applicable to Further, in this embodiment, polysilicon doped with impurities was used as the material for the gate electrode, but the present invention is not limited to this, and the present invention is not limited to this. It's okay. Further, in this embodiment, a polysilicon pad made of polysilicon or the like is shown as an example of the electrode material, but the present invention is not limited to this, and any material having electrical conductivity may be used.

[Effects of the Invention] As described above, according to the present invention, the first conductive layer is formed on the sidewalls and the upper part of the gate electrode with the second insulating film interposed therebetween, and the first conductive layer is formed on at least the end portion of the second conductive layer. By forming the conductive layer on the first conductive layer via the third insulating film, a conductive layer can be formed between the impurity region and the wiring layer even when the distance between adjacent gate electrodes is small. Therefore, even if the distance between gate electrodes becomes smaller as semiconductor devices become more integrated, the contact portion can be easily formed.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining a contact structure of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a contact structure of a conventional semiconductor device. In the figure, 1 is a semiconductor substrate, 3a, 3b, 3C are gate electrodes, 4a, 4b, 4c are insulating films, 6a, 6b, 6c
is a side wall, 8C is a polysilicon pad, 9 is an insulating film, 1.0a, 10b is a side wall, 11 is a polysilicon pad, 13a, 13b
is an upper layer wiring, and 15a and 15b are contact holes. In each figure, the same reference numerals indicate the same or corresponding parts. 6 1 Figure 1゜Display of the case 2゜Person who amends the name of the inventionRelationship with the caseAddress NameRepresentative 4, Agent Address Procedure Amendment (Voluntary) May 27, 1991 1990 Patent Application No. No. 63671' Semiconductor device

Claims (1)

[Claims] A semiconductor device in which at least two impurity regions of a second conductivity type are formed at a predetermined distance between an element isolation region on a semiconductor substrate of a first conductivity type, the impurity regions being formed on the element isolation region and a plurality of gate electrodes formed between the impurity regions on the semiconductor substrate via a first insulating film; and connected to one of the at least two impurity regions of the second conductivity type; A first conductive layer formed on the sidewalls and upper part of the gate electrode via a second insulating film, and connected to the other of the at least two impurity regions of the second conductivity type; a second conductive layer whose end portion is formed on the first conductive layer via a third insulating film; a first wiring layer connected to the first conductive layer; a second wiring layer connected to a conductive layer.