JPH0326843B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Example (a) One Implementation Explanation of the configuration of the example device (Figures 2 and 3)
(Figure 4) (b) Explanation of the internal configuration of one embodiment (Figure 5) (c) Explanation of the operation of the configuration of one embodiment (Figure 6) Effects of the invention [Summary] This is a sleep mode control method that suspends access, and includes a timer that is activated when the processor enters sleep mode, and an interrupt caused by the timer counting a certain period of time to exit sleep mode and access the input unit. By doing so, it is possible to escape from sleep mode without any special operation and to efficiently save power.

[Industrial application field]

The present invention relates to a processor sleep mode control method for controlling the sleep mode of a processor, and more particularly to a processor sleep mode control method that allows the processor to enter sleep mode while waiting for an input to save power consumption.

In general, in data processing equipment, the processor (hereinafter referred to as CPU) is always running with the power on, and is connected to the bus by I/O (input/output).
It monitors the status of the unit and, if requested, takes action accordingly.

The CPU constantly accesses the I/O unit by changing the state of the signals on the bus, so the CPU, I/O unit connected to the bus
Current flows through the unit's driver, receiver, etc., consuming power.

Therefore, if you stop CPU access when there is no request from the I/O unit,
It is possible to reduce power consumption, which is important from the viewpoint of effectively using limited power, especially in battery-powered devices.

[Conventional technology]

Generally, in a data processing device, FIG.
As shown in the configuration diagram, there is a CPU 1 and a read-only memory (hereinafter referred to as ROM) for storing programs.
6, a random access memory (hereinafter referred to as RAM) 2 for holding data input, an input section 3 such as a keyboard, and an I/O unit 5,
These are connected by a data bus 4b, an address bus 4a, and a control bus 4c, and interrupt signals, timing signals, chip select signals, etc. are exchanged via the control bus 4c.

The CPU 1 reads the program in the ROM 6, analyzes and executes commands, but a sleep instruction is stored in the ROM 6, so when it is waiting for an input, the input section 3, which is an input unit, and the I/O
A sleep mode is entered in which access to unit 5 is stopped.

In conventional sleep mode control, the seventh
As shown in the processing flow diagram in Figure B, if there is no input or processing for a certain period of time as a result of access to the input units 3 and 5, the CPU 1 enters sleep mode (state) by a sleep command, and stops accessing the input units 3 and 5. It has been canceled. On the other hand, input unit 3,
5 has interrupt units 3a and 5a, and when there is a processing request, the interrupt units 3a and 5a issue an interrupt signal to the control bus 4c and give it to the CPU 1, which causes the CPU 1 to escape from sleep mode and transfer the interrupt signal to the data bus 4c. 4
b, input units 3, 5 via address bus 4a;
access and make that request one after another, execute the corresponding job, and after the job is finished, input again for a certain period of time,
When there is no processing, it goes into sleep mode.

Therefore, when there is no request from the input units 3, 5, access via the buses 4a, 4b is not executed, so the bus driver and receiver do not operate, and power consumption can be reduced.

Also, as seen in Japanese Patent Application Laid-open No. 59-79325, etc.
A control method has also been proposed in which the device returns to the normal mode at regular intervals using a clock, accesses the input unit, and enters the standby mode if there is no request.

[Problem that the invention seeks to solve]

However, in the former conventional sleep mode control method, a special operation of interrupting the input units 3 and 5 is required in order for the CPU 1 to escape from the sleep mode.

Therefore, each input unit 3, 5 has an interrupt section 3.
There is a problem in that the number of input units increases when various input units such as keyboards, external devices, displays, etc. (not shown in the figure) are present, which causes an increase in costs. or,
In order to perform an interrupt, a special operation for that purpose is required in the input unit, which also poses a problem of requiring time and effort.

In addition, in the latter conventional technology, an interrupt by the input unit is not required, but since the normal mode is returned to the normal mode at regular intervals by the clock, regardless of the operation of the processor, when a request is received from the input unit, the processor only during the time that is being processed.
There was a problem in that the standby time was reduced and the period until the next normal mode returned was shortened, reducing the power saving effect by half.

In view of the above points, it is an object of the present invention to provide a processor sleep mode control method that allows the CPU to escape from the sleep mode without operating a special input unit and efficiently reduces power consumption. purpose.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

The present invention comprises a processor 1 that executes a normal mode and a sleeve mode, a timer 7 that is activated by an instruction from the processor 1, an input unit 3 connected to the processor 1 and accessed by the processor 1, 5, the processor 1 executes a job in response to a request from the input units 3 and 5 when there is no request from the input units 3 and 5 as a result of access to the input units 3 and 5. , enters the sleeve mode in which the access is stopped, and starts the timer 7, and in response to an interrupt generated by the timer 7 counting a certain period of time, the processor 1 exits the sleeve mode and starts the input unit 3, 5.

[Effect]

In the present invention, the input unit 3,
As a result of accessing 5, if it is determined that there is no request,
After processing this request, the system enters the sleep mode and starts the timer 7 as shown in Figure 1.The timer 7 measures a certain period of time as shown in the figure, exits the sleep mode, and returns to the normal mode. Certain input units 3 and 5 are accessed.

Therefore, in input units 3 and 5,
A special operation for escaping the CPU 1 from sleep mode is no longer necessary, and an interrupt section for escaping does not need to be provided in each input unit 3, 5.

Furthermore, when there is no request from the input units 3 and 5 or when a job is executed in response to a request from the input units 3 and 5, the input unit 3 enters a sleep mode in which access is stopped and starts the timer 7. , 5 and regardless of the processing time of the request, the sleep mode can be executed for a certain period of time determined by the timer, and sufficient power can be saved.

〔Example〕

(a) Description of the configuration of the device of one embodiment.

FIG. 2 is an external view of a data input device as an embodiment of the present invention, indicating a portable terminal, and FIG. 3 is an explanatory diagram of an example of use of the data input device configured in FIG. 2. It is.

In the figure, PT is a handheld terminal (data input device) that is held in the hand of the operator to perform operations such as inputting data. and,
The BD is the main unit, and the SW is the power switch, which is provided on the top of the main body BD and turns on/off the power. 3 is the key section as the aforementioned data input section, which has keys arranged in 7 rows and 5 columns, including numeric keys "0" to "9" and an input instruction key "ENTER".
In addition to the necessary alphanumeric keys and function keys, enter general data using the numeric keypad and alphanumeric keys, then press "ENTER".
Functions using keys and function keys (processing details)
5 is a display (I/O unit), which is composed of a liquid crystal display and is installed on the top of the main body BD to display input data, etc. 8 is a connector, which is used to input data to the main body BD. It is provided on the side and is used to connect with external equipment such as a communication unit or printer unit to exchange data and commands, and will be described later with reference to FIG. 4A.

In FIG. 3, CIU is a communication interface unit, which has a housing section for housing the handheld terminal PT, and a connector 9 connected to the connector 8 of the handheld terminal PT at the bottom.
(described later in FIG. 4B), and when the handheld terminal PT is accommodated in the housing part as shown in FIG. 3, the connectors 8 and 9 are connected, and the input data in the memory 2 of the handheld terminal PT is is sent to the host computer.

To explain an example of how such a handheld terminal PT is used, an operator holds the handheld terminal PT in his hand at a business partner (supermarket, etc.) and while checking the product, inputs the product type, quantity, etc. by operating the key part 3. and confirm the input data on the display 5. The input data is
Processed by CPU 1 and stored in memory 2.

Then, the operator connects the handheld terminal PT to, for example, a printer device (not shown) loaded in the vehicle, issues a slip, and hands it to the business partner. Furthermore, when the user returns to his/her office, the handheld terminal PT is connected to the communication interface unit CIU installed in the office, and the input data is sent to the host computer for purposes such as sales aggregation.

Figure 4 shows these handheld terminals PT.
FIG. 2 is a configuration diagram of connectors 8 and 9 provided in the communication interface unit CIU.

In FIG. 4A, 80a and 80b are guide holes for receiving alignment studs, which will be described later, on the other connector 9 provided on the communication interface unit CIU, and 81a to 81d are holes for lead terminals. 82 is an optical connection part, which receives the signal line pins (to be described later) of the other connector 9, respectively, and makes an electrical connection of the signal line, and includes three light emitting elements (light emitting diodes) 83,
It is composed of six light-receiving elements (phototransistors) 84, and exchanges signals by optical coupling while facing the six light-emitting elements and three light-receiving elements of the other connector 9, which will be described later. 85 is a connector support part. Guide holes 80a and 80b, lead terminal holes 81a to 81d, and an optical connection section 82 are provided.

In FIG. 4B, 90a and 90b are alignment studs, which are inserted into the guide holes 80a and 80b of one connector 8 of the handheld terminal PT to hold and align the connectors 8 and 9 when they are connected. 91a to 91d are pins for signal lines, and holes 81a for lead terminals of one connector 8.
~ 81d to electrically connect the signal line, 92 is an optical connection part, which is composed of six light emitting elements (light emitting diodes) 93 and three light receiving elements (phototransistors) 94, When connecting with one connector 8, each connector 6 of one connector 8
one that faces one light receiving element 84 and three light emitting elements 83 and exchanges signals by optical coupling;
Reference numeral 95 denotes a connector support section, which includes positioning studs 90a, 90b and signal line pins 91a to 91.
d. An optical connection section 92 is provided.

To connect the connectors 8 and 9, the handheld terminal PT is inserted into the communication interface unit CIU so that the alignment studs 90a, 90b of the connector 9 are inserted into the guide holes 80a, 80b of the connector 8.

As a result, the signal line pin 91a of the connector 9
~91d is the lead terminal hole 81a of the connector 8~
81d, an electrical connection is made, and the optical connection part 92 of the connector 9 and the optical connection part 82 of the connector 8 face each other, and the light emitting element 93 connects to the light receiving element 84, and the light receiving element 94 connects to the light emitting element 81d. Opposing the element 83, optical coupling is possible.

In connectors using such optical coupling, signal lines for power supply, connection detection, and signal ground that are unsuitable for optical coupling are connected to the signal line pin 91.
This is done by electrically connecting a to 91d and the lead terminal holes 81a to 81d. On the other hand, data lines, clock lines, etc. that can be optically coupled are optically coupled between optical connections 92 and 82. Optical coupling allows for highly reliable connections as there is no need to consider connection failures due to pin wear and deterioration, compared to electrical tangents produced by mechanical connections.In addition, the connections are electrically isolated and the terminals are not exposed. This prevents damage to internal circuits caused by static electricity.

(b) Description of the internal configuration of one embodiment.

FIG. 5 is an internal block diagram of one embodiment of the present invention.

In the figure, the same parts as those shown in FIGS. 1, 2, and 4 are indicated by the same symbols, and 10 is an interface circuit that connects external equipment with the RS-232c interface via the connector 8. 11 is a battery that supplies the operating voltage Vcc inside the device, and when connected to the communication unit CIU, the communication unit CIU
A charging voltage BV is applied from the power supply to the connector 8 via the pin 91c of the connector 9 to charge the battery, and during charging, an operating voltage Vcc is similarly applied to each part from the power supply via the pin 91d of the connector 9. 30, 50, and 70 are ports, which are composed of input/output registers, and port 30 is the key part 3.
port 50 is for display 5, port 70 is for interface circuit 1
0 and a buzzer, 51 is a display controller that controls the screen of the display 5, and 52 is a display buffer (hereinafter referred to as buffer) that stores data to be displayed. , 71 is a buzzer for issuing an alarm.

The basic operation of a data input device with such a configuration is as follows:
The CPU 1 sequentially sends the input contents of the key section 3 from the address bus 4a to the data bus 4b via the port 30, decodes the input contents, and performs job processing (for example, arithmetic processing such as addition/subtraction, multiplication, division, etc.) and search processing. ), the instructed processing is executed, and if it is general data, the data related to the display buffer 52 and data storage memory 2 is provided via the address bus 4a and stored therein. Further, the display controller 51 accesses the display buffer 52 via the address bus 4a in DMA mode via the port 50, and accesses the display buffer 52 via the data bus 4a.
It receives display data from b and displays it on the display 5. These programs are read and executed by the CPU 1 from the ROM 6. In addition, in the transmit/receive mode, CPU1 receives port 70 from address bus 4a.
is specified, data is exchanged with the interface circuit 10, and data is transmitted and received with external equipment via the connector 8.

(c) Description of operation of one embodiment configuration.

Next, the sleep mode control operation will be explained using the sleep mode control processing flow diagram in the configuration shown in FIG. 5 in FIG.

Upon completion of the job, the CPU 1 enters the sleep state in response to a sleeve command from the ROM 6, and also activates the timer 7 via the control bus 4c. In this sleeve state, the CPU 1 uses buses 4a, 4b,
Access to ports etc. connected from 4c is stopped.

Timer 7 counts the clocks by this activation, and after counting the clock for a certain period of time (for example, 100ms),
An interrupt is made to the CPU 1 via the control bus 4c.

The CPU 1 escapes from the sleep mode by this interrupt and enters the normal mode, and as explained above in the basic operation, each port 70, 50, 30 connected to the input unit is connected to the address bus 4.
The input data is sequentially specified via the data bus 4b, and the presence or absence of input data is received via the data bus 4b to determine the presence or absence of the input data.

For example, to access port 30 of key section 3, CPU 1 receives the output of each row of key section 3 as data from port 30, checks whether or not it has been pressed, and if so, the position in the key section, and which key It is determined whether the key is pressed, and if it is not pressed, there is no key input.

If there is no input, the process returns to step and enters sleep mode.

On the other hand, if there is input data, the corresponding job processing is executed, and after executing the job, the process returns to step and enters sleep mode.

In this way, the device exits from the sleep mode by the interrupt of the timer 7, accesses the port, and if there is no input data, enters the sleep mode again, and if there is input data, enters the sleep mode after completing the job.

In such a data input device, there is no need to operate the key unit 3 to raise an interrupt in order to escape from sleep mode, and there is no need to raise an interrupt from the communication unit CIU when connecting with the communication unit CIU. Operation is simplified, and there is no need to provide an escape switch or interrupt circuit in the key unit 3 or the communication unit CIU.

In the above-mentioned embodiment, the handheld terminal is used as an example, but the input unit is not limited to the keyboard 3, the interface 10, and the display 5, but may also include a barcode reader,
Other well-known input units such as OCR may also be used.

Although the present invention has been described above using one embodiment, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, since a timer interrupt is used for the CPU to escape from sleep mode, there is no need for a special escape operation, which saves time and effort. . Furthermore, since there is no need to provide an interrupt switch or an interrupt circuit in the input unit, it is possible to reduce costs accordingly.

Furthermore, if there is no request from the input unit or if a job is executed in response to a request from the input unit, the device enters a sleep mode that suspends access and starts the timer, so it is possible to check whether there is a request from the input unit or not and process the request. The sleep mode can be executed for a certain period of time determined by a timer regardless of the time, and there is also the effect that sufficient power saving is possible.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an external view of an embodiment of the present invention, Fig. 3 is an explanatory diagram of an example of use of the embodiment of the present invention, and Fig. 4 is Fig. 2. 5 is an internal block diagram of an embodiment of the configuration in FIG. 2, FIG. 6 is a processing flow diagram of an embodiment of the configuration in FIG. 5, and FIG. 7 is an explanation of the prior art. It is a diagram. In the figure, 1...processor (CPU), 3...key input unit, 7...timer, 10...interface.

Claims (1)

[Claims] 1. A processor that executes a normal mode and a sleep mode, a timer that is activated by instructions from the processor, and an input unit that is connected to and accessed by the processor, As a result of accessing the input unit, if there is no request from the input unit or if the processor executes a job in response to a request from the input unit, the processor enters a sleep mode in which the access is stopped and starts the timer. A sleep mode control method for a processor, characterized in that the processor escapes from the sleep mode and accesses the input unit in response to an interrupt generated when the timer measures a certain period of time.