JPH0326873B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) At present, devices using computers are used for both LSI layout design and post-design artwork data verification. The present invention relates to a system for verifying the layout of an LSI designed using this computer.

(Prior technology) Currently, a computer-based wiring check system has been introduced to check artwork data such as circuit wiring diagrams. The circuit representation restored from the data is often different even though the circuit has the same function.

When performing a wiring check using a computer using a computer to check such differences in circuit representation as the same wiring, the circuit representation in the basic circuit diagram must be partially corrected manually to match the artwork data. In some cases, a wiring check is executed after checking the wiring, or after a wiring check is executed without correction, the true error is manually extracted from the error data output from the computer.

(Problem to be solved by the invention) It requires manual correction and examination before or after execution, which consumes a large amount of man-hours, and is not suitable for large data because it requires such manual man-hours. This is the current situation.

An object of the present invention is to obtain a circuit connection verification system that does not require manual correction or examination.

(Means for solving the problem) According to the present invention, a circuit diagram to be inspected is converted into digital data, and among the converted data, a series circuit or a parallel circuit of a single element is converted into a single element as a whole. A circuit connection verification system is obtained, which is characterized in that the converted data is converted into element data, and the converted data and basic circuit data are compared and inspected.

(Example) In the present invention, when checking artwork data for LSI, the basic circuit diagram is stored electronically (for example, the coordinates of the circuit diagram are read using a digitizer or the like and stored on a disk, etc.). In addition, the circuit data (artwork data) created by the computer to be inspected is also stored electronically, and the continuity inspection is performed by the computer.

FIG. 1 shows a system configuration according to an embodiment of the present invention.

A circuit diagram expressed based on LSI artwork data is input into the system using a digitizer 101. If the artwork data is electronic, it may be input directly into the system. Basic circuit diagram data is input via the workstation 102. The input data is stored in storage media 103 and 104, respectively. The entire system is system controller 1
It is controlled by 05. The plot data after the test is executed under the control of the system controller 105 is plotted on a blotter 106 or output as a list on a printer 107. 108
is a bus line that transfers data electronically; a
is a circuit diagram drawn based on artwork data, b is a circuit diagram depicting the basic circuit,
c and d are plot diagrams and lists output from this system after processing.

A more detailed explanation will be given below based on an example of a bipolar circuit.

Figure 2 is a circuit diagram showing how a resistor is connected. For example, to connect a 10KΩ resistor,
In some cases, only one 10KΩ resistor 1 is connected (Figure a), but depending on the situation, two 5KΩ resistors 2 may be connected in series (Figure b), or two 20KΩ resistors 3 are connected in series. or connect them in parallel (c in the same figure). Since these are completely equivalent in function, by replacing them with one resistor 1', 2', 3', respectively, as shown in FIG. 3 a, b, and c under the control of the system controller 105, Unify circuit representation. A connection test is performed between the data unified in this way and the basic circuit diagram.

FIG. 4 shows the state in which the transistors are connected. In some cases, a single transistor 4 with a large emitter area is used (see figure a), and in some cases, a transistor 5 with a smaller emitter area is used.
Two emitters may be connected in parallel (FIG. 2(b)), or a transistor 6 having two emitters formed in the same base may be used (FIG. 3(c)). In addition, "2" in the figure a indicates the area series of the emitter. These various circuit expressions are made into a unified circuit expression similar to the resistance. There are two ways to achieve this unification. One method is to connect transistors 4' in parallel as shown in FIG. 5A in accordance with the area number added to the transistor 4 in FIG. 4A. The others are transistors 5' and 5', corresponding to the number of terminals that are the largest among the emitter and collector terminals of transistors 5 and 6 in FIG. 4b and c, respectively.
6' are connected in parallel as shown in FIG. 5b and c. Figure 5a, which unified the circuit representation in this way,
Both b and c are the same.

In this way, the circuit representation is unified as a pre-processing of the connection verification process in the circuit connection verification system.
Thereafter, an inspection is performed by comparing the data created based on the basic circuit diagram with the unified circuit representation data. The executed results are printed out on the plot diagram c by the plotter 6 or printed out on the printer 107.
is output to list d.

(Effects of the Invention) The present invention has the advantage that in the conventional circuit connection reference system, input data (artwork data and circuit diagram data)
Previously, the connection expressions were manually unified (modified input data) for output data and output data, but since this manual modification is not required, the work efficiency is significantly improved. Furthermore, since there is no human intervention, the verification results are highly reliable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a system configuration according to an embodiment of the present invention. Figure 2 a, b,
3c is a circuit diagram showing the connection states of the resistors, and FIGS. 3a, b, and c are circuit diagrams that unify the expressions of the resistor connections in FIGS. 2a, b, and c. Figure 4 a, b, c
5A, 5B, and 5C are circuit diagrams showing the connection states of the transistors, respectively, and FIGS. 5A, 5B, and 5C are circuit diagrams in which the transistor connections in FIGS. 1, 2, 3, 1', 2', 3'...Resistance, 4, 5,
6, 4', 5', 6'...transistor, 101...
...Digitizer, 102... Workstation, 103, 104... Storage medium, 1005...
System controller, 106...Protuter, 1
07...Printer, a...Circuit diagram to be inspected, b...
Basic circuit diagram, c...plot diagram, d...list.

Claims (1)

[Claims] 1 Input the basic circuit diagram data and the circuit diagram data of the circuit under test, and from both circuit diagram data, connect the resistors connected in series or parallel and the transistors connected in parallel to a single resistor. Circuit connection verification is characterized in that the circuit diagram data of the circuit to be inspected and the basic circuit diagram data are compared and verified after unifying the circuit representation between the circuit diagram data and the data as a transistor by converting the circuit diagram data into transistor data. system.