JPH0326933B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a signaling frame format conversion circuit having a multi-frame configuration.

(Prior art) In a device in which voice data and signaling data have a frame configuration and multiplex and demultiplex the voice channel and the signaling channel using the same sampling pulse, the voice data VF and the signaling data SIG have the same frame format (Fig. 4 a, b), it is necessary to convert them into a multi-frame configuration (Fig. 5 or 6).

In implementing this, a lot of memory is required for this conversion.

(Problems to be Solved by the Invention) In view of the fact that conventionally, a large number of memories were required when converting a signaling frame format, the present invention provides a simple signaling format conversion circuit that solves the above-mentioned drawbacks. This is what we provide.

(Means for Solving the Problems) The present invention provides an interface between an audio channel having a frame configuration and a signaling channel having a multi-frame configuration, for audio data and signaling data having the same frame format. The signaling frame format conversion circuit extracts the signaling data of the time slot that matches the frame number by matching the count value of the frame counter and the count value of the time slot counter, and extracts the signaling data of the time slot that matches the frame number. This is a signaling frame format conversion circuit characterized by inserting signaling data into a time slot.

(Function) According to the present invention, an extraction pulse for time slot extraction according to the frame number is generated in the signaling frame format conversion circuit,
Signaling data is thereby extracted.

(Embodiment) FIG. 1 is a block diagram for explaining a first embodiment of the present invention.

Signaling data (4th frame format) with the same frame format as audio data (Figure 4a) is input to input terminal 1.
Enter figure b).

Set an appropriate frame as the 0th frame, for example, the 0th frame.
It is provided with a frame counter F_COUNT that cycles and counts up to the 31st frame, and a time slot counter TS_COUNT that cycles and counts from the 0th time slot to the 31st time slot. A coincidence circuit C detects the coincidence between the count value of the frame counter F_COUNT and the count value of the time slot counter TS_COUNT. When the matching circuit C detects a match, a signaling extraction pulse is obtained where the frame number and time slot number match. For example, F0
Pulses such as TS0, TS1 of F1, TS2 of F2, TS3 of F3, etc. are generated.

By calculating the logical product of the signaling extraction pulse and the clock in an AND circuit,
Create a clock that occurs only in the signaling extraction timeslot. When a clock generated only in the signaling extraction time slot is input to the shift register SR1, only the signaling data of the time slot that matches the frame number is taken into the shift register SR1 and stored until the next clock arrives. While the data is stored in the shift register SR1, it is latched as a parallel signal by the latch circuit LATCH. This can be done, for example, by inputting a latch pulse at the beginning of the frame. The latched signaling data is sent to a specific time slot (e.g.
Shift register SR to be inserted into TS 16)
By performing parallel-to-serial conversion in 2,
Signaling data having a multi-frame configuration can be inserted into the specific time slot. In this case, the frame structure shown in FIG. 5 is used.

FIG. 2 is a block diagram for explaining the second embodiment. FIG. 2 shows the inverse transformation of the first embodiment. As in the first embodiment, the matching circuit C obtains a signaling extraction pulse whose frame number and time slot number match, and sends it to the AND circuit. The AND circuit inputs the signaling extraction pulse, the corresponding time slot pulse, and the clock, and outputs the ANDed result to the clock terminal of the flip-flop F/F. In the flip-flop F/F, if the conversion circuit CONV extracts only the data of a specific time slot from the data input from the input terminal 1 and repeatedly sends the data over that frame, the clock from the AND circuit, That is, it operates using a clock generated in a time slot in a section where the frame number and time slot number match. Only the signaling data for the time slot that matches the frame number is obtained from the flip-flop.

FIG. 3 is a block diagram for explaining the third embodiment. The first example and the second example are
Although one time slot corresponds to one frame as shown in FIG. 5, FIG. 3 shows an extraction clock generating section in which one frame corresponds to two time slots as shown in FIG.

The frame counter FCOUNT in Figure 3 counts 16 frames, and the time slot counter
TS COUNT counts 32 time slots. All output terminals of frame counter F COUNT
Q _A , Q _B , Q _C , Q _D (2 ⁰ , 2 ¹ , 2 ² , 2 ³ ) and the output terminals of the time slot counter TS COUNT Q _A , Q _B ,
Q _C and Q _D (2 ⁰ , 2 ¹ , 2 ² , 2 ³ ) are each connected to a matching circuit to detect matching. Therefore, frame number 0 has time slot number 0,16.
But frame number 1 has time slot number 1,17
But..., the time slot number is set to frame number 15.
15 and 31 correspond to each other, and when the count value of the frame counter F_COUNT and the count value of the time slot counter TS_COUNT match, a signaling extraction pulse is obtained. Then, the logical product of this signaling extraction pulse and the clock is
By using an AND circuit, a clock generated only in the signaling extraction time slot is created, and similarly to the first embodiment, a shift register SR1, a latch circuit, and a shift register (not shown) are generated.
Via SR2, signaling data having a multi-frame structure can be inserted into a specific time slot.

(Effects of the Invention) Since the present invention easily creates pulses with different extraction time slots depending on the frame, it is possible to miniaturize the device. Additionally, since memory is not used extensively, data delay is reduced.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a first embodiment of the present invention, FIG. 2 is a block circuit diagram of a second embodiment, FIG. 3 is a block circuit diagram of a third embodiment, and FIG.
FIGS. 5 and 6 are diagrams showing frame configurations. F COUNT……Frame counter, TS
COUNT...Time slot counter, C...Coincidence circuit, AND...AND circuit, SR1, SR2...
Shift register, LATCH...Latch circuit.

Claims (1)

[Scope of Claims] 1. A signal in a frame format for audio data having a plurality of time slots each consisting of a plurality of serial bits and inserting audio data into the plurality of time slots, and a frame for the audio data. A signal of a frame format for signaling data consisting of a plurality of time slots that are the same as the format, and in which signaling data is inserted into the plurality of time slots of the frame format for signaling data. In a signaling frame format conversion circuit that makes the signaling data into a multi-frame configuration by sequentially inserting the received signaling data into specific free time slots of the frame format for the audio data, the audio data counts a plurality of frames. a time slot counter for the signaling data that counts a plurality of time slots, an output of the frame counter and an output of the time slot counter, and checks whether the count values of the respective counters match. an AND circuit that ANDs the output of the coincidence circuit with a clock synchronized with the serial bit, and inputs the output of the AND circuit and a frame format signal for the signaling data;
a storage circuit 1 for extracting and storing signaling data of a time slot number in the signaling data frame that matches the number of the audio data frame; 1. A signaling frame format conversion circuit comprising: a memory circuit 2 capable of reading stored data using a timing signal for insertion into a specific free time slot of a frame format; 2. A signal with a frame format for audio data that has a plurality of time slots each consisting of a plurality of serial bits and inserts audio data into the plurality of time slots, and a signal with a frame format that is the same as the frame format for the audio data. from a signal of a frame format for signaling data formed by inserting signaling data into the time slots, the signaling data inserted into a plurality of time slots of the frame format for signaling data are sequentially processed. In a signaling frame format conversion circuit that makes the signaling data into a multi-frame structure by inserting the frame format into a specific empty time slot of the frame format for the voice data, the frame format for the voice data counts the number of 16 frames each consisting of 4 bits. a time slot counter for the signaling data that counts the number of 32 time slots each consisting of 5 bits; and the same weighting of the frame counter and the time slot counter except for the MSB bit output of the time slot counter. A matching circuit that matches each of the bit outputs of each, and an AND that takes AND of multiple outputs of the matching circuit.
circuit 1; AND circuit 2 which ANDs the output of the AND circuit 1 and a clock synchronized with the serial bit;
and inputting the output of the AND circuit 2 and the signal of the frame format for the signaling data, and extracting the signaling data of the time slot number in the frame for the signaling data that matches the number of the frame for the audio data. a memory circuit 1 for storing data output from the memory circuit 1 and reading the stored data using a timing signal for storing data output from the memory circuit 1 and inserting the data into a specific vacant time slot of the frame format for the audio data; 1. A signaling frame format conversion circuit comprising: a storage circuit 2 that can perform a storage circuit;