JPH0326949B2 - - Google Patents
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- Publication number
- JPH0326949B2 JPH0326949B2 JP59121133A JP12113384A JPH0326949B2 JP H0326949 B2 JPH0326949 B2 JP H0326949B2 JP 59121133 A JP59121133 A JP 59121133A JP 12113384 A JP12113384 A JP 12113384A JP H0326949 B2 JPH0326949 B2 JP H0326949B2
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- Japan
- Prior art keywords
- signal
- circuit
- limiter
- correlation
- output
- Prior art date
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- Television Signal Processing For Recording (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明はノイズリダクシヨン回路に係り、例え
ばVTR等の再生輝度信号のノイズを低減する回
路に用いられ、入力信号に相関がある時のみリミ
ツタの振幅制限動作を解除してノイズを十分に減
算せしめ得、SN比を向上し得る回路を提供する
ことを目的とする。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a noise reduction circuit, and is used, for example, in a circuit for reducing noise in a reproduced luminance signal of a VTR, etc., in which the amplitude of a limiter is reduced only when there is a correlation between input signals. It is an object of the present invention to provide a circuit that can sufficiently subtract noise by canceling the limited operation and improve the signal-to-noise ratio.
従来技術
磁気記録再生装置などにおいて、磁気記録媒体
から再生された映像信号に含まれる記録再生に起
因するノイズを低減するためのノイズリダクシヨ
ン回路が知られている。第7図は従来のノイズリ
ダクシヨン回路の一例のブロツク系統図を示す。
同図中、入力端子1に入来したノイズを含む再生
輝度信号は、1H遅延回路2により1水平走査期
間(1H)遅延され、減算器3において入力端子
1に入来した再生輝度信号から減算される。BACKGROUND ART In magnetic recording and reproducing devices, noise reduction circuits are known for reducing noise caused by recording and reproducing included in video signals reproduced from magnetic recording media. FIG. 7 shows a block system diagram of an example of a conventional noise reduction circuit.
In the figure, the reproduced luminance signal containing noise that has entered input terminal 1 is delayed by one horizontal scanning period (1H) by 1H delay circuit 2, and is subtracted from the reproduced luminance signal that has entered input terminal 1 in subtracter 3. be done.
ここで、再生輝度信号にH相関がある場合、そ
の1Hの時間間隔の映像情報は極めて近似してい
るため、減算器3からは映像情報に関連のないノ
イズが取出される。このノイズはリミツタ4を通
して減算器5に供給されてここでレベル減衰され
た後減算器6に供給され、入力端子1に入来した
再生輝度信号から減算される。この減算により、
ノイズの低減された再生輝度信号が出力端子7よ
り取出される。この従来のノイズリダクシヨン回
路は、3dB程度のSN比の改善が図れる。 Here, if there is an H correlation in the reproduced luminance signal, the video information in the 1H time interval is extremely similar, and therefore, the subtracter 3 extracts noise that is not related to the video information. This noise is supplied to a subtracter 5 through a limiter 4, where its level is attenuated, and then supplied to a subtracter 6, where it is subtracted from the reproduced luminance signal input to the input terminal 1. This subtraction gives us
A reproduced luminance signal with reduced noise is taken out from the output terminal 7. This conventional noise reduction circuit can improve the SN ratio by about 3 dB.
発明が解決しようとする問題点
一般に、輝度信号が黒レベルから白レベルへ立
上る部分又は白レベルから黒レベルへ立下る部分
(エツジ)ではクロストーク等により極めて振幅
の大きいノイズを生じ、第8図に示す如く、減算
器3から取出された信号には、極めて幅が小さ
く、しかもリミツタレベルl(一般には信号成分
のピーク・ピーク値の10%程度)を越える極めて
大きいパルスpを含む。Problems to be Solved by the Invention In general, noise with extremely large amplitude is generated due to crosstalk etc. in the portion (edge) where the luminance signal rises from the black level to the white level or falls from the white level to the black level. As shown in the figure, the signal taken out from the subtracter 3 includes an extremely small pulse p, which is extremely large and exceeds the limiter level l (generally about 10% of the peak-to-peak value of the signal component).
一般に、ライン相関がない場合、端子1に入来
した信号と1H遅延回路2の出力信号とは異なる
ので、減算器3からは両信号の差の信号成分及び
ノイズが取出され、リミツタ4がないと減算器6
において減算器3から取出された信号成分によつ
て端子1に入来した信号が減算されるのでリミツ
タ4が必要である。 Generally, when there is no line correlation, the signal input to terminal 1 and the output signal of 1H delay circuit 2 are different, so the subtracter 3 extracts the signal component and noise of the difference between the two signals, and there is no limiter 4. and subtractor 6
The limiter 4 is necessary because the signal received at the terminal 1 is subtracted by the signal component taken out from the subtracter 3 in the subtracter 3.
従来回路は、ライン相関の有無に無関係にリミ
ツタ4が作動するので、特にライン相関がある場
合でパルスpを生じた場合、パルスpの振幅をリ
ミツタレベルlで制限することによりパルスp全
体を取出し得ず、減算器6においてこのパルスp
を減算し得ないのでエツジにおけるノイズ低減効
果が少なく、エツジにおける画質を損ねる等の問
題点があつた。 In the conventional circuit, the limiter 4 operates regardless of the presence or absence of line correlation, so when a pulse p is generated especially when there is a line correlation, the entire pulse p can be extracted by limiting the amplitude of the pulse p by the limiter level l. First, in the subtracter 6, this pulse p
cannot be subtracted, so there are problems in that the noise reduction effect at the edges is small and the image quality at the edges is degraded.
問題点を解決するための手段及びその作用
本発明は、入力信号の低域成分に相関があるか
否かを検出し、相関があることが検出された時の
みリミツタの振幅制限動作を解除する回路を設け
た構成として上記問題点を解決したものであり、
以下、図面と共にその各実施例について説明す
る。Means for Solving the Problems and Their Effects The present invention detects whether or not there is a correlation between the low-frequency components of the input signal, and cancels the amplitude limiting operation of the limiter only when it is detected that there is a correlation. The above problem is solved as a configuration with a circuit,
Each embodiment will be described below with reference to the drawings.
実施例
第1図は本発明回路の第1実施例のブロツク系
統図を示し、同図中、第7図と同一構成部分には
同一番号を付してその説明を省略する。同図にお
いて、端子1に入来した再生輝度信号をa(第2
図A)とし、1H遅延回路2にて1H遅延された信
号をb(同図B)とする。ここで、信号a,bは
極めて近似した信号であるので減算器3において
信号成分が大武分打消されて信号c(同図C)と
される。信号cはライン相関がないので打消され
なかつた部分で、振幅の大きい部分c1、c2を有す
る。Embodiment FIG. 1 shows a block system diagram of a first embodiment of the circuit of the present invention. In the figure, the same components as those in FIG. 7 are given the same numbers and their explanations will be omitted. In the figure, the reproduced luminance signal input to terminal 1 is a (second
A) in the figure, and a signal delayed by 1H in the 1H delay circuit 2 is denoted by b (B in the figure). Here, since the signals a and b are extremely similar signals, the signal components are canceled by the subtracter 3 to form the signal c (C in the figure). The signal c has large amplitude parts c 1 and c 2 that are not canceled because there is no line correlation.
信号cはアンプ8にて増幅され、リミツタ9
a,9b(後述のリミツタ11においてトランジ
スタx1,x2を省いた回路)にて同図Cに破線で示
すリミツタレベルを以てその振幅を夫々制限され
た後、シユミツトインバータ(図示せず)にて波
形成形されて部分c1の期間Lレベル、それ以外の
期間Hレベルの制御信号(同図D)とされる一
方、シユミツトインバータ(図示せず)にて波形
成形されて部分c2の期間Lレベル、それ以外の期
間Hレベルの制御信号e(同図E)とされ、信号
eはそのまま、信号dはインバータ10で極性反
転されて夫々リミツタ11に供給される。 Signal c is amplified by amplifier 8, and limiter 9
A and 9b (circuits in which transistors x 1 and x 2 are omitted in the limiter 11 to be described later) limit their amplitudes to the limiter levels indicated by broken lines in C in the figure, respectively, and then a Schmitt inverter (not shown) The waveform is shaped into a control signal (D in the same figure) that is at L level during the period of part c 1 and at H level during the other periods, while the waveform is shaped by a Schmitt inverter (not shown) and becomes the control signal during the period of part c 2 . The control signal e (E in the figure) is at L level and at H level for other periods, and the signal e is supplied as is while the signal d is inverted in polarity by the inverter 10 and supplied to the limiter 11, respectively.
なお、減算器3とアンプ8との間に低域フイル
タ15(カツトオフ周波数は例えば1MHz)が設
けられており、パルスpが取出されないようにさ
れている。 Note that a low-pass filter 15 (cutoff frequency is, for example, 1 MHz) is provided between the subtracter 3 and the amplifier 8, so that the pulse p is not extracted.
リミツタ11は第3図に示す構成とされてお
り、端子11aに入来した制御信号dのHレベル
期間にトランジスタx1がオフとされて信号cの部
分c1の振幅を制限すると共に、そのLレベル期間
にトランジスタx1がオンとされて振幅制限動作が
解除され、一方、端子11bに入来した制御信号
eのLレベル期間にトランジスタx2がオフとされ
て信号cの部分c2の振幅を制限すると共に、その
Hレベル期間にトランジスタx2がオンとされて振
幅制限動作が解除される。 The limiter 11 has the configuration shown in FIG. 3, in which the transistor x1 is turned off during the H level period of the control signal d input to the terminal 11a, and limits the amplitude of the portion c1 of the signal c. During the L level period, the transistor x 1 is turned on and the amplitude limiting operation is canceled, while during the L level period of the control signal e input to the terminal 11b, the transistor x 2 is turned off and the part c 2 of the signal c is turned off. While limiting the amplitude, transistor x 2 is turned on during the H level period, and the amplitude limiting operation is canceled.
これにより、ライン相関がない部分c1,c2の期
間、信号cは振幅制限される一方、ライン相関が
ある部分c1,c2以外の期間、信号cは振幅制限さ
れず、従つて、ライン相関がある場合でリミツタ
11のリミツタレベルlを越えるパルスpをもつ
ノイズが入来した場合、パルスpはリミツタ11
からそのまま取出され、リミツタ11の出力は信
号f(同図F)とされる。減算器6において信号
aから信号fを減算器5にて減算した信号が減算
され、パルスpを含めたノイズが十分に低減され
て信号g(同図G)とされる。 As a result, the amplitude of the signal c is limited during the portions c 1 and c 2 where there is no line correlation, while the amplitude of the signal c is not limited during periods other than the portions c 1 and c 2 where there is line correlation, and therefore, If there is a line correlation and noise with a pulse p exceeding the limiter level l of the limiter 11 comes in, the pulse p will be
The output of the limiter 11 is taken as a signal f (F in the figure). A subtracter 6 subtracts a signal obtained by subtracting a signal f from a signal a by a subtracter 5, and noise including the pulse p is sufficiently reduced to obtain a signal g (G in the figure).
なお、ライン相関がある場合及びライン相関が
ない場合も上記の場合と同様の動作によりノイズ
を低減し得る。即ち、ライン相関がない場合減算
器3から取出される大振幅の信号成分からリミツ
タ11の振幅制限動作を可能にするレベルの制御
信号を得ると共に、ライン相関がある場合減算器
3から取出されるノイズ成分からリミツタ11の
振幅制限動作を解除するレベルの制御信号を得
る。 Note that noise can be reduced by the same operation as in the above case also when there is line correlation and when there is no line correlation. That is, when there is no line correlation, a control signal of a level that enables the amplitude limiting operation of the limiter 11 is obtained from the large amplitude signal component taken out from the subtracter 3, and when there is line correlation, it is taken out from the subtracter 3. A control signal having a level to cancel the amplitude limiting operation of the limiter 11 is obtained from the noise component.
これにより、ライン相関がない場合は従来回路
と同様にノイズ成分を低減された信号が取出さ
れ、ライン相関がある場合はパルスpを含むノイ
ズ成分を低減された信号が取出される。 As a result, when there is no line correlation, a signal with reduced noise components is extracted as in the conventional circuit, and when there is line correlation, a signal with reduced noise components including pulse p is extracted.
第4図は本発明回路の第2実施例のブロツク系
統図を示し、同図中、第1図と同一構成部分には
同一番号を付してその説明を省略する。同図にお
いて、端子1に入来した再生輝度信号aは微分回
路12にて1.5MHz以上の高域(エツジ)を正極
性及び負極性の極性別に夫々取出され、整形回路
13にて波形整形されて極性別に夫々信号i(第
5図B)が取出され、夫々アンドゲート14a,
14bに供給される。 FIG. 4 shows a block system diagram of a second embodiment of the circuit of the present invention, in which the same components as in FIG. 1 are given the same numbers and their explanations will be omitted. In the figure, a reproduced luminance signal a input to a terminal 1 is extracted by a differentiating circuit 12 in the high frequency range (edge) of 1.5 MHz or more into positive polarity and negative polarity, and is waveform-shaped by a shaping circuit 13. Signals i (FIG. 5B) are taken out for each polarity, and are passed through the AND gates 14a and 14a, respectively.
14b.
一方、リミツタ9a,9bからは第1実施例の
ものと同様にライン相関がある時Hレベル、ライ
ン相関がない時Lレベルの信号h(第5図A)が
取出され、アンドゲート14a,14bに供給さ
れる。 On the other hand, the limiters 9a and 9b take out a signal h (FIG. 5A) which is at H level when there is line correlation and at L level when there is no line correlation, as in the first embodiment, and the AND gates 14a and 14b is supplied to
信号hと正極性に対応の信号iとはアンドゲー
ト14aにてアンドをとられて信号j(同図C)
とされ、更にインバータ10で極性反転され、ラ
イン相関がある場合Lレベル、ライン相関がない
場合Hレベルの制御信号とされる。一方、信号
hと負極性に対応の信号iとはアンドゲート14
bにてアンドをとられ、ライン相関がある場合H
レベル、ライン相関がない場合Lレベルの制御信
号jとされる。 The signal h and the signal i corresponding to the positive polarity are ANDed by the AND gate 14a, and the result is a signal j (C in the same figure).
Further, the polarity is inverted by the inverter 10, and the control signal is set to L level when there is line correlation, and set to H level when there is no line correlation. On the other hand, the signal h and the signal i corresponding to the negative polarity are connected to the AND gate 14.
If the AND is taken at b and there is a line correlation, then H
If there is no level or line correlation, the control signal j is set to L level.
制御信号j,は夫々リミツタ11の端子11
a,11bに供給され、これにより、リミツタ1
1はライン相関があり、かつ、エツジ発生期間に
のみ振幅制限動作を解除され、パルスpを含めた
ノイズを十分に低減し得る。 The control signals j and are respectively connected to the terminals 11 of the limiters 11.
a, 11b, thereby limiter 1
1 has a line correlation, and the amplitude limiting operation is canceled only during the edge generation period, so that noise including the pulse p can be sufficiently reduced.
第6図は本発明回路の第3実施例のブロツク系
統図を示し、同図中、第4図と同一構成部分には
同一番号を付してその説明を省略する。このもの
は巡回形であり、減算器3において、端子1に入
来した再生輝度信号から減算器6の出力を1H遅
延回路2にて遅延した信号を減算するものであ
る。その他の動作は第1及び第2実施例のものと
同様であるので、その説明を省略する。 FIG. 6 shows a block system diagram of a third embodiment of the circuit of the present invention, in which the same components as those in FIG. 4 are given the same numbers and their explanations will be omitted. This is a cyclic type, in which a signal obtained by delaying the output of the subtracter 6 in the 1H delay circuit 2 is subtracted from the reproduced luminance signal inputted to the terminal 1 in the subtracter 3. The other operations are the same as those of the first and second embodiments, so their explanation will be omitted.
なお、上記各実施例はH相関に関する回路構成
であるが、これに限定されるものではなく、フイ
ールド相関或いはフレーム相関に関する回路構成
にしてもよい。 Although each of the above embodiments has a circuit configuration related to H correlation, the present invention is not limited to this, and a circuit configuration related to field correlation or frame correlation may be used.
4明の効果
上述の如く、本発明になるノイズリダクシヨン
回路は、入力信号の低域成分における相関の有無
を検出し、相関のあるときのみリミツタの振幅制
限動作を解除する回路を設けたので、相関がある
場合でリミツタレベルを越えるパルスをもつノイ
ズが入来した場合、パルスはリミツタからそのま
ま取出され、これにより、ノイズを十分に低減し
得、特に例えば1.5MHz以上の高域(エツジ)の
SN比を向上し得る等の特長を有する。そして、
入力信号の低域成分における相関の有無を検出す
ると共に、入力信号における高域成分の有無を検
出し、相関と高域成分の両方があるときのみリミ
ツタの振幅制限動作を解除する回路を設けた場合
には、エツジ部分のノイズも十分に低減すること
ができるという効果がある。4. Effect of Brightness As mentioned above, the noise reduction circuit according to the present invention is equipped with a circuit that detects the presence or absence of correlation in the low frequency components of the input signal and cancels the amplitude limiting operation of the limiter only when there is a correlation. If there is a correlation and there is incoming noise with pulses exceeding the limiter level, the pulses are taken out of the limiter as is, which can sufficiently reduce the noise, especially in the high frequency range (edge) of, for example, 1.5 MHz or higher.
It has features such as being able to improve the signal-to-noise ratio. and,
A circuit is installed that detects the presence or absence of correlation in the low-frequency components of the input signal, as well as the presence or absence of high-frequency components in the input signal, and releases the limiter's amplitude limiting operation only when there is both correlation and high-frequency components. In some cases, the noise at the edge portion can also be sufficiently reduced.
第1図及び第2図は夫々本発明回路の第1実施
例のブロツク系統図及び動作説明用信号波形図、
第3図は本発明回路の一部の具体的回路図、第4
図及び第5図は夫々本発明回路の第2実施例のブ
ロツク系統図及び動作説明用信号波形図、第6図
は本発明回路の第3実施例のブロツク系統図、第
7図は従来回路の一例のブロツク系統図、第8図
はパルスを含むノイズの信号波形図である。
1…再生輝度信号入力端子、2…1H遅延回路、
3,6…減算器、7…出力端子、8…アンプ、9
a,9b,11…リミツタ、10…インバータ、
12…微分回路、13…整形回路、14a,14
b…アンドゲート、15…低域フイルタ。
1 and 2 are a block system diagram and a signal waveform diagram for explaining the operation of the first embodiment of the circuit of the present invention, respectively;
FIG. 3 is a specific circuit diagram of a part of the circuit of the present invention, and FIG.
5 and 5 are respectively a block system diagram and a signal waveform diagram for explaining the operation of the second embodiment of the circuit of the present invention, FIG. 6 is a block system diagram of the third embodiment of the circuit of the present invention, and FIG. 7 is a conventional circuit. FIG. 8, which is an example block system diagram, is a signal waveform diagram of noise including pulses. 1... Reproduction brightness signal input terminal, 2... 1H delay circuit,
3, 6...Subtractor, 7...Output terminal, 8...Amplifier, 9
a, 9b, 11...limiter, 10...inverter,
12... Differential circuit, 13... Shaping circuit, 14a, 14
b...And gate, 15...Low pass filter.
Claims (1)
と、 この遅延回路の出力信号を前記入力信号から減
算する第1の減算回路と、 この第1の減算回路より出力される信号の振幅
制限を行なうリミツタと、 このリミツタより出力される信号を前記入力信
号から減算する第2の減算回路とを有するノイズ
リダクシヨン回路において、 前記第1の減算回路の出力信号が供給され、低
域成分のみを出力する低域フイルタと、 この低域フイルタより出力される信号によつ
て、前記入力信号の低域成分における相関の有無
を検出し、相関のあるときのみ前記リミツタの振
幅制限動作を解除する回路とを設けたことを特徴
とするノイズリダクシヨン回路。 2 入力信号又は出力信号を遅延する遅延回路
と、 この遅延回路の出力信号を前記入力信号から減
算する第1の減算回路と、 この第1の減算回路より出力される信号の振幅
制限を行なうリミツタと、 このリミツタより出力される信号を前記入力信
号から減算する第2の減算回路とを有するノイズ
リダクシヨン回路において、 前記第1の減算回路の出力信号が供給され、低
域成分のみを出力する低域フイルタと、 この低域フイルタより出力される信号によつ
て、前記入力信号の低域成分における相関の有無
を検出すると共に、前記入力信号における高域成
分の有無を検出し、相関と高域成分の両方がある
ときのみ前記リミツタの振幅制限動作を解除する
回路とを設けたことを特徴とするノイズリダクシ
ヨン回路。[Claims] 1. A delay circuit that delays an input signal or an output signal; a first subtraction circuit that subtracts the output signal of this delay circuit from the input signal; and a signal output from the first subtraction circuit. A noise reduction circuit having a limiter that limits the amplitude of the noise reduction circuit, and a second subtraction circuit that subtracts the signal output from the limiter from the input signal, the output signal of the first subtraction circuit being supplied, A low-pass filter that outputs only high-frequency components, and a signal output from this low-pass filter detects whether there is a correlation in the low-frequency components of the input signal, and only when there is a correlation, the limiter operates to limit the amplitude. A noise reduction circuit comprising: a circuit for canceling the noise reduction circuit; 2. A delay circuit that delays an input signal or an output signal, a first subtraction circuit that subtracts the output signal of this delay circuit from the input signal, and a limiter that limits the amplitude of the signal output from this first subtraction circuit. and a second subtraction circuit that subtracts the signal output from the limiter from the input signal, the noise reduction circuit is supplied with the output signal of the first subtraction circuit and outputs only low-frequency components. A low-pass filter, and a signal output from the low-pass filter to detect the presence or absence of correlation in the low-frequency components of the input signal, and to detect the presence or absence of high-frequency components in the input signal, and to detect the correlation and high frequency components. and a circuit for canceling the amplitude limiting operation of the limiter only when both of the range components are present.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59121133A JPS60264178A (en) | 1984-06-13 | 1984-06-13 | Noise reduction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59121133A JPS60264178A (en) | 1984-06-13 | 1984-06-13 | Noise reduction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60264178A JPS60264178A (en) | 1985-12-27 |
| JPH0326949B2 true JPH0326949B2 (en) | 1991-04-12 |
Family
ID=14803687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59121133A Granted JPS60264178A (en) | 1984-06-13 | 1984-06-13 | Noise reduction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60264178A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6320968A (en) * | 1986-07-15 | 1988-01-28 | Matsushita Electric Ind Co Ltd | Television picture signal processor |
| JPS63299690A (en) * | 1987-05-29 | 1988-12-07 | Matsushita Electric Ind Co Ltd | Line noise canceler circuit |
| JPH05304622A (en) * | 1992-04-24 | 1993-11-16 | Toshiba Corp | Noise detector and noise reduction device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58223973A (en) * | 1982-06-22 | 1983-12-26 | Victor Co Of Japan Ltd | Noise reduction circuit |
-
1984
- 1984-06-13 JP JP59121133A patent/JPS60264178A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60264178A (en) | 1985-12-27 |
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