JPH0328009B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure detection device for a relay drive circuit controlled by a logic device.
The purpose of this invention is to detect circuit failures as a heavy system at an early stage, prevent relay malfunctions due to circuit failures, and thereby contribute to improving the reliability of this type of relay drive device.

As shown in Figure 1, a conventional relay drive circuit of this type has one relay drive transistor controlled by a logic device, and does not include a transistor failure detection circuit. In general, there was no such thing. Therefore, if a short-circuit failure occurs in the relay driving transistor, the relay malfunctions, resulting in dangerous consequences.

The present invention includes a relay operation circuit in which two transistors and one relay are connected in series, and a transistor operation monitoring circuit outside the circuit connected in series to each of the transistors and in parallel to the relay. 2. Turn on and off each transistor individually at a speed that the relay cannot respond to.
By checking the output of each monitoring circuit, failures in each transistor can be detected early and malfunctions of relays can be prevented.

Embodiments of the present invention will be described below with reference to FIGS. 2 and 3.

Figure 2 is a circuit diagram configuring the dual relay drive device of the present invention, in which Ry is a relay, Tr ₁ and Tr ₂ are transistors, and OCI ₁ and OCI ₂ are each a combination of a light receiving transistor and a light emitting diode. D is a diode, and R ₁ and R ₂ are resistors.
The LG is a logic device that controls the operation of a circuit whose components are each element below the relay.

Next, we will discuss the operation of the circuit shown in Figure 2.
Normal operation is based on the control signals b ₁ , b ₂ from the logic unit LG.
are input to the base circuits of transistors Tr ₁ and Tr ₂ , so that both transistors are turned on.
So, power supply (+) → transistor Tr ₂ → relay
A circuit of Ry → diode D → transistor Tr ₁ → power supply (-) is constructed, and relay Ry operates.
Further, when there is no control signal b ₁ or b ₂ and therefore both transistors Tr ₁ and Tr ₂ are OFF, the relay Ry is restored. Furthermore, when one of the control signals b ₁ and b ₂ is present and the other is not, that is, the transistor
When either Tr ₁ or Tr ₂ is ON and the other is OFF, relay Ry is restored. The above is a case of normal operation under normal conditions.

Therefore, the operation of checking for transistor failure in the circuit of FIG. 2 will be explained using the time chart of FIG. 3. Chart a in FIG. 3 is a time chart of the check operation of transistor Tr ₁ , and chart b of the same figure is a time chart of the check operation of transistor Tr ₂ , when ON and OFF operations are performed simultaneously. Both the ON time t ₁ and the OFF time t ₂ in the figure are short times in which the relay Ry cannot operate or recover. Such transistors Tr ₁ and Tr ₂
ON and OFF operations are performed using the control signal b ₁ from the logic device LG,
It goes without saying that they are each controlled by _b2 , and may be turned on and off at the same time as shown in charts a and b, or may be turned on and off separately. When the ON time of the transistors Tr ₁ and Tr ₂ continues for a certain period of time or more, the relay Ry operates as shown in chart c in Fig. 3, and the transistors Tr ₁ and Tr ₂ are turned OFF for a short period of time t ₂ . However, relay Ry continues to operate without recovery.

As mentioned above, in the device shown in FIG. 2, in addition to the conditions for driving the relay Ry, timings t ₁ and t ₂ for checking the operation of the transistors Tr ₁ and Tr ₂ are created.
The conditions are output to transistors Tr ₁ and Tr ₂ .
The operating state of each transistor at this time is monitored by the optical coupling elements OCI ₁ and OCI ₂ , respectively. That is, the chart d in FIG. 3 is the transistor Tr ₁
This is a time chart of the optical coupling element OCI ₁ which operates in accordance with the operation of the transistor Tr ₂ .
In the time chart of OCI ₂ , optocoupler ODI ₁ is connected in series with transistor Tr ₁ , and optocoupler OCI ₂ is connected in series with transistor Tr ₂ , so the operation timing of each optocoupler is Each is synchronized with the operating timing of the transistors connected in series. Therefore, the operation of each transistor is monitored at times synchronized with the check timings t ₁ and t ₂ (T ₁ and T ₂ of the chart ()), and the operation of the transistor Tr _{1 is} monitored.
Or, it is determined by the logic device LG that the output state is such that Tr ₂ remains ON or remains OFF. In this way, when the logic device LG determines that the transistor Tr ₁ or Tr ₂ has failed,
By immediately stopping the output of control signals b ₁ and b ₂ , malfunction of relay Ry can be prevented.

Note that the diode D inserted in series in the circuit of the relay Ry is the power supply (+) → resistance R ₁ → optical coupling element.
OCI ₁ → Relay Ry → Optical coupling element OCI ₂ → Resistor R ₂ → Prevents current from flowing in the power supply (-) circuit. If this diode D is short-circuited, the optical coupling element
Since OCI ₁ and OCI ₂ no longer operate normally, it is also possible to discover the failure of diode D. Furthermore, in this embodiment, an optical coupling element was used to monitor the operating states of the transistors Tr ₁ and Tr ₂ , but other circuits, such as inserting a relay, using the voltage drop of the resistor R ₁ , or using a magnetic sensor, etc. It's okay.

As explained in the above embodiments, the present invention employs a dual system of transistors that drive relays, and attaches a monitoring circuit for the operation of each transistor, thereby detecting circuit failures at an early stage and detecting circuit failures. This makes it possible to prevent malfunctions of relays based on this method, and has a significant effect on improving the reliability of this type of relay drive circuit.

[Brief explanation of drawings]

Figure 1 is an example of a conventional relay drive circuit, Figure 2
The figure is a circuit diagram showing an embodiment of the dual system relay driving device of the present invention, and FIG. 3 is a time chart for explaining the operation of the same circuit. Tr ₁ , Tr ₂ : Transistor, Ry: Relay,
OCI ₁ , OCI ₂ : (Optical coupling element) monitoring circuit, LG: Logic device.

Claims (1)

[Claims] 1 Consists of a relay operation circuit in which two transistors and one relay are connected in series, and a circuit in which a transistor operation monitoring circuit is connected outside the circuit in series to each of the transistors and in parallel to the relay. , a dual system relay driving device, characterized in that the two transistors are individually driven with a short-time signal to which the relay cannot respond, and the output of the monitoring circuit is checked to detect a failure in each transistor. .