JPH0328584B2 - - Google Patents
Info
- Publication number
- JPH0328584B2 JPH0328584B2 JP18948784A JP18948784A JPH0328584B2 JP H0328584 B2 JPH0328584 B2 JP H0328584B2 JP 18948784 A JP18948784 A JP 18948784A JP 18948784 A JP18948784 A JP 18948784A JP H0328584 B2 JPH0328584 B2 JP H0328584B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power supply
- main
- ram
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02D—CONTROLLING COMBUSTION ENGINES
- F02D41/00—Electrical control of supply of combustible mixture or its constituents
- F02D41/24—Electrical control of supply of combustible mixture or its constituents characterised by the use of digital means
- F02D41/2406—Electrical control of supply of combustible mixture or its constituents characterised by the use of digital means using essentially read only memories
- F02D41/2425—Particular ways of programming the data
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02D—CONTROLLING COMBUSTION ENGINES
- F02D41/00—Electrical control of supply of combustible mixture or its constituents
- F02D41/24—Electrical control of supply of combustible mixture or its constituents characterised by the use of digital means
- F02D41/26—Electrical control of supply of combustible mixture or its constituents characterised by the use of digital means using computer, e.g. microprocessor
- F02D41/266—Electrical control of supply of combustible mixture or its constituents characterised by the use of digital means using computer, e.g. microprocessor the computer being backed-up or assisted by another circuit, e.g. analogue
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Combustion & Propulsion (AREA)
- Mechanical Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Combined Controls Of Internal Combustion Engines (AREA)
Description
【発明の詳細な説明】
＜産業上の利用分野＞
本発明は車載マイクロコンピユータのメモリバ
ツクアツプ装置に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a memory backup device for a vehicle-mounted microcomputer.
＜従来の技術＞
たとえば車両に搭載された内燃機関を集中制御
する車載マイクロコンピユータは、その作動開始
時には前回作動時のデータを必要とするものであ
る。このため、この種の車載マイクロコンピユー
タは、キースイツチオフ後も、バツテリから、バ
ツクアツプ電源回路を介してRAMに給電するこ
とにより、次回の作動時までRAM内のデータを
保持させるメモリバツクアツプ装置を有している
（例えば特願昭58−73062号等）。<Prior Art> For example, an on-vehicle microcomputer that centrally controls an internal combustion engine mounted on a vehicle requires data from the previous operation when starting its operation. For this reason, this type of in-vehicle microcomputer is equipped with a memory backup device that maintains the data in the RAM until the next operation by supplying power from the battery to the RAM via the backup power supply circuit even after the key switch is turned off. (For example, Japanese Patent Application No. 58-73062, etc.)
従来のメモリバツクアツプ装置の一例を第３図
に示す。 An example of a conventional memory backup device is shown in FIG.
図において、バツテリ１の電圧はキースイツチ
２を介してメイン安定化電源である定電圧レギユ
レータ３に入力され、その出力電圧V1（例えば
5V）は、メイン通電回路Ａを介して図示しない
ROM、MPUに供給されると共に、トランジス
タ１１，１２及び抵抗１３〜１６からなるスイツ
チング回路１０を介してRAM４に供給される。
また、バツテリ電圧はキースイツチ２を介さず直
接にダイオード２１、コンデンサ２２、ツエナダ
イオード２３からなるバツクアツプ電源回路２０
に入力され、その出力電圧V2（例えば5V）はバ
ツクアツプ通電回路Ｂを通つて前記RAM４に供
給される。更に、バツテリ電圧はキースイツチ２
を介してトランジスタ３１、ダイオード３２，３
３および抵抗３４，３５等で構成されRAM４と
MPUの断接を制御するスタンバイ信号を形成す
るスタンバイ信号形成回路３０に入力されてい
る。 In the figure, the voltage of a battery 1 is input via a key switch 2 to a constant voltage regulator 3, which is the main stabilized power supply, and its output voltage V 1 (for example
5V) is not shown through the main energizing circuit A.
The signal is supplied to the ROM and MPU as well as to the RAM 4 via a switching circuit 10 consisting of transistors 11, 12 and resistors 13-16.
In addition, the battery voltage is directly supplied to the backup power supply circuit 20 consisting of the diode 21, capacitor 22, and Zener diode 23 without passing through the key switch 2.
The output voltage V 2 (for example, 5V) is supplied to the RAM 4 through the backup energization circuit B. Furthermore, the battery voltage is controlled by key switch 2.
Transistor 31, diode 32, 3 via
3 and resistors 34, 35, etc. RAM4 and
The signal is input to a standby signal forming circuit 30 that forms a standby signal for controlling connection/disconnection of the MPU.
次にかかる従来装置の作用を説明する。 Next, the operation of this conventional device will be explained.
キースイツチ２をONと操作すると、定電圧レ
ギユレータ３の出力電圧V1が立ち上がりROM、
MPUへ供給される。また、前記V1の立ち上がり
に伴つてスイツチング回路１０のトランジスタ１
１がONし、トランジスタ１２がONしてメイン
通電回路Ａが閉成され、RAM４に供給される電
圧がバツクアツプ電源回路２０の出力電圧V2か
ら定電圧レギユレータ３の出力電圧V1に切り換
えられる。 When the key switch 2 is turned ON, the output voltage V1 of the constant voltage regulator 3 rises and the ROM,
Supplied to MPU. Further, as the voltage V 1 rises, the transistor 1 of the switching circuit 10 is turned off.
1 is turned on, the transistor 12 is turned on, the main energizing circuit A is closed, and the voltage supplied to the RAM 4 is switched from the output voltage V 2 of the backup power supply circuit 20 to the output voltage V 1 of the constant voltage regulator 3.
また、キースイツチ２のON操作に伴い、スタ
ンバイ信号形成回路３０にもバツテリ電圧が入力
され、この入力電圧U′Bとバツクアツプ電源回路
２０の出力電圧V2との差が所定レベル以上にな
るとダイオード３２、抵抗３４を介してベース電
流が流れトランジスタ３１がONし、トランジス
タ３１と抵抗３５との接続点ａの電圧が略入力電
圧U′Bと等しくなり、所定時間後に、２つの
NAND回路５，６を介してスタンバイ信号が
“Ｌ”レベルから“Ｈ”レベルに切り換えられ、
RAM４とMPUが接続される。そして、定電圧
レギユレータ３からの安定した出力電圧V1によ
つてMPUが作動しエンジン運転等に要求される
各種演算が行われる。 Further, with the ON operation of the key switch 2, the battery voltage is also input to the standby signal forming circuit 30, and when the difference between this input voltage U'B and the output voltage V2 of the backup power supply circuit 20 exceeds a predetermined level, the diode 32 , the base current flows through the resistor 34, turning on the transistor 31, and the voltage at the connection point a between the transistor 31 and the resistor 35 becomes approximately equal to the input voltage U'B , and after a predetermined time, the two
The standby signal is switched from the "L" level to the "H" level via the NAND circuits 5 and 6,
RAM4 and MPU are connected. Then, the MPU is operated by the stable output voltage V1 from the constant voltage regulator 3, and various calculations required for engine operation etc. are performed.
一方、キースイツチ２をOFFにすると、スタ
ンバイ信号形成回路３０の入力電圧U′Bが低下し
トランジスタ３１がOFFとなり、接続点ａの電
圧が低下することによりスタンバイ信号が“Ｈ”
レベルから“Ｌ”レベルに切り換わり、RAM４
とMPUが切り離される。また、スイツチング回
路１０のトランジスタ１２がOFFになりRAM４
からメイン通電回路Ａが切り離されるが、RAM
４へはバツクアツプ通電回路Ｂを介してバツクア
ツプ電源回路２０の出力電圧V2が入力され、
RAM４内に記憶された次回作動時に必要なデー
タを保持するようになつている。 On the other hand, when the key switch 2 is turned off, the input voltage U'B of the standby signal forming circuit 30 decreases, turning off the transistor 31, and the voltage at the connection point a decreases, causing the standby signal to go "H".
level to “L” level, RAM4
and the MPU is disconnected. Also, the transistor 12 of the switching circuit 10 is turned off, and the RAM 4
The main current-carrying circuit A is disconnected from the RAM.
The output voltage V2 of the backup power supply circuit 20 is inputted to 4 through the backup energization circuit B.
The data stored in RAM 4 and necessary for the next operation is retained.
＜発明が解決しようとする問題点＞
しかしながら、従来装置では、メイン通電回路
ＡとRAM４とを断接するスイツチング回路１０
の動作信号を、定電圧レギユレータ３の出力から
取り入れていたため、定電圧レギユレータ３の出
力電圧V1が安定しないうちにスイツチング回路
１０のトランジスタ１１がONしてしまう。この
ため、キースイツチ２のON操作直後において、
バツクアツプ通電回路Ｂを流れる電流が、スイツ
チング回路１０の抵抗１５及びトランジスタ１１
を介してアースに流れてしまい、RAM４に供給
するバツクアツプ電源回路２０の出力電圧V2の
落ち込みが生じる。この場合、バツクアツプ電源
回路２０のコンデンサ２２の経時変化及び温度特
性等を考慮すると、RAM４のデータ保持に必要
な最小電圧である2Vを割る恐れがあるという問
題を有していた。<Problems to be Solved by the Invention> However, in the conventional device, the switching circuit 10 that connects and disconnects the main energizing circuit A and the RAM 4 is
Since the operating signal was taken in from the output of the constant voltage regulator 3, the transistor 11 of the switching circuit 10 is turned on before the output voltage V1 of the constant voltage regulator 3 is stabilized. Therefore, immediately after turning on key switch 2,
The current flowing through the backup energizing circuit B flows through the resistor 15 and transistor 11 of the switching circuit 10.
This causes the output voltage V 2 of the backup power supply circuit 20 that supplies the RAM 4 to drop. In this case, considering the aging and temperature characteristics of the capacitor 22 of the backup power supply circuit 20, there is a problem that the voltage may fall below 2V, which is the minimum voltage required for data retention in the RAM 4.
本発明は上記の問題点に鑑みてなされたもの
で、メイン安定化電源の出力が安定した後に、ス
イツチング回路が動作を開始するようにし、以て
キースイツチのON直後におけるRAMへの供給
電圧の落ち込み現象を防止することを目的とす
る。 The present invention was made in view of the above problem, and the switching circuit starts operating after the output of the main stabilized power supply becomes stable, thereby reducing the drop in the supply voltage to the RAM immediately after the key switch is turned on. The purpose is to prevent the phenomenon.
＜問題点を解決するための手段＞
このため本発明では、トランジスタを用いたス
イツチング回路によつてメイン安定化電源と
RAMとを断接するようにしてバツクアツプ電源
とメイン安定化電源との切り換えを行う構成のメ
モリバツクアツプ装置において、スイツチング回
路の動作信号を、メイン安定化電源と並列でかつ
キースイツチを介してバツテリと接続されるスタ
ンバイ信号形成回路を介して取り出す構成とする
と共に、スイツチング回路への動作信号の入力を
遅延させる遅延回路を設けるようにした。<Means for solving the problem> For this reason, in the present invention, the main stabilized power supply and the switching circuit using transistors are used.
In a memory backup device configured to switch between the backup power supply and the main stabilized power supply by connecting/disconnecting the RAM, the operating signal of the switching circuit is connected to the battery in parallel with the main stabilized power supply and via a key switch. In addition, a delay circuit is provided to delay the input of the operation signal to the switching circuit.
＜作用＞
これにより、メイン安定化電源の安定時の出力
電圧以上の電圧で作動するスタンバイ信号形成回
路が作動してから所定時間遅延されてスイツチン
グ回路へ動作信号が入力することになり、スイツ
チング回路の作動開始が、確実にメイン安定化電
源の出力が安定した後に行われるようになる。<Function> As a result, the operation signal is input to the switching circuit after a predetermined time delay after the standby signal forming circuit, which operates at a voltage higher than the stable output voltage of the main stabilized power supply, is activated. The start of operation will surely take place after the output of the main stabilized power supply has stabilized.
＜実施例＞
以下本発明の一実施例を第１図及び第２図に基
づいて説明する。尚、第３図に示す従来例と同一
構成部分には同一符号を付して詳細な説明を省略
する。<Example> An example of the present invention will be described below based on FIGS. 1 and 2. Components that are the same as those of the conventional example shown in FIG. 3 are denoted by the same reference numerals and detailed explanations will be omitted.
第１図において、定電圧レギユレータ３、バツ
クアツプ電源回路２０、スタンバイ信号形成回路
３０は従来同様に構成され接続されている。 In FIG. 1, a constant voltage regulator 3, a backup power supply circuit 20, and a standby signal forming circuit 30 are constructed and connected in the same manner as conventional ones.
一方、スイツチング回路１０′は、その動作信
号をスタンバイ信号形成回路３０を介して取り入
れるよう構成されている。即ち、トランジスタ１
１のベースを、抵抗４１及びコンデンサ４２で構
成された遅延回路４０を介してスタンバイ信号形
成回路３０のトランジスタ３１のコレクタと抵抗
３５との間に接続してある。 On the other hand, the switching circuit 10' is configured to receive its operating signal via the standby signal forming circuit 30. That is, transistor 1
1 is connected between the collector of the transistor 31 of the standby signal forming circuit 30 and the resistor 35 via a delay circuit 40 composed of a resistor 41 and a capacitor 42.
次に作用を第２図のタイムチヤートを参照しな
がら説明する。 Next, the operation will be explained with reference to the time chart shown in FIG.
キースイツチ２をON操作すると、定電圧レギ
ユレータ３への供給電圧U′Bと共にその出力電圧
V1が立ち上がり、出力電圧V1は所定値（例えば
5V）に達すると一定に保たれるが前記U′B即ちス
タンバイ信号形成回路30の入力電圧は、さらに増
大して定常時のバツテリ電圧に達する。 When key switch 2 is turned ON, the supply voltage U′ B to constant voltage regulator 3 and its output voltage
V 1 rises and the output voltage V 1 is set to a predetermined value (e.g.
5V), it remains constant, but the input voltage of the standby signal forming circuit 30 increases further and reaches the normal battery voltage.
そして、従来と同様にしてU′Bがバツクアツプ
電源回路２０の出力電圧V2（例えば5V）よりも
所定レベル以上になると、トランジスタ３１が
ONとなり、トランジスタ３１のコレクタと抵抗
３５との間の電圧が上昇し略U′Bと等しくなる。
かかる電圧の上昇によつてスイツチング回路１
０′の動作信号が遅延回路４１を介して所定時間
遅延されてトランジスタ１１のベースに入力す
る。これにより、トランジスタ１１がONし、さ
らにトランジスタ１２がONしてメイン通電回路
Ａを介して定電圧レギユレータ３をRAM４に接
続する。この時点では、定電圧レギユレータ３の
出力電圧V1は安定しているため、従来のような
バツクアツプ通電回路Ｂからの電流の流れ込みを
確実に防止できる。従つて、電圧の落ち込み現象
を生ずることなく、RAM４への供給電圧がバツ
クアツプ電源回路２０の出力電圧V2から定電圧
レギユレータ３の出力電圧V1へ安定した状態で
スムーズに切り換えられる。 Then, as in the conventional case, when U′ B becomes a predetermined level or higher than the output voltage V 2 (for example, 5V) of the backup power supply circuit 20, the transistor 31 is turned on.
It turns on, and the voltage between the collector of the transistor 31 and the resistor 35 rises and becomes approximately equal to U'B .
Due to this increase in voltage, the switching circuit 1
The operation signal 0' is input to the base of the transistor 11 after being delayed for a predetermined time via the delay circuit 41. As a result, the transistor 11 is turned on, and the transistor 12 is also turned on, thereby connecting the constant voltage regulator 3 to the RAM 4 via the main energizing circuit A. At this point, the output voltage V1 of the constant voltage regulator 3 is stable, so that it is possible to reliably prevent current from flowing into the backup current supply circuit B as in the conventional case. Therefore, the voltage supplied to the RAM 4 can be smoothly and stably switched from the output voltage V 2 of the backup power supply circuit 20 to the output voltage V 1 of the constant voltage regulator 3 without causing a voltage drop phenomenon.
また、スタンバイ信号形成回路３０のａ点が電
圧上昇してから所定時間後に、２つのNAND回
路５，６を介してスタンバイ信号が“Ｌ”レベル
から“Ｈ”レベルに切り換わりMPUとRAM４
が接続され演算動作が開始される。 Furthermore, after a predetermined period of time after the voltage at point a of the standby signal forming circuit 30 increases, the standby signal switches from the "L" level to the "H" level via the two NAND circuits 5 and 6, and the MPU and RAM 4
is connected and calculation operation begins.
一方、キースイツチ２をONからOFFにする
と、U′Bが低下し、スタンバイ信号形成回路３０
のトランジスタ３１がOFFになつた時点から所
定時間遅れてスイツチング回路１０′のトランジ
スタ１１がOFFとなり、トランジスタ１２が
OFFしてメイン通電回路ＡをRAM４から切り離
す。そして、RAM４へはバツクアツプ電源回路
２０の出力電圧V2がバツクアツプ通電回路Ｂを
介して供給される。このときには、定電圧レギユ
レータ３の出力電圧V1はまだ安定状態にあるの
で、前記切り換えはスムーズに行われる。従つ
て、RAM４内の次回動作時に必要なデータは確
実に保持される。尚、スタンバイ信号も、トラン
ジスタ３１のOFF後所定時間後に“Ｈ”レベル
から“Ｌ”レベルに切り換わりMPUとRAM４
とを切り離すことは従来同様である。 On the other hand, when the key switch 2 is turned from ON to OFF, U′ B decreases and the standby signal forming circuit 30
After a predetermined time delay after the transistor 31 of the switching circuit 10' turns OFF, the transistor 11 of the switching circuit 10' turns OFF, and the transistor 12 turns OFF.
Turn OFF and disconnect main energizing circuit A from RAM4. The output voltage V2 of the backup power supply circuit 20 is supplied to the RAM 4 via the backup power supply circuit B. At this time, the output voltage V1 of the constant voltage regulator 3 is still in a stable state, so the switching is performed smoothly. Therefore, data necessary for the next operation in the RAM 4 is reliably retained. The standby signal also switches from the "H" level to the "L" level after a predetermined period of time after the transistor 31 is turned off, and the MPU and RAM 4
The separation between the two is the same as before.
＜発明の効果＞
以上述べたように本発明によれば、スイツチン
グ回路の動作信号をメイン安定化電源の出力から
ではなく、メイン安定化電源への供給電圧から取
り入れかつ遅延回路で遅らせて入力するようにし
たので、メイン安定化電源の出力電圧が安定した
後に、スイツチング回路の動作が開始してメイン
安定化電源をRAMに接続するため、RAMへの
供給電圧の落ち込み現象を防止できる。従つて、
RAMの記憶保持を確実なものにできる。<Effects of the Invention> As described above, according to the present invention, the operating signal of the switching circuit is taken in from the voltage supplied to the main stabilized power supply, not from the output of the main stabilized power supply, and is input after being delayed by the delay circuit. As a result, after the output voltage of the main stabilized power supply becomes stable, the switching circuit starts operating and connects the main stabilized power supply to the RAM, thereby preventing the drop in the voltage supplied to the RAM. Therefore,
Memory retention in RAM can be ensured.
第１図は本発明の一実施例の回路構成図、第２
図は同上実施例のタイムチヤート、第３図は従来
例の回路構成図である。
１……バツテリ、２……キースイツチ、３……
定電圧レギユレータ、４……RAM、１０′……
スイツチング回路、１１，１２……トランジス
タ、２０……バツクアツプ電源回路、３０……ス
タンバイ信号形成回路、４０……遅延回路、Ａ…
…メイン通電回路、Ｂ……バツクアツプ通電回
路。
Fig. 1 is a circuit configuration diagram of an embodiment of the present invention;
The figure is a time chart of the same embodiment, and FIG. 3 is a circuit configuration diagram of a conventional example. 1...Battery, 2...Key switch, 3...
Constant voltage regulator, 4...RAM, 10'...
Switching circuit, 11, 12...Transistor, 20...Backup power supply circuit, 30...Standby signal forming circuit, 40...Delay circuit, A...
...Main energizing circuit, B...Backup energizing circuit.
Claims (1)
メイン安定化電源を介装したメイン通電回路と、
バツテリに直接接続されるバツクアツプ電源を介
装したバツクアツプ通電回路と、キースイツチの
ON動作によつてメイン通電回路を閉成しメイン
安定化電源をRAMに接続するスイツチング回路
と、メイン安定化電源と並列かつキースイツチを
介してバツテリと接続され前記RAMとメイン安
定化電源によつて作動するMPUとの断接を制御
するスタンバイ信号を形成する回路とを備えた車
載マイクロコンピユータのメモリバツクアツプ装
置において、前記スイツチング回路の動作信号
を、前記スタンバイ信号形成回路を介して取り出
す構成とすると共に、前記動作信号を遅延させる
遅延回路を設けたことを特徴とする車載マイクロ
コンピユータのメモリバツクアツプ装置。1 A main energizing circuit with a main stabilized power supply connected to the battery via a key switch,
A backup energizing circuit with a backup power supply connected directly to the battery, and a key switch.
A switching circuit that closes the main energizing circuit by ON operation and connects the main regulated power supply to the RAM, and a switching circuit that is connected to the battery in parallel with the main regulated power supply via a key switch and connected to the RAM and the main regulated power supply. A memory backup device for an on-vehicle microcomputer comprising a circuit for forming a standby signal for controlling connection/disconnection with an operating MPU, wherein the operating signal of the switching circuit is taken out via the standby signal forming circuit. A memory backup device for a vehicle-mounted microcomputer, further comprising a delay circuit for delaying the operation signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18948784A JPS6170155A (en) | 1984-09-12 | 1984-09-12 | Memory backup device for in-vehicle microcomputer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18948784A JPS6170155A (en) | 1984-09-12 | 1984-09-12 | Memory backup device for in-vehicle microcomputer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6170155A JPS6170155A (en) | 1986-04-10 |
| JPH0328584B2 true JPH0328584B2 (en) | 1991-04-19 |
Family
ID=16242082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18948784A Granted JPS6170155A (en) | 1984-09-12 | 1984-09-12 | Memory backup device for in-vehicle microcomputer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6170155A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2587078Y2 (en) * | 1991-07-04 | 1998-12-14 | 本田技研工業株式会社 | RAM data guarantee device |
-
1984
- 1984-09-12 JP JP18948784A patent/JPS6170155A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6170155A (en) | 1986-04-10 |
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