JPH0328864B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an interface circuit between two digital devices whose operating frequencies are asynchronous.

[Description of prior art]

Conventionally, memory such as a register file is used in an interface circuit, data signals input in time series are used as data input, time information is used as address input, and writing is performed at all times, while scanning is performed by independent synchronization on the reading side. The method used was to acquire information by doing things.

For this reason, all data signals of "0" or "1" that are input in time series must be stored in the memory, so a memory with a large storage capacity must be used, and furthermore, it is necessary to use a memory with a large storage capacity. Because it is necessary to read data sequentially regardless of whether the input data signal is "0" or "1", addresses in the memory are sequentially designated as read signals.
Since all addresses must be searched, the operation time required to collect information becomes a large part of the time.

The present inventors focused on the fact that the above-mentioned drawbacks can be eliminated by changing the conventional method in which input time information is accumulated and stored in sequence to a method in which it is stored only when a certain data signal is present. The invention was completed.

[Purpose of the invention]

Instead of sequentially accumulating data signals of "0" or "1" input in time series, the present invention uses time information representing the time series as data input only when the data signal is "0" or "1". An interface circuit that can reduce the memory capacity by storing data, and shorten the time required to collect information by reading it as time information only when the stored data signal is "0" or "1". The purpose is to provide

[Features of the invention]

The interface circuit of the present invention has a data signal of "0" or "1" inputted in time series, a clock pulse synchronized with the data signal, and time information representing the time series, and the clock pulse is used as the "0" or "1" data signal of the data signal. ” or “1”, a gate circuit that passes the data, time information representing a time series as data input, the output signal of the gate circuit as a write signal, and only when the data is “0” or “1”, the time series is expressed. Write time information, generate accumulated information for data input, and based on that accumulated information,
A first-in/first-out memory circuit that sends time information when a data signal input in time series is "0" or "1" by a read signal input asynchronously with the writing side of the stored data. It is characterized by

[Explanation based on examples]

A circuit according to an embodiment of the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram showing a circuit according to an embodiment of the present invention.
FIG. 2 is a time chart showing various signals for explaining the operation of the circuit according to the embodiment of the present invention. In the device circuit according to the embodiment of the present invention, an external information input terminal 1 and a clock pulse input terminal 2 are connected to an AND gate 4, and this AND gate 4 and an address signal input terminal 3 are connected to a first-in/first-out memory 5.

The first-in/first-out memory 5 is connected to an output ready output terminal 6, a shift out output terminal 7, and an address signal output terminal 8.

The operation of the circuit according to the embodiment of the present invention configured as described above will be explained. An external information input terminal 1 receives a data signal a of "0" or "1" inputted in time series, and a clock pulse input terminal 2 receives a clock pulse b synchronized with the data signal. Further, time-series time information c is input to the address signal input terminal 3.

The data signal a and clock pulse b are
The write signal d is input to the AND gate 4 and the write signal d is extracted by inhibiting the clock pulse b with the low level "0" of this data signal.

This write signal d and the above-mentioned time information c are input to the SI terminal and D terminal of the first-in/first-out memory 5, respectively, and this first-in/first-out memory 5 is in a state where the data signal a is at a high level of "1". Only then, time information c representing the time series is generated as accumulated information e, which is the data input of the write signal d, and based on the accumulated information e, accumulated data is transferred from the shift-out output terminal 7 asynchronously to the writing side. , the read signal f input to the SO terminal of the first-in/first-out memory 5 sends out time information g when the data signal input in time series is "1".

The above accumulated information e and this time information g are the OR of the above first-in/first-out memory 5.
It is output from the terminal and the Q terminal.

Unlike the above-mentioned method in which data signals of "0" or "1" input in time series are stored and stored sequentially by specifying an address as time information, the data signal is either "0" or "1". Since the time information is stored in the first-in/first-out memory 5 as storage information only in this case, the memory capacity and readout time can be reduced. In addition, when the reading side is a computer, information can be collected by simply specifying one port, making it possible to simplify the program and reduce the operating rate.

〔Effect of the invention〕

As explained above, according to the present invention, time information is stored in the first-in/first-out memory as storage information only when the data signal is "0" or "1", thereby reducing memory capacity and readout time. It can be shortened, and if the reading side is a computer, information can be collected by specifying only one port, which has the excellent effect of simplifying the program and reducing the operating rate. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a circuit according to an embodiment of the present invention.
FIG. 2 is a time chart showing various signals for explaining the operation of the circuit according to the embodiment of the present invention. 1... External information input terminal, 2... Clock pulse input terminal, 3... Address signal input terminal, 4... AND gate, 5... First-in/first-out memory, 6... Output ready output terminal, 7...
Shift out input terminal, 8...address signal output terminal.

Claims (1)

[Claims] 1. An input terminal for a data signal inputted in time series, an input terminal for a clock pulse synchronized with this data signal, an input terminal for time information representing a time series of this clock pulse, and the above-mentioned data signal and the above-mentioned a gate circuit that receives a clock pulse and passes the clock pulse at the timing of either "0" or "1" of the data signal; and a first-in-first circuit that writes the time information in response to the output of the gate circuit. An interface circuit comprising: an out memory; and circuit means for reading out the time information written in the first-in/first-out memory using a read signal asynchronous with the writing side.