JPH0330171B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to microprogram control in an information processing device, and more particularly to a microprogram control method for instructions of different operations depending on a state mode defined in a system architecture. (Prior Art) Conventionally, in this type of information processing device, there may be a difference in the operation of a specific instruction due to a difference in the state mode defined in the system architecture that occupies the device. In such a case, a set of microprogram startup addresses is prepared corresponding to the instruction code, and if a different operation depending on the state mode exists in the activated instruction, the microprogram startup address is The state mode was referenced by the instruction firmware, a conditional branch was made, and the corresponding operation routine was executed. In this system, instructions with different operations refer to the state mode, and a step that performs a conditional branch is always present in the microprogram, which is a major factor in performance deterioration. For this reason, recently, the following configuration described in Japanese Patent Application No. 59-81585 (Japanese Unexamined Patent Publication No. 60-225253) has been adopted. For a group of instructions that are unrelated to the state mode, create one microprogram corresponding to each instruction, and if the operation of the instruction differs depending on the state mode, create as many microprograms as the number of related state modes for each instruction. A unique startup address is given to every created microprogram and stored in the control store, and the control memory that stores the startup address of the microprogram is provided with compartments equal to the number of state modes. stores the start address of the microprogram corresponding to each state mode. The outputs of the plurality of compartments are input to a selection circuit selected in state mode, configuring the control store to be addressed by the output of the selected compartment. As described above, the microprogram is controlled by preparing the start address for the microprogram in accordance with the state mode. (Problems to be Solved by the Invention) In the information processing apparatus according to the prior art described above, an improvement has been made in that unnecessary steps in a microprogram can be reduced regarding a group of instructions having a plurality of operations. Since it is necessary to prepare a microprogram start address for each instruction in accordance with the state mode, the start address for an instruction having an operation unrelated to the state mode is redundant. Therefore, there is a drawback that as the number of state modes increases, the amount of redundant hardware increases accordingly. An object of the present invention is to specify a read address using an instruction code, store startup address information of a microprogram in correspondence with each instruction code, and store a plurality of microprograms each consisting of a series of microinstructions. In an information processing device configured such that a microprogram is started using the specified startup address information and the operation of instructions differs depending on the state mode, the state defined in the system architecture that affects the operation of a specific group of instructions. Mask information corresponding to the mode is stored inside the control memory, and the mask information and status mode signal output from the control memory are input to give an AND logical output, and the microprogram output from the control memory is activated. It is an object of the present invention to provide an information processing device configured to eliminate the above-mentioned drawbacks and eliminate the need for redundant hardware by providing a startup address to a control store using address information. (Means for solving the problem) An information processing device according to the present invention includes a control memory,
It comprises an instruction register, a control store, a state register, a pair of AND gates, and an address register. The control memory can specify a read address using an instruction code, and is used to store microprogram start address information and state mask information in correspondence with each instruction code. The instruction register is for storing instructions that give addresses to control memory. The control store is for storing multiple microprograms consisting of a series of microinstructions. The pair of status registers is for indicating a program status mode and a hardware status mode defined in a system architecture configured such that instruction operations differ depending on the status of the system. The pair of AND gates are used to input and gate the state mask information output from the control memory and the outputs of the pair of state registers. The address register is for providing a start address to the control store based on the state-specific mask information output from the pair of AND gates and the start address information of the microprogram output from the control memory. (Example) Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. In Figure 1, 1
2 is a main storage device, 2 is a storage control device, 3 is an instruction control arithmetic unit, 301 is an instruction register, 302 is a control memory, 303 and 304 are each a status register, 305 and 306 are each an AND gate, 3
07 is an address register, and 308 is a control store. In FIG. 1, the instruction control arithmetic unit 3 includes an instruction register 301 for storing instruction words inputted from the main storage device 1 via the storage control device 2, and an instruction code 301a output from the instruction register 301.
is input as an address through the signal line 316, and the activation address information 302a of the control store 308 and the program status register 33 are input in accordance with the instruction code.
A control memory 302 that stores mask information 302b of 03 and mask information 302c of the hardware status register 304 in advance, and a program for displaying "1" and outputting it on the signal line 312 in program status mode M1. A status register 303, a hardware status register 304 for displaying “1” and outputting it on the signal line 313 when in the hardware status mode M2, and a hardware status register 304 for displaying “1” and outputting it on the signal line 313, and transmitting mask information 302b of the control memory 302 to the signal line 31.
0, the program state mode M1 is input via the signal line 312, and an AND gate 305 for outputting the AND operation result of both signals to the signal line 314, and mask information 302c of the control memory 302. Activation of the AND gate 306 and the control memory 302 for inputting the hardware status mode M2 through the signal line 311 and inputting it through the signal line 313, and outputting the AND operation result of both signals to the signal line 315. Address information 302a, output of AND gate 305, and
The output of the AND gate 306 is connected to the signal line 30, respectively.
9, 314, 315 for input and holding, and a control store 308 for outputting the microinstruction addressed in the address register 307 via the signal line 317 to the signal line 318. It has been prepared and configured. Next, the specific capacity of each storage means in the information processing apparatus shown in FIG. 1 will be shown numerically. In FIG. 1, the capacity of control memory 308 is 65,536 words, and address register 307 consists of 16 bits. The instruction code 301a of the instruction register 301 is 8 bits, and the capacity of the control memory 302 addressed by the instruction code 301a is 16 bits x
It is 256 words. Status registers 304, 305
Both are 1-bit registers. FIG. 2 is an explanatory diagram showing the storage state of the control memory 302, where the activation address information 302a is 14 bits, and the mask information 302b and 302c are each 1 bit.
It has a bit structure. Therefore, one word of the control memory 302 contains mask information 302b, 3
There are four possible combinations of 02c. FIG. 3 is an explanatory diagram showing the input state and holding state of the control store 307. The upper 14 bits (bits 0 to 13) contain the activation address information 302a of the control memory 302 given by the signal line 309 in an unmodified state. entered and retained. Bits 14 and 15 are ANDed by signal lines 314 and 315, respectively.
The logical operation results of gates 305 and 306 are input and held. Next, specific operations will be described with reference to FIGS. 1 to 8. Instruction control arithmetic unit 3 in Fig. 1
Up to 256 instructions executed in program state mode M1, as well as hardware state mode M2
Due to the difference in operation, the following
It is classified into four types, A to D, as shown in the table.

[Table] The mask information 302b, 302c of the control memory 302 corresponds to these four types of instructions A to D, and the type A instruction is 302b="0", 302c="
Specified by “0”, type B instructions are 302
Specified by b="1", 302c="0",
Type C instructions are 302b="0", 302c="1"
and the type D instruction is 302b=
"1", designated by 302c="1". FIG. 4 is an explanatory diagram showing the storage state of the control memory 302 corresponding to each representative instruction of the types A to D described above. In FIG. 4, an instruction of instruction code A1 (displayed in hexadecimal, hereinafter, instruction codes are expressed in hexadecimal) as an instruction of type A, as well as an instruction of types B, C,
Instructions with instruction codes B2, C3, and D4 are shown as instructions of D. Bits 0 to 11 of the boot address information in Figure 4 are displayed in hexadecimal, and bits 12 and 13
is displayed in binary. Now, when instructions with instruction codes = A1, B2, C3, and D4 are executed in an environment where the program state mode is M1 = "0" and the hardware state is M = 2 "0", the The contents of registers 303 and 304 in FIG. 1 are both "0". Therefore, the signals on the signal lines 312 and 313 also become "0", and the signals on the output signal lines 314 and 315 of the AND gates 305 and 306 also become "0".
Therefore, "0" is input and held in both bits 14 and 15 of the address register 307 of the control store 308 in FIG. Therefore,
The address register 307 is filled with 1110, 2220, 3330, and 4440 (all expressed in hexadecimal) corresponding to the instructions with instruction codes A1, B2, C3, and D4, along with the input from the startup address information 302a of the control memory 302. The input is held and the microprogram is started. Next, when instructions with instruction codes = A1, B2, C3, and D4 are executed in an environment where the program status mode is M1="1" and the hardware status mode is M2="0", the state Since the contents of the register 303 are “1” and the contents of the status register 304 are “0”, the output of the AND gate 306 is always “0”, and the output of the AND gate 305 is the mask information 302b of the control memory 302. becomes "1" only when is "1". Therefore, judging from Figure 4, the instruction code = B2,
It can be seen that the output of the AND gate 305 becomes "1" only when the command is D4. Therefore, in the address register 307 of the control store 308, 1110, 2222, 3330, and 4442 (all expressed in hexadecimal) are input and held corresponding to the instructions with instruction codes = A1, B2, C3, and D4, respectively. The program is started. Similarly, program state mode is
M1="0" and hardware status mode M2
= “1” and program status mode is M1 =
“1” and hardware status mode is M2=
When the flag is "1", the activation address is modified and given to each type of instruction. FIG. 5 is an explanatory diagram summarizing the above-described modification of the startup address. Figure 5 shows the instruction code of type A.
The microprogram startup address of 1110 (hexadecimal) is given to the A1 instruction regardless of the state mode M1 or M2, and the other type B, C, D instruction codes = B2, C3, D4 instructions Two types and four types of activation addresses are given to the target.
Different activation control of microprograms is possible for instructions that have different operations with respect to the state mode, and for instructions that do not have different operations. (Effects of the Invention) As explained above, the present invention prepares mask information corresponding to the state mode corresponding to the instruction code, so that the start address of the microprogram can be used for instructions whose operations differ depending on the state mode. This has the effect that for instructions whose operation is constant regardless of the state mode, the activation address can be easily unmodified using gate logic.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. FIG. 2 is an explanatory diagram showing the storage state of the control memory shown in FIG. 1.
FIG. 3 is an explanatory diagram showing the input holding state of the address register shown in FIG. 1. FIG. 4 is an explanatory diagram showing a part of the storage state of the control memory in the embodiment of the information processing apparatus according to the present invention. FIG. 5 is an explanatory diagram showing a part of the startup address of the microprogram in correspondence with the state mode in the embodiment of the information processing apparatus according to the present invention. 1...Main storage device, 2...Storage control device, 3...
...Instruction control arithmetic unit, 301...Instruction register,
302... Control memory, 303, 304... Status register, 305, 306... AND gate, 3
07...Address register, 308...Control store, 309-317...Signal line.

Claims (1)

[Claims] 1. A read address can be specified by an instruction code, and a control memory for storing microprogram startup address information and status mask information corresponding to each instruction code, and an instruction for giving an address to the control memory are provided. A system architecture that includes an instruction register for storing instructions, a control store for storing multiple microprograms consisting of a series of microinstructions, and a system architecture that allows instructions to operate differently depending on the state of the system. A pair of status registers for indicating a prescribed program status mode and a hardware status mode, mask information for both the statuses output from the control memory, and outputs of the pair of status registers for input and gate. a pair of AND gates; and an address register for providing a startup address to the control store based on state-specific mask information output from the pair of AND gates and microprogram startup address information output from the control memory. An information processing device comprising: